JP2002118541A - Synchronous clock generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a synchronous clock generating circuit capable of making it unnecessary to provide any phase guaranteeing function in a PLL circuit by performing synchronization control only when phase step-out is generated. SOLUTION: This synchronous clock generating circuit for generating a prescribed clock signal phase-synchronizing with an in-device clock signal by using a PLL circuit, and a frequency-dividing part is provided with a phase detecting means for detecting the phase step-out of the in-device clock signal and the synchronous clock signal based on a phase monitor range setting signal. In this case, only when the phase step-out is detected by the phase detecting means, the frequency-dividing part is reset, and the phase pull-in of the output is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous clock generating circuit for generating a phase synchronous clock used in a multiplex transmission apparatus of a bit interleave multiplex system and the like.
In particular, the present invention relates to a synchronous clock generation circuit that does not require a phase guarantee function in a PLL circuit by performing synchronization control only when phase synchronization is lost.

[0002]

2. Description of the Related Art Generally, in a multiplex transmission apparatus of a bit interleave multiplex system or the like, a phase-synchronized clock phase-synchronized with an internal clock is used for transmission. FIG.
FIG. 1 shows a conventional example of a synchronous clock generation circuit for generating a phase synchronous clock. As shown in FIG. 5, the synchronous clock generation circuit includes a PLL circuit 1 for inputting an internal clock signal (8 kHz) and the internal clock signal (8 kHz).
Hz) together with the signal (155.5) from the PLL circuit 1.
2 MHz) and the PLL circuit 1
Signal (8 kHz differential pulse) from the differentiating circuit 3 together with the input signal (155.52 MHz)
And a frequency dividing circuit 5. Next, the operation of the conventional synchronous clock generation circuit will be described with reference to the operation time chart of FIG. First, when an internal clock signal of 8 kHz is input to the PLL circuit 1, the PLL circuit 1 has a 155.52M phase-locked to the 8 kHz.
A Hz clock signal is generated and output. Next, the above 8
The internal clock signal of 1 kHz and the output signal of 155.52 MHz from the PLL circuit 1 are input to the differentiating circuit 3 and subjected to a differentiating process in the differentiating circuit 3 to 8 k
An Hz differential pulse is generated and output. Next, the PL
An output signal of 155.52 MHz from the L circuit 1 and an 8 kHz differentiated pulse from the differentiating circuit 3 are input to the 1/8 frequency dividing circuit 5, and the 8/8 frequency dividing circuit 5 outputs the 8 k
155.5 based on the timing of the Hz differential pulse.
The 2 MHz signal is frequency-divided by 8 to generate and output a 19.44 MHz signal. That is, in the 1/8 frequency dividing circuit 5, the 8 kHz differential pulse and the 15 kHz signal from the PLL circuit 1 are used.
The phase synchronization with the 5.52 MHz clock was always taken.

[0003]

However, in the above-described conventional synchronous clock generation circuit, since the phase synchronization is always performed, it is necessary to obtain a stable 19.44 MHz synchronous clock signal. It was necessary to stabilize the 155.52 MHz output signal from the PLL circuit 1. That is, the output of the differentiating circuit 3 is susceptible to fluctuations in the 155.52 MHz clock that is the input signal for the differentiation processing, and it is necessary to stabilize the 155.52 MHz output signal. Therefore, the above 155.
In order to stabilize the output signal of 52 MHz, it is necessary to add a function of performing phase assurance including temperature fluctuations in the PLL circuit 1, which is disadvantageous not only in component cost and board mounting surface but also in shipping. There was a problem that the adjustment cost at the time of inspection also increased. SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a synchronous clock generation circuit that does not require a phase guarantee function in a PLL circuit by performing synchronization control only when phase synchronization is lost. And

[0004]

In order to achieve the above object, the present invention provides a synchronous clock generating circuit for generating a predetermined clock signal phase-synchronized with an internal clock signal using a PLL circuit and a frequency divider. Having phase detection means for detecting out-of-phase synchronization between the internal clock signal and the synchronous clock signal based on the phase monitoring range setting signal, wherein the out-of-phase detection is detected by the phase detection means. Only in this case, the frequency divider is reset, and the operation of pulling in the output phase synchronization is performed. Another feature of the present invention is that the phase detection means detects the loss of phase synchronization by determining whether or not a clock edge of the internal clock signal has entered a phase monitoring range set by the phase monitoring range setting signal. It is. Another feature of the present invention is that the phase monitoring range is changed by the phase monitoring range setting signal.

[0005]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described based on illustrated embodiments. FIG. 1 is a configuration diagram showing one embodiment of a synchronous clock generation circuit according to the present invention. As shown in FIG. 1, the synchronous clock generation circuit includes a PLL circuit 7 for inputting an internal clock signal (8 kHz), and a signal (155.52 MHz) from the PLL circuit 7 together with the internal clock signal (8 kHz). And a signal (155.52 MH) from the PLL circuit 7.
z) together with the synchronization detection signal (phase out-of-synchronization signal) from the phase detector 9 and the internal clock signal (8 kHz).
z), and a 1/8 frequency divider 11 for inputting the output signal (19.44 MHz) from the 1/8 frequency divider 11 and a phase monitoring range setting signal. It is to be entered. FIG. 2 is an internal configuration diagram of the phase detection unit 9 shown in FIG. As shown in FIG. 2, the phase detector 9 includes the １ ／ frequency divider 11 and the PLL
The pulse generation circuit 13 connected to the circuit 7, the phase monitoring range setting signal is input, and the selector circuit 15 connected to the pulse generation circuit 13 is input. The internal clock signal (8 kHz) is input. And a phase detection circuit 17 connected to the selector circuit 15.

Next, the operation of the synchronous clock generation circuit shown in FIGS. 1 and 2 will be described with reference to the operation time charts of FIGS. First, when an internal clock signal of 8 kHz is input to the PLL circuit 7, the P
In the LL circuit 7, the phase is synchronized with the above 8 kHz.
A 5.52 MHz clock signal is generated and output. Next, the 8 kHz internal clock signal, the 155.52 MHz output signal from the PLL circuit 7 and the 1/8
The signal (19.44 MHz) from the frequency divider 11 and the phase monitoring range setting signal are input to the phase detector 9. Here, in the phase detection unit 9, 8
When a clock edge of kHz enters, a phase-out-of-phase signal is generated and output (see FIG. 3). On the other hand, if the clock edge of 8 kHz does not fall within the above-mentioned phase monitoring range, the out-of-phase signal is not generated and output (see FIG. 4). The width of the phase monitoring range is changed as indicated by a dotted line (B), and the changing operation will be described later in detail. Next, 15 from the PLL circuit 7
When the 5.52 MHz output signal and the internal clock signal (8 kHz) are input to the 1/8 frequency divider 11 and no phase-out-of-phase signal is input from the phase detector 9, The above-mentioned 155.52M
The Hz signal is frequency-divided by 8 to generate and output a 19.44 MHz signal. On the other hand, when a signal out of phase synchronization is input from the phase detector 9 to the 1/8 frequency divider 11, the 1/8 frequency divider 11 is reset, and the output (19.44 MHz) is output. A phase synchronization pull-in operation is performed. That is, according to the synchronous clock generation circuit, the synchronization control (reset operation) is performed only when the phase synchronization is lost.
Is to be performed.

Here, the phase monitoring operation of the phase detector 9 will be described in more detail with reference to FIG. In FIG. 2, the pulse generation circuit 13 outputs an output signal (19.44 MHz) from the 1/8 frequency divider 11 and the P signal.
The signal (155.52 MHz) from the LL circuit 7 is input and two pulse signals A and B having different pulse widths (FIGS. 3 and 4)
(Corresponding to A and B of the phase monitoring signal shown in FIG. 3) and outputs it. Next, the pulse signals A and B from the pulse generation circuit 13 are input to the selector circuit 15, and one of the pulse signals A and B is selected and output based on the phase monitoring range setting signal. In this selection operation, for example, a pulse signal of A having a narrow pulse width (a wide phase monitoring range) is selected at the rising timing of the synchronous clock generation circuit based on the phase monitoring range setting signal, and after the rising timing, Wide pulse width (narrow phase monitoring range)
The B pulse signal is selected. Next, the phase detection circuit 17 detects whether or not a clock edge of 8 kHz is included in the phase monitoring range based on the pulse signal A or B selected by the selector circuit 15, and detects whether or not the clock edge is 8 kHz within the phase monitoring range. When a clock edge of the clock signal is present (FIG. 3), a phase out-of-synchronization signal is output. Has become.

[0008]

As described above, according to the present invention, the synchronization control is performed only when the phase synchronization is lost.
The phase assurance function in the L circuit becomes unnecessary, which is very advantageous in terms of component cost and board mounting.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating an embodiment of a synchronous clock generation circuit according to the present invention.

FIG. 2 is an internal configuration diagram of a phase detection unit shown in FIG.

FIG. 3 is an operation time chart of the synchronous clock generation circuit shown in FIGS. 1 and 2;

FIG. 4 is an operation time chart of the synchronous clock generation circuit shown in FIGS. 1 and 2;

FIG. 5 is a configuration diagram of a conventional synchronous clock generation circuit for generating a phase synchronous clock.

FIG. 6 is an operation time chart of the conventional synchronous clock generation circuit shown in FIG.

[Explanation of symbols]

1, 7 PLL circuit, 3 differentiator circuit, 5, 11 1/8
Frequency dividing circuit, 9: phase detector, 13: pulse generating circuit, 1
5 selector circuit, 17 phase detection circuit

Claims (3)

[Claims] 1. A synchronous clock generation circuit for generating a predetermined clock signal phase-synchronized with an internal clock signal using a PLL circuit and a frequency divider, wherein the synchronous clock generation circuit generates a predetermined clock signal based on a phase monitoring range setting signal. A phase detection unit for detecting out-of-phase of the clock signal and the synchronous clock signal; the frequency divider is reset only when the out-of-phase is detected by the phase detection unit; A synchronous clock generation circuit wherein a synchronization pull-in operation is performed. 2. The method according to claim 1, wherein the phase detecting means detects the out-of-phase by detecting whether or not a clock edge of the internal clock signal has entered a phase monitoring range set by the phase monitoring range setting signal. 2. The synchronous clock generation circuit according to claim 1, wherein: 3. The synchronous clock generation circuit according to claim 2, wherein said phase monitoring range is varied by said phase monitoring range setting signal.