JPH03278180A - Method and device for logic synthesis - Google Patents

Abstract

PURPOSE:To shorten the design time by automatically generating a conversion rule for synthesis of a corrected logic circuit at the time when the correction reason of the logic circuit to be corrected is true in the case of correction of trouble in the synthesized logic circuit. CONSTITUTION:A new conversion rule generating part 10 generates the conversion rule, by which the logic circuit whose trouble is corrected is accurately synthesized in accordance with inputted function specification information, based on information given from a correction information storage part 8 and information given from a conversion history storage part 9. The generated conversion rule is registered without contention to already prepared conversion rules. thus, the conversion rule is corrected and added without manual operation to not only reduce the burden to a designer but also shorten the design time.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a logic synthesis method and device for synthesizing logic circuits according to conversion rules, and particularly relates to The present invention relates to a logic synthesis method and apparatus for automatically creating conversion rules for logic synthesis of a logic circuit after modification.

(Conventional Technology) Manually installing the detailed logic of an LSI is usually a task that requires a great deal of effort and time. For this reason, conventionally, such work has been performed by a logic synthesis device using a computer.

The logic synthesis device inputs functional specification information of a circuit to be logically designed, sequentially converts this information according to conversion rules, and synthesizes a logic circuit that realizes the previously input functional specifications. Conversion rules consist of rules necessary to generate a logic circuit from functional specification information, and are given to the device as a knowledge base of a group of conversion rules.

If a defect occurs that does not satisfy the designer in a logic circuit synthesized by such a logic synthesis device, the input functional specification information is converted into a logic circuit. There is a problem with the conversion rules. Therefore, even if the defective part is corrected to the designer's satisfaction after logic synthesis, the same defect will occur when logic synthesis is performed again. That is, when the functional specification information is corrected and logic synthesis is executed again, the same correction has to be made again.

Therefore, in order to obtain a logic circuit that does not cause any defects, it is necessary to modify or add conversion rules.

When modifying or adding conversion rules, first consider the synthesis process from the input functional specification information to the synthesis of the logic circuit, and identify the conversion rules that caused defects in the synthesized logic circuit. Find out. Next, modify this conversion rule so that the problem does not occur, or if the problem cannot be solved by modifying the conversion rule alone, create a new conversion rule based on the existing conversion rule, and then modify the existing conversion rule. Additional registration for. Thereafter, a series of extremely labor-intensive tasks must be performed, such as performing logic synthesis again to ensure that a fault-free logic circuit is synthesized.

Traditionally, this kind of work was performed by designers.

Therefore, the designer is forced to perform extra work in addition to the original work of logic synthesis.

Furthermore, by performing such work, unnecessary time is spent on logic synthesis, and logic synthesis takes time.

(Problem to be solved by the invention) As explained above, in the conventional logic synthesis device,
In order to eliminate defects that occur in synthesized logic circuits, designers must either correct the defects each time they occur, or modify or add the conversion rules that caused the defects. I was doing it. Therefore, in addition to the logic synthesis work, the designer has to perform secondary labor-intensive work, which places a heavy burden on the designer. Furthermore, performing such work requires a large amount of time for logic synthesis.

Therefore, this invention was made in view of the above,
The purpose of this is to provide a logic synthesis method and device that enables modification and addition of conversion rules without human intervention, significantly reducing the burden on designers, and contributing to shortening the design period. Our goal is to provide the following.

[Structure of the Invention (Means for Solving the Problems) In order to achieve the above object, the invention according to claim 1 provides a logic synthesis device that synthesizes a logic circuit from input design information according to a conversion rule. a storage means for storing conversion history information consisting of circuit conversion history and conversion rules in the logic synthesis process; a correction means for correcting the logically synthesized logic circuit together with an input of a reason for correction; and a correction means for correcting the logic circuit corrected by the correction means. an extraction means for extracting conversion history information from the storage means; and a modified circuit information extracted by the extraction means, the circuit information after modification modified by the pre-modification means, and the modification reason when the modification reason is established. It is comprised of a creation means for creating a conversion rule for synthesizing a logic circuit, and a registration means for registering the conversion rule created by the creation means so as to avoid conflict with existing conversion rules.

(Operation) In the above configuration, the invention of claim 1 corrects the logically synthesized logic circuit together with the input of the reason for correction, and provides a conversion rule and a circuit conversion history for synthesizing the logic circuit configuration before and after the correction and the logic circuit before the correction. Based on the analysis results, if the reason for modifying the logic circuit is established, a conversion rule is created to synthesize the modified logic circuit, and the created conversion rule is combined with the existing conversion rule. I try to avoid conflicts when registering.

(Example) Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a diagram showing the configuration of an apparatus for performing logic synthesis using a logic synthesis method according to an embodiment of the present invention. The logic synthesis device of the embodiment shown in the figure searches for the conversion rule that caused a defective part in the synthesized logic circuit from the history of conversion rules related to the synthesis of logic circuits, and corrects this conversion rule. Alternatively, new conversion rules can be created and added within the device.

In FIG. 1, the logic synthesis device includes an input section 1, a circuit information storage section 2, a logic synthesis processing section 3, a conversion rule storage section 4, and an output section 5.

The human power section 1 provides the device with functional specification information consisting of connection information indicating the function and human output relationship of the circuit to be logically synthesized. The functional specification information input from the input section] is given to the circuit information storage section 2.

The circuit information storage section 2 stores the functional specification information given from the input section 1 and the configuration of the synthesized logic circuit given from the logic synthesis processing section 3 as circuit information. The circuit information stored in the circuit information storage section 2 is given to the output section 5, and among the circuit information, functional specification information is given to the logic synthesis processing section 3.

The logic synthesis processing unit 3 converts the functional specification information given from the circuit information storage unit 2 into a circuit according to conversion rules, and synthesizes a logic circuit that realizes the functional specification information from the functional specification information. Further, the logic synthesis processing section 3 provides the circuit information of the logically synthesized logic circuit to the circuit information storage section 4. Further, the logic synthesis processing section 3 outputs the conversion rule used in the process of synthesizing the logic circuit and the history of circuit conversion performed using this conversion rule.

The conversion rule storage unit 4 stores a plurality of conversion rules necessary for synthesizing a logic circuit from functional specification information.
The stored conversion rules are provided to the logic synthesis processing section 3 in response to a request from the logic synthesis processing section 3.

The output unit 5 outputs and displays information necessary for logic synthesis and modification of conversion rules, and additional work, as well as circuit information stored in the circuit information storage unit 2.

For example, when modifying a conversion rule, the circuit in which the defect occurs, the circuit in which the defect has been corrected, and the reason for the correction are output and displayed.

In addition to the above-mentioned components, the logic synthesis device of this embodiment includes:
It includes a modification section 6, a modification information extraction section 7, a modification information storage section 8, a conversion history storage section 9, a conversion rule creation section 10, a conversion rule storage section 11, and a new conversion rule installation section 12.

The correction unit 6 corrects the defective portion of the logical circuit synthesized and displayed on the output unit 5, and inputs the reason for the correction. Information on the partial circuit including the reason for modification and the modified parts before and after modification is provided to the modification information extraction unit 7.

The modification information extraction section 7 extracts the circuit information of the partial circuit modified by the modification section 6 from the circuit information storage section 2, and stores the extracted circuit information in the modification information storage section 8 together with the modification reason inputted to the modification section 6. give.

The modification information storage section 8 stores the circuit information and modification reason extracted by the modification information extraction section 7, and provides the stored circuit information and modification reason to the new conversion rule creation section 10.

The conversion history storage unit 9 stores conversion rules and circuit conversion history in the logic synthesis process output from the logic synthesis processing unit 3 described above, and stores the stored information in the new conversion rule creation unit 1.
Give to 0.

0 The new conversion rule creation unit 10 accurately synthesizes the logic circuit in which the defect has been corrected from the input functional specification information based on the information provided from the correction information storage unit 8 and the information provided from the conversion history storage unit 9. Create a conversion rule for

The new conversion rule creation unit 10 first searches the circuit conversion history of the synthesis process for the circuit conversion that caused the defect based on the reason for modification and the conversion rule that performed this circuit conversion.

Then, this conversion rule is modified so that different conversion operations are performed depending on whether the reason for modification is successful or not. Further, if the conversion rule necessary for synthesizing the corrected logic circuit when the reason for modification is satisfied is not found in the existing conversion rule group, a new conversion rule for synthesis is created. The new conversion rule created in this way is given to the new conversion rule storage section 12.

The new conversion rule storage section 11 stores the new conversion rule created by the new conversion rule creation section 10, and provides the stored new conversion rule to the new conversion rule incorporation section 12.

1 The new conversion rule incorporation unit 12 provides the new conversion rule to the conversion rule storage unit 4 in such a way that the new conversion rule provided from the new conversion rule storage unit 11 avoids conflict with the existing conversion rule group. Store.

Next, the operation of the above embodiment will be explained with reference to the flowchart shown in FIG.

First, the functional specification information given from the input section 1 is converted into a circuit by the logic synthesis processing section 3 according to the conversion rule given from the conversion rule storage section 4 and synthesized into a logic circuit. At this time, the conversion history of the synthesis process is provided from the logic synthesis processing section 3 to the conversion history storage section 9 and stored therein.

It is examined whether the logic circuit synthesized and displayed on the output section 5 has any unsatisfactory points for the designer (step 100). If there are no unsatisfactory points, no corrections or additional work will be made to the conversion rules, but if there are any unsatisfactory points, the unsatisfactory points will be corrected by the designer in the modification section 6, and the reason for the modification will be explained. is input from the correction unit 6 (steps 110 and 120).

2 For example, as shown in FIG.
ND” and the modified partial circuit B, the circuit information of the partial circuit A and the partial circuit B is extracted from the circuit information storage unit 2 by the modified information extraction unit 7, and the extracted circuit information and the modified circuit information are extracted from the circuit information storage unit 2 by the modified information extraction unit 7. The reason "C0ND" is given to and stored in the modification information storage section 8. The information stored in the modification information storage section 8 is given to the new conversion rule creation section 10, so that when the partial circuit A is synthesized, The conversion history is given from the conversion history storage section 9 to the new conversion rule creation section 10.

For example, when a conversion history as shown in FIG. 4 is given to the new conversion rule creation unit 10, the conversion rule R□ that caused the problem is selected from the conversion history as the logic circuit before and after modification. Focus on and find differences (Step 14)
0).

As shown in FIG. 5, the found conversion rule Rffi is modified to a conversion rule RII 3 so as to perform a different conversion depending on the success or failure of the modification reason "C0ND" (step 150). Furthermore, the modified partial circuit B
Conversion rules required to synthesize Rm + 1'~R
1' is newly created (step 160). Therefore, when the modification reason "C0ND" is established, the conversion rule R□4 is applied after the conversion rule R□' is applied as shown in FIG. ' to R,' are sequentially applied to synthesize a partial circuit B in which no defective points exist. In addition, the reason for the modification “C”
0ND'' does not hold, the conversion rule R0' is applied, and then the conversion rules R4,1 to Ro+1 are sequentially applied as before to synthesize the partial circuit A.

New conversion rule R□R01′ created in this way
R1' is given to and stored in the new conversion rule storage unit 1], and the stored new conversion rule is stored in the new conversion rule embedding unit 12.
given to. It is checked whether the new conversion rule given to the new conversion rule incorporation unit 12 conflicts with the existing conversion rule group stored in the conversion rule storage unit 4 (step 170), and if there is a conflict, , the new conversion rule is modified to avoid conflicts (step 180), and the revised new conversion rule is registered in the conversion rule storage unit 4 and incorporated into the existing conversion rules (step 190).
. On the other hand, if there is no conflict, the created new conversion rule is registered in the conversion rule storage section 4 and incorporated into the existing conversion rule. Note that if there are any equivalent conversion rules among the existing conversion rules, the created new conversion rule will not be incorporated.

Such operations are repeated until there are no unsatisfactory points in the synthesized logic circuit, and each time the conversion rule that caused the unsatisfactory point is modified or added, and a new conversion rule is created.

Next, the process of creating a new conversion rule will be explained using a specific example.

For example, in order to synthesize a 5-bit multiplexer from the input section 1, when functional specification information of the 5-bit multiplexer as shown in FIG. 6(a) is given by graphic input,
The conversion rule r1 is applied to this functional specification information, and the logic synthesis processing section 3 converts the circuit as shown in FIG. 6(b). In other words, for a 55-bit multiplexer, the manpower is divided into two bits each, resulting in two 2-bit multiplexers and one 1-bit multiplexer.
It consists of a juxtaposition of bit multiplexers.

Next, the conversion rule r2 is applied to such a configuration, and a 5 bi·yt□ multiplexer is logically synthesized as shown in FIG. 6(C). That is, the 2-bit multiplexer shown in FIG. 6(b) is converted into a cell α2 in the library, and the 1-bit multiplexer is converted into a cell α1. In FIG. 6(C), each cell α2, α1 receives an input (AIA
2. Bl, B2) is selected and given to the output (Zl, Z2).

In this way, the 5-bit multiplexer is shown in Figure 6(C).
The signals are logically synthesized and displayed on the output section 5 as shown in FIG. At this time, it is assumed that cell α4 of the 4-bit multiplexer shown in FIG. 8 is available in the library. Therefore, the designer was dissatisfied with the fact that a 2-bit multiplexer was used even though a 4-bit multiplexer could be used, so he decided to use cell α4 of the 4-bit multiplexer.
The configuration shown in FIG. 6(C) is modified to a configuration in which cell α4 and cell α1 are juxtaposed as shown in FIG.

By performing such correction, the circuit information of the circuits shown in FIGS. 6(C) and 9 and the reason for the correction that "cell α4 can be used" are provided to the correction information storage section 8 and stored therein.

Further, the conversion history of the 5-bit multiplexer shown in FIG. 6 is given from the conversion history storage section 9 to the new conversion rule creation section 10, and the modified circuit shown in FIG. 9 and the conversion history shown in FIG. A comparison will be made.

Focusing on the difference between the circuits before and after the modification, which is that the 2-bit multiplexer has been changed to a 4-bit multiplexer, if cell α4 is available, the existing method of ``dividing the functional element multiplexer into every 2 bits'' will be considered. The conversion rule r1 is modified to ``If cell α4 is available, divide the functional element multiplex into every 4 bits,'' and a new conversion rule r1' is created as shown in FIG.

Similarly, the conversion rule r2 is modified to "convert the functional element 4-bit multiplexer to the cell α4", and a new conversion rule r2' is created as shown in FIG.

New conversion rule r]-1r2′ created in this way
When is registered and incorporated into the conversion rule storage unit 4,
Existing conversion rule r1. ．． r2 and new conversion rule rl',
existing transformation rules rl so that r2' works together.
, r2 are the new conversion rules rl', r as shown in FIG.
2', and are registered and incorporated into the conversion rule storage unit 4 as conversion rules rl and r2.

In this way, the conversion rules are modified and added, so that when the 5-bit multiplexer is logically synthesized again, it will be possible to synthesize the circuit shown in Figure 9 that satisfies the designer. become.

[Effects of the Invention] 8. As explained above, according to the present invention, when a defect occurring in a synthesized logic circuit is corrected, if the reason for the correction of the corrected logic circuit is established, the corrected Since conversion rules for synthesizing logic circuits are automatically created, conversion rules can be modified and added without manual intervention. This greatly reduces the burden on designers,
It becomes possible to shorten the design period.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a logic synthesis device according to an embodiment of the invention, FIG. 2 is a flowchart showing the operation of the device shown in FIG. 1, and FIGS. 3 to 11 are shown in FIG. 1. FIG. 3 is a diagram for explaining a correction operation of the device. DESCRIPTION OF SYMBOLS 1... Input part, 2... Circuit information storage part, 3... Logic synthesis processing part, 4... Conversion rule storage part, 5... Output part, 1 6... Correction part, 7. Modification information extraction section, 8. Modification information storage section, 9. Conversion history storage section, 10. New conversion rule creation section, 11. New conversion rule storage section, 12. New conversion Rule memory section.

Claims (2)

[Claims] (1) In a logic synthesis method that synthesizes a logic circuit from input design information according to conversion rules, the synthesized logic circuit is modified along with the input of the reason for modification, and the logic circuit configuration before and after modification and the logic before modification are Analyze the conversion rules for synthesizing the circuit and the circuit conversion history, and based on the analysis results, if the reason for the modification is established when modifying the logic circuit, create a conversion rule to synthesize the modified logic circuit. A logic synthesis method characterized in that a converted conversion rule is registered in such a way as to avoid conflict with an existing conversion rule. (2) In a logic synthesis device that synthesizes a logic circuit from input design information according to conversion rules, a storage means for storing conversion history information consisting of a circuit conversion history and conversion rules in the logic synthesis process, and a logic synthesized logic modifying means for modifying a circuit while inputting a reason for modification; extracting means for extracting conversion history information of the logic circuit modified by the modifying means from the storage means; and converting history information extracted by the extracting means and the modification. creating means for creating a conversion rule for synthesizing a modified logic circuit based on the corrected circuit information modified by the means and the reason for modification when the reason for modification is satisfied; 1. A logic synthesis device comprising: a registration means for registering in a manner to avoid conflicts with rules.