JPH03277076A - Video signal processing circuit - Google Patents

Abstract

PURPOSE:To realize clamping without damaging a back porch of a video signal by applying delay detection to a trailing edge of a horizontal synchronizing signal of the video signal and a horizontal synchronizing pulse and stopping the clamping of a clamp circuit with the output of the detection. CONSTITUTION:An input of a switch circuit 8 is connected to an output of a synchronizing signal separator circuit 5 and the output is connected to a control input of a clamp circuit 2 and an input of a delay circuit 14, connection is controlled by a comparator 7 and opened when a difference is smaller than a DC level to interrupt a horizontal synchronizing pulse being an output of the synchronizing separator circuit 5. The output of the delay circuit 14 is inputted to the control input of the comparator 12 being a component of the clamp circuit 13 and the comparator 12 is operated subsequently by the output of the delay circuit 14. That is, the comparator 12 applies comparison for a period only when the horizontal synchronizing pulse from the switch circuit 8 delayed by a prescribed quantity at the delay circuit 14 is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video signal processing circuit, and more particularly to a video signal processing circuit that clamps the leading end of a synchronization signal in a video signal to a constant potential.

(Prior Art) Conventionally, for example, home video magnetic recording and reproducing devices (hereinafter referred to as VTRs) have been used.
video signal processing that clamps the tip of the horizontal synchronization signal (hereinafter referred to as the sync chip) in the video signal to a predetermined DC potential in order to prevent the brightness level of the video signal from changing during recording and playback. circuit is used.

FIG. 4 is a block diagram of a conventional example of a video signal processing circuit.

During VTR playback, the FM-modulated video signal is demodulated into a video signal by the signal processing circuit 1, and then sent to the clamp circuit 2.
, are input to the level shift circuit 9 via the signal processing circuit 3. Level shift circuit 9, output circuit 10, comparator 12
, and the smoothing circuit 11 constitute a negative feedback type clamp circuit 13, which outputs a video signal from the output point of the output circuit 10.

The operation of the clamp circuit 13 will be explained. Output circuit 1
The comparator 12 compares the sync tip level in the output video signal of 0 with a preset DC potential. At this time, in order to operate the comparator 12 only during the horizontal synchronization signal period, the comparator 12 Give the operating point for .

A comparator 12 compares the sync tip level in the video signal with a predetermined DC potential, and the output thereof is smoothed by a smoothing circuit 11 and used as a DC level shift amount control signal for the level shift circuit 9.

That is, when the sync tip level in the output video signal is higher than a predetermined DC potential, the level shift circuit 9 lowers the sync tip level, and also adjusts the sync tip level in the output signal to a predetermined DC potential. If it is lower than , the level shift circuit 9 controls the sync tip level to be higher. In this way, the sync tip level of the output video signal is maintained at a constant DC potential.

FIG. 5 is a waveform diagram showing the operation of the conventional example shown in FIG. The figure (a) is the output of the signal processing circuit 1, the figure (b) is the LPF
(C) is the output of the synchronization signal separation circuit 5 (horizontal synchronization pulse), (d) is the horizontal synchronization pulse whose delay has been adjusted to give an operating point to the comparator 12. , (e) shows the output of the output circuit 10. The synchronization signal separation circuit 5 converts the horizontal synchronization signal part in the video signal delayed by the LPF 4 into the V-engine 9. The pulse shown in FIG. 5(C) is generated during the period when the DC potential of the input signal is less than 78. This pulse generation period,
The clamp circuit 2 controls the input video signal to a predetermined Vc.
It is clamped to a DC potential and output. Similarly, the comparator 12 is operated, and the clamp circuit 13 causes the output circuit 10 to
The sync chip level of the video signal output from the sync chip is clamped to a predetermined DC potential of Vc. here,
Output horizontal synchronization pulse of synchronization signal separation circuit 5 and output circuit 1
In order to match the delay (ΔT in FIG. 5(d)) with the output video signal of 0, the output point of the synchronizing signal separation circuit 5 and the comparator 12
A delay circuit 14 is provided between the input points of , and timing adjustment is performed. In the case of a VTR, the signal processing circuit 1 performs FM demodulation processing, and the signal processing circuit 3
Then, de-emphasis processing or the like is performed.

[Problem to be solved by the invention]

In the conventional video signal processing circuit described above, the clamp circuit 1
In order to stably generate a horizontal synchronizing pulse by the synchronizing signal separation circuit 5 which provides an operating point to the comparator 12 constituting the video signal 43, the horizontal synchronizing pulse portion in the video No.
Since the video signal is delayed by the LPF 4 before slicing at 7H, the output horizontal synchronization pulse of the synchronization signal separation circuit 5 is also delayed, as shown in FIG. 5(c). Not only does it clamp only the sync tip level in the video signal, but it also clamps a part of the pack pouch, damaging the video signal. At this time, the back pouch of the output video signal from the output circuit 10 Color subcarrier reference signal (color burst signal)
is superimposed, which also affects the color burst signal, making it impossible to accurately reproduce the video signal.

An object of the present invention is to provide a video signal processing circuit that performs a clamping operation without damaging the back porch of the video signal.

[Means to solve the problem]

The video signal processing circuit of the present invention includes a clamp circuit to which a video signal is input, a low-pass filter to which the output of the clamp circuit is input, and the output of the low-pass filter is input, and a horizontal synchronizing pulse is detected from the video signal. a subtracter that takes the difference between the input signal and the output signal of the low-pass filter; a delay circuit that operates while the horizontal synchronization pulse is output from the synchronization signal separation circuit, and clamps the difference. a first comparator for comparison with a predetermined first DC potential smaller than a sync tip clamp potential in the circuit; an input connected to the output of the synchronization signal separation circuit; connected and controlled by the first comparator;
a switch circuit that turns off when the DC potential of an output circuit; a second comparator that operates while the horizontal synchronization pulse is output from the delay circuit and compares the sync tip level in the output video signal of the output circuit with a predetermined second DC potential; The comparison output of the comparator is smoothed, and if the sync tip level in the output video signal is higher than the second DC potential, the level shift circuit or the sync level is reduced. and a smoothing circuit that controls the level shift circuit so that the level shift circuit increases the sync tip level when the level shift circuit is lower than the second DC potential.

[Function] The present invention uses a horizontal synchronization pulse that is delayed and generated for the horizontal synchronization signal portion in the input video by the LPF placed before the synchronization signal separation circuit, and adds a sync chip to the output video signal. When performing a clamp operation, the delay amount of the horizontal synchronizing pulse is detected and the horizontal synchronizing pulse to the d-period clamp circuit is cut off.

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a video signal processing circuit according to a first embodiment of the present invention.

In FIG. 1, parts having the same functions as those in the conventional example shown in FIG. 3 are given the same numbers. The differences from the conventional example will be explained. The subtracter 6 takes the difference between the input signal and the output signal of the LPF 4. The comparator 7 operates while the horizontal synchronizing pulse is output from the synchronizing signal separation circuit 5, and calculates the difference as follows.
Sync tip clamp potential Vc in clamp circuit 2
DC level VT such that V TRI < V c,
, compared with . The switch circuit 8 has an input connected to the output of the synchronizing signal separation circuit 5, an output connected to the control input of the clamp circuit 2 and the input of the delay circuit 14, and is controlled by the comparator 7, so that the difference is set to the DC level VT.

It is turned off for a shorter period of time to cut off the horizontal synchronization pulse that is the output of the synchronization separation circuit 5. The output of the delay circuit 14 is input to the control input of the comparator 12 constituting the clamp circuit 13, and the output of the delay circuit 14 causes the comparator 12 to operate dependently. That is, the comparator 12 performs the comparison operation only during the period when the horizontal synchronizing pulse from the switch circuit 8 is generated, which is delayed by a predetermined time by the delay circuit 14.

FIG. 2 is a wave IF diagram showing the operation of the embodiment of FIG. 1. Figure 2 (a) is the output of the signal processing circuit 1, Figure 2 (b)
is the output of the LPF 4, FIG. 2(C) is the output of the subtracter 6, FIG. 2(d) is the output of the synchronizing signal separation circuit 5, and FIG. 2(e)
is the output of the comparator 7, FIG. 2(f) is the output of the switch circuit 8, FIG. 2(g) is the output of the delay circuit 14, and FIG. 2(h)
indicates the output of the output circuit 10, that is, the output of the clamp circuit 13.

The comparator 7 detects the delay period for the recovery part of the horizontal synchronizing signal in the input video signal of the horizontal synchronizing pulse (FIG. 2(e)), and the comparison output of the comparator 7 controls the switch circuit 8. During the delay period, the horizontal synchronizing pulses to the clamp circuit 2 and the delay circuit 14 are cut off, so the clamp circuit 13 including the comparator 12 which uses the output of the delay circuit 14 as a control signal controls the back-up of the input video signal. Do not make any clamp movements within the range of the pouch period.

FIG. 3 is a block diagram of a second embodiment in which the present invention can be used for both EE monitoring during reproduction and recording of a VTR.

A switch circuit 17 is provided at the input point of the clamp circuit 13. During playback, the switch circuit 17 is selected to the "playback" side, and the playback video signal from the playback system signal processing circuit 15 is input to the clamp circuit 13, and during recording, the switch circuit 17 is set to the "playback" side. , switch circuit 17
is selected to the "EE (recording)" side, and the video recording signal processed by the EE, f-signal processing circuit 16 is sent to the clamp circuit 1.
3 as an EE monitor signal. By changing the signal processing circuit as described above, the same clamp circuit can be used in both motes.

Note that the present invention can produce similar effects not only in video signal processing in a VTR but also in other video fields.

〔Effect of the invention〕

As explained above, the present invention detects the delay between the trailing edge of the horizontal synchronizing signal of the video signal and the horizontal synchronizing pulse, and uses this output to stop the clamping operation of the clamp circuit, thereby detecting the hack pouch of the video signal. without any damage
A clamping operation is realized, which has the effect of not only preventing level fluctuations in the luminance signal but also eliminating the influence on the color burst signal superimposed on the hack pouch area.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the video signal processing circuit of the first embodiment of the present invention, Fig. 2 is a waveform diagram showing the operation of the embodiment of Fig. 1, and Fig. 3 is a block diagram showing the video signal processing circuit of the first embodiment of the invention. FIG. 4 is a block diagram showing the embodiment, FIG. 4 is a block diagram showing the conventional example, and FIG. 5 is a waveform diagram showing the operation of the conventional example shown in FIG. 1.3...Signal processing circuit, 2.13...Clamp circuit, 4...LPF. 5... Synchronous signal separation circuit, 6... Sas reduction device, 7.12... Comparator, 8.17... Switch circuit, 9... Level shift circuit, 10... Output circuit, 11... Smoothing circuit, 14... Delay circuit, 15.18... Reproduction system signal processing circuit, EE system low signal processing circuit

Claims (1)

[Claims] 1. A clamp circuit to which a video signal is input; a low-pass filter to which the output of the clamp circuit is input; and the output of the low-pass filter is input, and a horizontal synchronizing pulse is detected from the video signal. a sync signal separation circuit; a subtracter that takes the difference between the input signal and the output signal of the low-pass filter; a delay circuit; and a clamp circuit that operates while the sync signal separation circuit outputs a horizontal sync pulse; a first comparator for comparison with a predetermined first DC potential that is smaller than the sync tip clamp potential at the sync tip; is controlled by the first comparator, and the first
a switch circuit that turns off when the DC potential is lower than the DC potential of the horizontal synchronization pulse, which is the output of the synchronization separation circuit; a level shift circuit that receives the output of the clamp circuit; and an output circuit that outputs the output of the level shift circuit. a second comparator that operates while the horizontal synchronizing pulse is output from the delay circuit and compares the sync tip level in the output video signal of the output circuit with a predetermined second DC potential; The second DC voltage of the sync tip level in the output video signal is smoothed so that the level shift circuit reduces the sync level when the sync chip level in the output video signal is higher than the second DC potential. and a smoothing circuit that controls the level shift circuit so that the level shift circuit raises the sync tip level when the level is lower than the sync tip level.