JPH03276746A - High frequency semiconductor device - Google Patents
High frequency semiconductor deviceInfo
- Publication number
- JPH03276746A JPH03276746A JP7758890A JP7758890A JPH03276746A JP H03276746 A JPH03276746 A JP H03276746A JP 7758890 A JP7758890 A JP 7758890A JP 7758890 A JP7758890 A JP 7758890A JP H03276746 A JPH03276746 A JP H03276746A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- high frequency
- power supply
- frequency signal
- grounding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 22
- 230000008054 signal transmission Effects 0.000 claims description 10
- 241000612182 Rexea solandri Species 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、高周波用半導体装置に関し、特に入力信号や
出力信号等に生じるクロストークを抑圧するものに関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high-frequency semiconductor device, and particularly to one that suppresses crosstalk occurring in input signals, output signals, and the like.
［従来の技術］
従来、上記の高周波用半導体装置には、例えばプラスチ
ックモールドパッケージに封止したものがあり、そのモ
ールド前の状態＠−例を第３図に示す。同図において、
９は高周波帯で動作する半導体集積回路装置で、例えば
高周波分周器である。１０は、この半導体集積回路装置
９が載置されるフレームで、電源電圧印加端子用リード
部８″接地用リード部２′″、３〜．６′″、７〜、入
力端子用リード部ｌ″、入力基準信号端子用リード部４
−１出力端子用リード部５〜を有している。なお、半導
体集積回路装置９は、へンダ等のダイボンド材によりフ
レーム１０に固着されている。また、接地用リード部２
′、３″、６〜．７′″は、フレーム１０と共通となっ
ている。１１は、上記の各リード部と、これに対応する
半導体集積回路９の対応する端子とを接続するワイヤで
ある。[Prior Art] Conventionally, the above-mentioned high frequency semiconductor device has been sealed in, for example, a plastic mold package, and an example of the state before molding is shown in FIG. In the same figure,
Reference numeral 9 denotes a semiconductor integrated circuit device that operates in a high frequency band, such as a high frequency frequency divider. Reference numeral 10 denotes a frame on which the semiconductor integrated circuit device 9 is mounted, and includes a power supply voltage application terminal lead portion 8'', a grounding lead portion 2'', 3-. 6''', 7~, input terminal lead part l'', input reference signal terminal lead part 4
-1 output terminal lead portion 5 is provided. Note that the semiconductor integrated circuit device 9 is fixed to the frame 10 with a die-bonding material such as solder. In addition, the grounding lead part 2
', 3'', and 6 to .7'' are common to the frame 10. Reference numeral 11 denotes a wire that connects each of the above lead parts and the corresponding terminal of the corresponding semiconductor integrated circuit 9.
［発明が解決しようとする課題］
従来、入力端子用リート部１〜、入力基準信号端子用リ
ード部４″には、ＩＧＨ，程度の周波数の信号か入力さ
れていたか、高周波化か進むにつれて、２Ｇｌｂ以」−
の周波数の高周波信号か入力されるようになってきた。[Problems to be Solved by the Invention] Conventionally, a signal with a frequency of about IGH has been input to the input terminal lead part 1 to the input reference signal terminal lead part 4'', but as the frequency becomes higher, More than 2 Glb”-
Nowadays, high-frequency signals with a frequency of
ところか、第３図に示すようなものては、入力端子用リ
ート部１″′、入力基準信号端子用リート部４″′か隣
接していると、両す−１〜部１−１４″″間の容量な通
して、クロストークか発生する。このクロストークは、
入力信号及び入力基準信号の周波数か高くなればなるほ
ど大きくなるのて、入力信号や入力基準信号としてレベ
ルか、より大きな信号を入力しなければ動作しないとい
う問題点かあった。また出力端子用リー１へ部５″も電
源電圧印加端子用リート部８−と、隣接することにより
電源ラインのノイズの影響を受けるという問題点もあっ
た。On the other hand, in the case shown in FIG. 3, if the input terminal reat part 1"' and the input reference signal terminal reat part 4"' are adjacent to each other, both parts -1 to 1-14" Crosstalk occurs through the capacitance between the two. This crosstalk is
The higher the frequency of the input signal and the input reference signal, the higher the frequency, so there was a problem that it would not work unless a higher level signal was input as the input signal or input reference signal. Furthermore, since the output terminal lead part 5'' is adjacent to the power supply voltage application terminal lead part 8-, there is a problem in that it is affected by noise from the power supply line.
本発明は上記の問題点を解決した高周波用半導体装置を
提供することを目的とする。An object of the present invention is to provide a high frequency semiconductor device that solves the above problems.
［課題を解決するだめの手段コ
上記の目的を達成するために、本発明は、高周波帯て動
作する半導体集積回路装置と、この半導体集積回路装置
か載置され、半導体集積回路装置に対する複数の高周波
信号伝送用リート部と、電源供給用のり一ト部と、接地
用リード部とを有しているフレームと、各リート部と半
導体集積回路装置の対応する端子とを接続しているワイ
ヤとを、具備し、複数の高周波信号伝送用リート部間及
び高周波信号伝送り−ト部と電源供給用のり−上部間に
それぞれ１つ以」二の接地用リー１へ部を設けたことを
特徴とするものである。[Means for Solving the Problems] In order to achieve the above object, the present invention provides a semiconductor integrated circuit device that operates in a high frequency band, a semiconductor integrated circuit device on which the semiconductor integrated circuit device is mounted, and a plurality of A frame having a REET part for high frequency signal transmission, a glue part for power supply, and a grounding lead part, and a wire connecting each REET part to a corresponding terminal of a semiconductor integrated circuit device. It is characterized by having at least one or two sections connected to the grounding wire 1 between the plurality of high frequency signal transmission wire sections and between the high frequency signal transmission wire section and the power supply layer upper part. That is.
［作用］
本発明によれば、高周波信号伝送用リート部間及び高周
波信号伝送用リート部と電源供給用のリート部との間に
は、接地用リート部か設けられているのて、高周波信号
伝送用及び電源供給用のリート部は、それぞれシールド
され、クロストークや電源ノイズの影響は生しない。[Function] According to the present invention, since the grounding reat portion is provided between the high-frequency signal transmission reat portions and between the high-frequency signal transmission reat portion and the power supply reat portion, the high-frequency signal The transmission and power supply REIT sections are each shielded to prevent the effects of crosstalk and power supply noise.
［実施例］
第１図及び第２図に、本発明の一実施例を示す。第２図
において、１２はプラスチックモールドで、その内部に
従来のものと同様にフレーム１０」二に載置された半導
体集積回路装置９か収容されている。１′乃至８′は外
部リート端子である。[Example] FIGS. 1 and 2 show an example of the present invention. In FIG. 2, reference numeral 12 denotes a plastic mold, and a semiconductor integrated circuit device 9 mounted on a frame 10''2 is accommodated therein, as in the conventional mold. 1' to 8' are external lead terminals.
フレーム１０は、第１図に示すように構成されており、
電源電圧印加端子用リート部８、接地用リード部２．３
．６．７、入力端子用リート部ｌ、入力基準信号端子用
リード部４、出力端子用り−ト部５を有している。接地
用リート部２．３．６．７は、フレーム１０と共通とさ
れ、これらリート部ｌ乃至８は、第２図に示す外部リー
ト端子１′乃至８′の対応するものにそれぞれ接続され
ている。The frame 10 is constructed as shown in FIG.
Lead part 8 for power supply voltage application terminal, lead part 2.3 for grounding
．． 6.7. It has a lead part 1 for input terminal, lead part 4 for input reference signal terminal, and lead part 5 for output terminal. The grounding REEAT part 2.3.6.7 is common to the frame 10, and these REEAT parts 1 to 8 are respectively connected to corresponding ones of the external REET terminals 1' to 8' shown in FIG. There is.
第１図から明らかなように、入力端子用リート部１と入
力基準信号端子用リード部４との間には、接地用リート
部２．３か設けられ、出力端子用リート部５と電源電圧
印加端子用リート部８との間には、接地用リート部６．
７か設けられている。１１は、各す−ト部ｌ乃至８と、
これらにそれぞれ対応する半導体集積回路装置９の端子
とを接続するワイヤである。As is clear from FIG. 1, between the input terminal lead part 1 and the input reference signal terminal lead part 4, a grounding lead part 2.3 is provided, and the output terminal lead part 5 and the power supply voltage A grounding leat section 6.
There are 7. 11 is each st part 1 to 8;
These are wires that connect the corresponding terminals of the semiconductor integrated circuit device 9, respectively.
このように高周波信号を伝送するリート部１．４間や、
高周波信号を伝送するり−ト部８と電源電圧印加端子用
リート部５との間にそれぞれ接地用ソー１〜部２．３．
６．７か設けられているのて、高周波信号を伝送する入
力端子用リート部ｌ、入力基準信号端子用リート部４は
、接地用リート部２．３によってシールドされ、たとえ
周波数か２ＧＨ，以上のような高周波信号か供給されて
も、入力端子用リート部ｌ、入力基準信号端子用リード
部４間の容量か減少し、これによってクロス１ヘークか
減少する。出力端子用リート部５と電源電圧印加端子用
リート部８も、接地用リート部６．７によってシールド
され、出力端子用リート部５は電源ラインのノイズの影
響を受けない。Between the REIT parts 1 and 4 that transmit high frequency signals in this way,
Grounding saws 1 to 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3, 3, 3 . . . . . . . . . . . .
6.7, the input terminal REET part 1 for transmitting high frequency signals and the input reference signal terminal REET part 4 are shielded by the grounding REET part 2.3, and even if the frequency is 2 GH or more, Even if such a high frequency signal is supplied, the capacitance between the input terminal lead portion 1 and the input reference signal terminal lead portion 4 decreases, thereby reducing the cross 1 hake. The output terminal REEAT part 5 and the power supply voltage application terminal REEAT part 8 are also shielded by the grounding REET part 6.7, so that the output terminal REEAT part 5 is not affected by the noise of the power supply line.
上記の実施例ては、入力端子用リート部１と入力基準信
号端子用リード部４との間に２つの接地用リート部２．
３を、出力端子用リート部５と電源電圧印加端子用リー
ト部８との間に２つの接地用リート部６．７をそれぞれ
設けたか、これら接地用リート部の数は状況に応して任
意に変更することかでき、最低限度１つたけてもよい。In the above embodiment, there are two grounding lead parts 2. between the input terminal lead part 1 and the input reference signal terminal lead part 4.
3, whether two grounding REEAT sections 6 and 7 are provided between the output terminal REEAT section 5 and the power supply voltage application terminal REEAT section 8, or the number of these grounding REEAT sections is arbitrary depending on the situation. You can change it to , and you can add at least one.
［発明の効果コ
以上のように、本発明によれば、複数の高周波信号伝送
用及び電源供給用のリート部間に１つ以上の接地用リー
ト部を設けているのて、これら接地用リード部がシール
ドとして機能するのて、高周波信号のクロストークか発
生したり、電源ノイズの影響を受けることかない。[Effects of the Invention] As described above, according to the present invention, since one or more grounding reat parts are provided between a plurality of high frequency signal transmission and power supply reat parts, these grounding leads Since the section functions as a shield, there will be no crosstalk of high-frequency signals or the effects of power supply noise.
第１図は本発明による高周波半導体装置の１実施例の要
部を示す平面図、第２図は同実施例の斜視図、第３図は
従来の高周波半導体装置の要部の平面図である。
ｌ・・・・入力端子用リート部、２．３．６．７・・・
・接地用リード部、４・・・・入力基準信号端子用リー
ド部、５・・・・出力端子用リード部、８・・・・電源
電圧印加端子用リート部、９・・・・半導体集積回路装
置、１０・・・・フレーム、１１・・・・ワイヤ。FIG. 1 is a plan view showing the main parts of an embodiment of a high-frequency semiconductor device according to the present invention, FIG. 2 is a perspective view of the same embodiment, and FIG. 3 is a plan view of the main parts of a conventional high-frequency semiconductor device. . l...Leat part for input terminal, 2.3.6.7...
・Grounding lead part, 4...Lead part for input reference signal terminal, 5...Lead part for output terminal, 8...Lead part for power supply voltage application terminal, 9...Semiconductor integration Circuit device, 10...frame, 11...wire.
Claims (1)
半導体集積回路装置が載置され上記半導体集積回路装置
に対する複数の高周波信号伝送用リード部と電源供給用
のリード部と接地用リード部とを有しているフレームと
、上記各リード部と上記半導体集積回路装置の対応する
端子とを接続しているワイヤとを、具備し、上記複数の
高周波信号伝送用リード部間及び上記高周波信号伝送リ
ード部と上記電源供給用のリード部間にそれぞれ１つ以
上の上記接地用リード部を設けたことを特徴とする高周
波用半導体装置。(1) A semiconductor integrated circuit device that operates in a high frequency band, and a plurality of high frequency signal transmission lead portions, power supply lead portions, and grounding lead portions for the semiconductor integrated circuit device on which the semiconductor integrated circuit device is mounted. and wires connecting each of the lead parts and the corresponding terminals of the semiconductor integrated circuit device, the wires connecting the plurality of lead parts for high frequency signal transmission and the high frequency signal transmission between the plurality of high frequency signal transmission lead parts. A high frequency semiconductor device, characterized in that one or more of the grounding lead parts are provided between the lead part and the power supply lead part.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7758890A JPH03276746A (en) | 1990-03-27 | 1990-03-27 | High frequency semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7758890A JPH03276746A (en) | 1990-03-27 | 1990-03-27 | High frequency semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03276746A true JPH03276746A (en) | 1991-12-06 |
Family
ID=13638132
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7758890A Pending JPH03276746A (en) | 1990-03-27 | 1990-03-27 | High frequency semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03276746A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002299645A (en) * | 2001-03-29 | 2002-10-11 | Furukawa Electric Co Ltd:The | Lead frame for optical module and optical module |
-
1990
- 1990-03-27 JP JP7758890A patent/JPH03276746A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002299645A (en) * | 2001-03-29 | 2002-10-11 | Furukawa Electric Co Ltd:The | Lead frame for optical module and optical module |
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