JPH0786495A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0786495A
JPH0786495A JP5184440A JP18444093A JPH0786495A JP H0786495 A JPH0786495 A JP H0786495A JP 5184440 A JP5184440 A JP 5184440A JP 18444093 A JP18444093 A JP 18444093A JP H0786495 A JPH0786495 A JP H0786495A
Authority
JP
Japan
Prior art keywords
semiconductor chip
semiconductor
chip
semiconductor device
insulating substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP5184440A
Other languages
Japanese (ja)
Inventor
Kazuya Matsumoto
一也 松本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP5184440A priority Critical patent/JPH0786495A/en
Publication of JPH0786495A publication Critical patent/JPH0786495A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To reduce the size of a metallic enclosure for housing a plurality of semiconductor chips by arranging a first semiconductor chip on an insulating substrate and a second semiconductor chip which is turned over as compared with the first semiconductor chip on the first semiconductor chip. CONSTITUTION:In a metallic package composed of an insulating substrate 1 and metallic enclosure 3, a first semiconductor chip 2a is mounted 1 in an inverted state on the substrate 1 by flip-chip bonding and a second semiconductor chip 2b is mounted on the chip 2a in a normal state so that the rear surfaces of the chips 2a and 3b can meet each other. The chip 2a is connected to wiring on the substrate 1 through bump electrodes 5 and the chip 2b is connected to the wiring on the substrate 1 through bonding wires 4. Therefore, the using area of the substrate 1 becomes the same as that obtained when only the chip 2a is mounted on the substrate 1 and the size of the metallic enclosure can be reduced.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体デバイスに関す
る。より詳細には、ひとつの金属パッケージ内に複数の
半導体チップを収容して形成された半導体デバイスの新
規な構成に関する。
FIELD OF THE INVENTION The present invention relates to semiconductor devices. More specifically, the present invention relates to a novel structure of a semiconductor device formed by accommodating a plurality of semiconductor chips in one metal package.

【0002】[0002]

【従来の技術】近年の半導体技術の進歩は目覚ましく、
極めて多くの素子を高密度に実装する技術が実現されて
いる。しかしながら、ベアチップとして供給される汎用
の半導体チップを使用する場合や、光素子、超電導素子
等のように通常の半導体回路とは製造工程の異なる素子
等を使用する場合には、複数のチップを組み合わせてひ
とつの半導体デバイスを構成する場合もある。
2. Description of the Related Art Recent advances in semiconductor technology are remarkable.
A technique for mounting an extremely large number of elements at high density has been realized. However, when using a general-purpose semiconductor chip supplied as a bare chip, or when using an element such as an optical element or a superconducting element whose manufacturing process is different from that of a normal semiconductor circuit, a plurality of chips are combined. In some cases, one semiconductor device may be configured.

【0003】図4は、複数の半導体チップを備えた半導
体デバイスの典型的な構成を示す図である。
FIG. 4 is a diagram showing a typical structure of a semiconductor device having a plurality of semiconductor chips.

【0004】同図に示すように、この半導体デバイス
は、絶縁基板1上に装荷された複数の半導体チップ2
a、2bと、これら半導体チップ2a、2bを封止する
金属筐体3とから主に構成されている。半導体チップ2
a、2bは、それぞれボンディングワイヤ4により絶縁
基板1上の配線に接続され、更に、絶縁基板1に装着さ
れたリードピン1aを介して外部に接続できるように構
成されている。
As shown in FIG. 1, this semiconductor device includes a plurality of semiconductor chips 2 loaded on an insulating substrate 1.
It is mainly composed of a and 2b and a metal casing 3 that seals the semiconductor chips 2a and 2b. Semiconductor chip 2
Each of a and 2b is configured to be connected to a wiring on the insulating substrate 1 by a bonding wire 4 and further connected to the outside via a lead pin 1a mounted on the insulating substrate 1.

【0005】上述のような半導体デバイスにおいて、デ
バイス全体の製造コストのうちで金属筐体が占める割合
は比較的大きく、使用する金属筐体の寸法は小さいこと
が望ましい。しかしながら、実際には、絶縁基板上に各
半導体チップのワイヤリングスペース等をとる必要があ
り、複数の半導体チップを備えた半導体デバイスではチ
ップサイズ以上に金属筐体が大きくならざるを得ない。
このため、複数の半導体チップを備えた半導体デバイス
は割高なものになりがちである。
In the semiconductor device as described above, the metal casing occupies a relatively large proportion of the manufacturing cost of the entire device, and it is desirable that the size of the metal casing used is small. However, in reality, it is necessary to secure a wiring space for each semiconductor chip on the insulating substrate, and in a semiconductor device including a plurality of semiconductor chips, the metal housing has to be larger than the chip size.
Therefore, a semiconductor device including a plurality of semiconductor chips tends to be expensive.

【0006】また、ボンディングワイヤは、それ自体の
寄生インダクタンス等のために、特に周波数の高い信号
や微弱な信号を取り扱う場合の信号の劣化が大きい。ま
た、ボンディングワイヤを使用した場合、高速動作の要
求されるデバイスでは、信号線路長も無視し得ないもの
となる。
Further, the bonding wire has a large signal deterioration due to its own parasitic inductance or the like, particularly when a high frequency signal or a weak signal is handled. Further, when a bonding wire is used, the signal line length cannot be ignored in a device that requires high-speed operation.

【0007】[0007]

【発明が解決しようとする課題】上述のように、複数の
半導体チップを収容して構成された半導体デバイスでは
金属筐体が大きくなるためにコストの上昇が避けられ
ず、また、高速あるいは微弱な信号の劣化が生じ易いと
いう問題があった。
As described above, in a semiconductor device configured to accommodate a plurality of semiconductor chips, the metal housing becomes large, so that an increase in cost is unavoidable, and the speed is high or weak. There is a problem that signal deterioration is likely to occur.

【0008】そこで、本発明は、上記従来技術の問題点
を解決し、複数の半導体チップを収容する一方で小型の
金属筐体を使用でき、且つ、高速な信号や微弱な信号も
劣化させることなく使用できる、新規な構成の半導体デ
バイスを提供することをその目的としている。
Therefore, the present invention solves the above-mentioned problems of the prior art, can accommodate a plurality of semiconductor chips, can use a small metal housing, and can degrade high-speed signals and weak signals. It is an object of the present invention to provide a semiconductor device having a novel structure that can be used without any need.

【0009】[0009]

【課題を解決するための手段】本発明に従うと、絶縁基
板と、該絶縁基板上に装荷された半導体チップと、該絶
縁基板上の該半導体チップを封止する金属筐体とを含む
半導体デバイスにおいて、該絶縁基板上にフリップチッ
プボンディング方式で装荷された第1半導体チップと、
該第1半導体チップ上に、該第1半導体チップとは表裏
を反転させて実装された第2半導体チップとを備えるこ
とを特徴とする半導体デバイスが提供される。
According to the present invention, there is provided a semiconductor device including an insulating substrate, a semiconductor chip loaded on the insulating substrate, and a metal casing for sealing the semiconductor chip on the insulating substrate. A first semiconductor chip loaded on the insulating substrate by a flip chip bonding method,
A semiconductor device is provided, comprising: a second semiconductor chip mounted on the first semiconductor chip, the front surface and the back surface of the first semiconductor chip being reversed.

【0010】[0010]

【作用】本発明に係る半導体デバイスは、絶縁基板に対
する半導体チップの実装方法にその主要な特徴がある。
The semiconductor device according to the present invention is characterized mainly in the method of mounting a semiconductor chip on an insulating substrate.

【0011】即ち、従来の半導体デバイスでは、半導体
チップを絶縁基板上に水平に配列していたので、収容す
る半導体チップが複数になった場合に、単純に面積が増
えるだけではなく、半導体チップ毎にワイヤリングスペ
ース等を確保しなければならず、結果的にデバイスの寸
法が非常に大きなものになっていた。また、半導体チッ
プ相互の配線はボンディングによる他はなかったので、
不可避に寄生インダクタンスを有するボンディングワイ
ヤのために、周波数の高い信号や微弱な信号の劣化がさ
けられなかった。
That is, in the conventional semiconductor device, since the semiconductor chips are arranged horizontally on the insulating substrate, when a plurality of semiconductor chips are accommodated, not only the area is simply increased but also each semiconductor chip is increased. It was necessary to secure a wiring space and the like, and as a result, the size of the device was very large. Also, because the wiring between the semiconductor chips was nothing but bonding,
Due to the bonding wire inevitably having parasitic inductance, deterioration of high frequency signals and weak signals was unavoidable.

【0012】これに対して本発明に係る半導体デバイス
は、複数の半導体チップを積層して実装することによ
り、専有面積を著しく低減させたのみならず、配線長の
短縮においても効果を挙げている。
On the other hand, the semiconductor device according to the present invention not only significantly reduces the occupied area by stacking and mounting a plurality of semiconductor chips, but is also effective in reducing the wiring length. .

【0013】即ち、半導体チップは、通常その一方の面
の上に回路または素子が形成されている。従って、1対
の半導体チップを互いに裏面が対向するように積層して
も、その機能に対して影響はない。
That is, the semiconductor chip usually has a circuit or element formed on one surface thereof. Therefore, even if a pair of semiconductor chips are stacked so that their back surfaces face each other, their functions are not affected.

【0014】ここで、絶縁基板の半導体チップは、装荷
された回路または素子が絶縁基板の実装面に対向するこ
とになるが、フリップチップボンディングとよばれるバ
ンプ電極を使用した実装方法によれば、半導体チップの
表面を下に向けて実装することに問題はない。
Here, in the semiconductor chip on the insulating substrate, the loaded circuit or element faces the mounting surface of the insulating substrate. According to the mounting method using bump electrodes called flip chip bonding, There is no problem in mounting with the surface of the semiconductor chip facing downward.

【0015】一方、上記フリップチップボンディングに
より実装された半導体チップに積層して実装される第2
半導体チップは、従来通りワイヤボンディングによって
基板との接続を行うことができる他、具体的に後述する
ように、第1半導体チップに形成したヴィアホールを介
して第1半導体チップおよび絶縁基板との間の配線を形
成することができる。このような方式によれば、寄生容
量の大きなボンディングワイヤの使用を削減できる他、
信号線路長も短縮することができる。
On the other hand, the second is mounted by stacking on the semiconductor chip mounted by the flip chip bonding.
The semiconductor chip can be connected to the substrate by wire bonding as is conventionally done, and as will be described later in detail, the semiconductor chip is connected between the first semiconductor chip and the insulating substrate through a via hole formed in the first semiconductor chip. Wiring can be formed. According to such a method, it is possible to reduce the use of a bonding wire having a large parasitic capacitance,
The signal line length can also be shortened.

【0016】尚、上記の説明では『半導体チップ』と呼
んでいるが、実際には、超電導集積回路や光集積回路等
の必ずしも電子回路ではない集積回路を装荷されたチッ
プに対しても本発明が適用可能であることはいうまでも
ない。
Although referred to as a "semiconductor chip" in the above description, the present invention also applies to a chip loaded with an integrated circuit which is not necessarily an electronic circuit such as a superconducting integrated circuit or an optical integrated circuit. Needless to say, is applicable.

【0017】以下、実施例を挙げて本発明をより具体的
に説明するが、以下の開示は本発明の一実施例に過ぎ
ず、本発明の技術的範囲を何ら限定するものではない。
Hereinafter, the present invention will be described in more detail with reference to examples, but the following disclosure is merely one example of the present invention and does not limit the technical scope of the present invention.

【0018】[0018]

【実施例】図1は、本発明に係る半導体デバイスの具体
的な構成例を示す図である。尚、同図において、図4と
共通の構成要素には同じ参照番号を付して詳細な説明を
省略している。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram showing a concrete configuration example of a semiconductor device according to the present invention. In the figure, the same components as those in FIG. 4 are designated by the same reference numerals, and detailed description thereof is omitted.

【0019】同図に示すように、この半導体デバイス
は、絶縁基板1と金属筐体3とによって構成されたメタ
ルパッケージに1対の半導体チップ2a、2bを収容し
て構成されているという点では、図4に示した半導体デ
バイスと共通である。
As shown in the figure, this semiconductor device is constructed by accommodating a pair of semiconductor chips 2a and 2b in a metal package composed of an insulating substrate 1 and a metal housing 3. , Which is common to the semiconductor device shown in FIG.

【0020】但し、この半導体デバイスでは、第1半導
体チップ2aが倒立して、いわゆるフリップチップボン
ディングにより絶縁基板1に実装されている。また、第
2半導体チップ2bは通常の向きで、即ち、第1半導体
チップ2aと裏面どうしを合わせるようにして、第2半
導体チップ2a上に装荷されている。
However, in this semiconductor device, the first semiconductor chip 2a is inverted and mounted on the insulating substrate 1 by so-called flip chip bonding. Further, the second semiconductor chip 2b is loaded on the second semiconductor chip 2a in the normal orientation, that is, the back surfaces of the first semiconductor chip 2a and the first semiconductor chip 2a are aligned with each other.

【0021】ここで、第1半導体チップ2aは、バンプ
電極5を介して絶縁基板1上の配線に接続されている。
一方、第2半導体チップ2bは、ボンディングワイヤ4
を介して絶縁基板1上の配線に接続されている。
Here, the first semiconductor chip 2a is connected to the wiring on the insulating substrate 1 via the bump electrode 5.
On the other hand, the second semiconductor chip 2b has a bonding wire 4
Is connected to the wiring on the insulating substrate 1 via.

【0022】以上のように構成された半導体デバイスで
は、使用する絶縁基板1に必要な面積は、第1半導体チ
ップ2aを単独で実装した場合と同じである。従って、
封止のために使用する金属筐体3は小型のものを使用す
ることができる。また、特に第1半導体チップ2aは、
フリップチップボンディング方式により実装されている
ので、信号劣化の原因となり易いボンディングワイヤの
使用量も削減されている。
In the semiconductor device configured as described above, the required area of the insulating substrate 1 to be used is the same as when the first semiconductor chip 2a is mounted alone. Therefore,
A small metal casing 3 can be used for sealing. Further, in particular, the first semiconductor chip 2a is
Since the flip-chip bonding method is used for mounting, the amount of bonding wires used, which easily causes signal deterioration, is also reduced.

【0023】図2は、本発明に係る半導体デバイスの他
の構成例を示す図である。この図においても、図1およ
び図4と共通の構成要素には同じ参照番号を付して詳細
な説明を省略している。
FIG. 2 is a diagram showing another structural example of the semiconductor device according to the present invention. Also in this figure, components common to those in FIGS. 1 and 4 are denoted by the same reference numerals, and detailed description thereof is omitted.

【0024】同図に示すように、この半導体デバイス
は、絶縁基板1、半導体チップ2a、2bおよび金属筐
体3による基本的な配置は、図1に示した半導体デバイ
スと共通の構成を有している。
As shown in the figure, this semiconductor device has the same basic arrangement as that of the semiconductor device shown in FIG. 1 in terms of the basic arrangement of the insulating substrate 1, the semiconductor chips 2a and 2b, and the metal housing 3. ing.

【0025】この半導体デバイスの特徴は、第2半導体
チップ2bの電気的な接続にある。即ち、ここで使用さ
れている第1半導体チップ2aには複数のヴィアホール
6が形成されており、第2半導体チップは、ボンディン
グワイヤ4およびヴィアホールを介して、第1半導体チ
ップ2aの回路の接続されている。
The characteristic of this semiconductor device is the electrical connection of the second semiconductor chip 2b. That is, a plurality of via holes 6 are formed in the first semiconductor chip 2a used here, and the second semiconductor chip is connected to the circuit of the first semiconductor chip 2a via the bonding wire 4 and the via hole. It is connected.

【0026】以上のような構成により、この半導体デバ
イスでは、信号劣化の原因になり易いボンディングワイ
ヤの使用量を低減し、更に、このパッケージ内での信号
線路長を短縮している。
With the above-mentioned structure, in this semiconductor device, the amount of the bonding wire, which is apt to cause the signal deterioration, is reduced, and further, the signal line length in this package is shortened.

【0027】図3は、本発明に係る半導体デバイスの更
に他の構成例を示す図である。この図においても、図
1、図2および図4と共通の構成要素には同じ参照番号
を付して詳細な説明を省略している。
FIG. 3 is a diagram showing still another configuration example of the semiconductor device according to the present invention. Also in this figure, constituent elements common to those in FIGS. 1, 2 and 4 are designated by the same reference numerals, and detailed description thereof is omitted.

【0028】同図に示すように、この半導体デバイス
は、絶縁基板1、半導体チップ2a、2cおよび金属筐
体3による基本的な配置並びにそれらの配線について
は、図2に示した半導体デバイスと共通の構成を有して
いる。
As shown in the figure, this semiconductor device has the same basic arrangement as the insulating substrate 1, the semiconductor chips 2a, 2c, and the metal housing 3 and the wiring thereof as in the semiconductor device shown in FIG. It has the configuration of.

【0029】この半導体デバイスの特徴は、第2半導体
チップ2cとして光素子であるフォトダイオードを使用
している点にある。従って、金属筐体3には、フォトダ
イオードの受ける光を透過させるための透明な窓3aが
形成されている。
A characteristic of this semiconductor device is that a photodiode, which is an optical element, is used as the second semiconductor chip 2c. Therefore, the metal casing 3 is formed with a transparent window 3a for transmitting the light received by the photodiode.

【0030】一般に、フォトダイオードの出力する電気
信号は、通常の電子回路で取り扱われる信号と比較する
と極めて微弱であり、信号の劣化や雑音の影響が常に問
題になっている。これに対して、本発明に従って構成さ
れた半導体デバイスでは、信号劣化の原因になり易いボ
ンディングワイヤ4の使用が極限まで短縮されており信
号品質を維持し易い。
In general, an electric signal output from a photodiode is extremely weak as compared with a signal handled by an ordinary electronic circuit, and the deterioration of the signal and the influence of noise are always a problem. On the other hand, in the semiconductor device configured according to the present invention, the use of the bonding wire 4, which easily causes signal deterioration, is shortened to the utmost limit, and the signal quality is easily maintained.

【0031】[0031]

【発明の効果】以上説明したように、本発明に従う半導
体デバイスは、複数のチップを備えた半導体デバイスデ
バイスとしては画期的に小型化されている。従って、封
止のために使用する金属筐体を小型化することができる
ので、低コストに製造することができる。
As described above, the semiconductor device according to the present invention is remarkably miniaturized as a semiconductor device device having a plurality of chips. Therefore, the metal casing used for sealing can be miniaturized, so that the manufacturing cost can be reduced.

【0032】また、単に物理的に小型化されているだけ
ではなく、信号劣化の原因になり易いボンディングワイ
ヤの使用量を短縮しており、微弱な信号や周波数の高い
信号を取扱う場合にも、信号劣化の少ないデバイスとし
て有利に使用することができる。
Further, not only is it physically miniaturized, but the amount of bonding wires that tend to cause signal deterioration is shortened, and when handling weak signals or high frequency signals, It can be advantageously used as a device with little signal deterioration.

【0033】以上のような特徴を有する本発明に係る半
導体デバイスは、複数の半導体チップを使用したデバイ
スのみならず、光素子、光集積回路、チップ集積回路等
の半導体以外の集積回路を使用したデバイスにも好適に
採用することができる。
The semiconductor device according to the present invention having the above characteristics uses not only a device using a plurality of semiconductor chips but also an integrated circuit other than the semiconductor such as an optical element, an optical integrated circuit, and a chip integrated circuit. It can also be suitably used in devices.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る半導体デバイスの構成を模式的に
示す図である。
FIG. 1 is a diagram schematically showing a configuration of a semiconductor device according to the present invention.

【図2】本発明に係る半導体デバイスの他の構成例を示
す図である。
FIG. 2 is a diagram showing another configuration example of a semiconductor device according to the present invention.

【図3】本発明に係る半導体デバイスの更に他の構成例
を示す図である。
FIG. 3 is a diagram showing still another configuration example of the semiconductor device according to the present invention.

【図4】複数の半導体チップを使用した従来の半導体デ
バイスの典型的な構成を示す図である。
FIG. 4 is a diagram showing a typical configuration of a conventional semiconductor device using a plurality of semiconductor chips.

【符号の説明】 1・・・絶縁基板、 2a・・第1半導体チップ、 2b・・第2半導体チップ、 2c・・フォトダイオード、 3・・・金属筐体、 4・・・ボンディングワイヤ、 5・・・バンプ電極、 6・・・ヴィアホール[Explanation of reference numerals] 1 ... Insulating substrate, 2a ... First semiconductor chip, 2b ... Second semiconductor chip, 2c ... Photodiode, 3 ... Metal housing, 4 ... Bonding wire, 5 ... Bump electrodes, 6 ... Via holes

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】絶縁基板と、該絶縁基板上に装荷された半
導体チップと、該絶縁基板上の該半導体チップを封止す
る金属筐体とを含む半導体デバイスにおいて、 該絶縁基板上にフリップチップボンディング方式で装荷
された第1半導体チップと、該第1半導体チップ上に、
該第1半導体チップとは表裏を反転させて装荷された第
2半導体チップとを備えることを特徴とする半導体デバ
イス。
1. A semiconductor device comprising an insulating substrate, a semiconductor chip loaded on the insulating substrate, and a metal casing encapsulating the semiconductor chip on the insulating substrate, wherein a flip chip is provided on the insulating substrate. A first semiconductor chip loaded by a bonding method, and on the first semiconductor chip,
A semiconductor device comprising: a first semiconductor chip, and a second semiconductor chip loaded with its front and back reversed.
【請求項2】請求項1に記載された半導体デバイスにお
いて、前記第1半導体チップ上の素子または回路と、前
記第2半導体チップ上の素子または回路とが、該第1半
導体チップに形成されたヴィアホールを介して接続され
ていることを特徴とする半導体デバイス。
2. The semiconductor device according to claim 1, wherein the element or circuit on the first semiconductor chip and the element or circuit on the second semiconductor chip are formed on the first semiconductor chip. A semiconductor device characterized by being connected through a via hole.
JP5184440A 1993-06-29 1993-06-29 Semiconductor device Withdrawn JPH0786495A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5184440A JPH0786495A (en) 1993-06-29 1993-06-29 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5184440A JPH0786495A (en) 1993-06-29 1993-06-29 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0786495A true JPH0786495A (en) 1995-03-31

Family

ID=16153191

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5184440A Withdrawn JPH0786495A (en) 1993-06-29 1993-06-29 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0786495A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6509638B2 (en) 2000-09-07 2003-01-21 Matsushita Electric Industrial Co., Ltd. Semiconductor device having a plurality of stacked semiconductor chips on a wiring board
KR100368607B1 (en) * 2000-04-17 2003-01-24 주식회사 케이이씨 semiconductor package
JP2005158767A (en) * 2003-11-20 2005-06-16 Ibiden Co Ltd Ic chip connection structure and ic chip mounting substrate
WO2007126910A1 (en) * 2006-03-31 2007-11-08 Intel Corporation A single package wireless communication device

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100368607B1 (en) * 2000-04-17 2003-01-24 주식회사 케이이씨 semiconductor package
US7078818B2 (en) 2000-09-07 2006-07-18 Matsushita Electric Industrial Co., Ltd. Semiconductor device
US6693347B2 (en) 2000-09-07 2004-02-17 Matsushita Electric Industrial Co., Ltd. Semiconductor device
US6707143B2 (en) 2000-09-07 2004-03-16 Matsushita Electric Industrial Co., Ltd. Stacked semiconductor chips attached to a wiring board
EP1187210A3 (en) * 2000-09-07 2005-03-02 Matsushita Electric Industrial Co., Ltd. Semiconductor device
US6509638B2 (en) 2000-09-07 2003-01-21 Matsushita Electric Industrial Co., Ltd. Semiconductor device having a plurality of stacked semiconductor chips on a wiring board
JP2005158767A (en) * 2003-11-20 2005-06-16 Ibiden Co Ltd Ic chip connection structure and ic chip mounting substrate
JP4522079B2 (en) * 2003-11-20 2010-08-11 イビデン株式会社 IC chip mounting substrate
US7692295B2 (en) 2006-03-31 2010-04-06 Intel Corporation Single package wireless communication device
WO2007126910A1 (en) * 2006-03-31 2007-11-08 Intel Corporation A single package wireless communication device
US8138599B2 (en) 2006-03-31 2012-03-20 Intel Corporation Wireless communication device integrated into a single package
US10439265B2 (en) 2006-03-31 2019-10-08 Intel Corporation Single-package wireless communication device
US10727567B2 (en) 2006-03-31 2020-07-28 Intel Corporation Single-package wireless communication device
US11552383B2 (en) 2006-03-31 2023-01-10 Tahoe Research, Ltd. Single-package wireless communication device
US11942676B2 (en) 2006-03-31 2024-03-26 Tahoe Research, Ltd. Single-package wireless communication device

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