JPS63173347A - Package for integrated circuit part - Google Patents

Package for integrated circuit part

Info

Publication number
JPS63173347A
JPS63173347A JP62005434A JP543487A JPS63173347A JP S63173347 A JPS63173347 A JP S63173347A JP 62005434 A JP62005434 A JP 62005434A JP 543487 A JP543487 A JP 543487A JP S63173347 A JPS63173347 A JP S63173347A
Authority
JP
Japan
Prior art keywords
pattern
package
lsi
resistor
cut
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62005434A
Other languages
Japanese (ja)
Inventor
Seiichi Saito
斎藤 精一
Toshinari Hayashi
俊成 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62005434A priority Critical patent/JPS63173347A/en
Publication of JPS63173347A publication Critical patent/JPS63173347A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Abstract

PURPOSE:To use the title package for each application of a plurality of connection of the same specification and a large number of LSI connection, and to reduce the turbulence of a waveform by connecting a wire pad, a lead, a terminal resistor and a power supply by a pattern so that at least three kinds of circuits are constituted by cut ting one part of the pattern. CONSTITUTION:A terminal resistor 3 with a power supply 19 is mounted into a package body 11. These power supply and terminal resistor, a pad 14 and a lead 16 are connected by patterns 17, 18, 20, 21, and one parts of the patterns are shaped onto the surface of a package. When there is the terminal resistor proper to operation at high speed, the pattern 21 is cut. The connection of parts is used properly by pattern-cutting into the presence or absence of the terminal resistor on a plurality of connection of the same specification. An LSI at the final terminal of a signal wiring is pattern-cut in the presence of the terminal resistor. The section 18a of the pattern 18 is cut in midway LSI of the signal wiring. When a large number of LSIs are connected, one part 18a of the pattern 18 and one part 17a of the pattern 17 are cut.

Description

【発明の詳細な説明】 〔概要〕 集積回路部品パッケージであって、パッケージ本体に終
端抵抗、電源又はグランドのパターンを設け、且つ接続
パターン切断可能に設けるように構成し、終端抵抗の有
る場合、無い場合及び終端抵抗をダンピング抵抗とする
3通りの使用を可能とする。
[Detailed Description of the Invention] [Summary] In the case of an integrated circuit component package, the package body is provided with a terminating resistor, a power supply or a ground pattern, and the connection pattern is provided so that it can be cut. Three ways of use are possible: when there is no terminal resistor and when the terminating resistor is used as a damping resistor.

〔産業上の利用分野〕[Industrial application field]

本発明は、高速で動作するLSI等の集積回路部品のパ
ッケージ(例えばECL回路を有するLS I)に関し
、詳しくは、終端抵抗の実装構造に関する。
The present invention relates to a package for an integrated circuit component such as an LSI that operates at high speed (for example, an LSI having an ECL circuit), and specifically relates to a mounting structure for a termination resistor.

高速LSIを基板に実装してLSI間の信号伝送を行う
場合は、伝送波形の反射を無くすために終端抵抗を設け
るのが一般的である。
When high-speed LSIs are mounted on a board and signals are transmitted between the LSIs, it is common to provide a terminating resistor to eliminate reflections of transmitted waveforms.

〔従来の技術〕[Conventional technology]

そこで、従来LSIと終端抵抗に関しては種々の考えが
あり、以下それについて述べる。
Therefore, there are various ideas regarding conventional LSIs and terminating resistors, and these will be described below.

先ず、第4図のものは終端抵抗をLSIの内部に設ける
場合であり、基板lにLSIパッケージ10a、10b
、10cが実装されている。LSIのパッケージ10b
、IOCは同一仕様のものであり、それぞれに終端抵抗
3b、3Cが内蔵されており、これが信号配線2により
パッケージ10aに接続しである。
First, the one in FIG. 4 is a case where a terminating resistor is provided inside the LSI, and the LSI packages 10a and 10b are mounted on the substrate l.
, 10c are implemented. LSI package 10b
, IOCs have the same specifications, and each has built-in termination resistors 3b and 3C, which are connected to the package 10a through signal wiring 2.

第5図のものは終端抵抗をLSIの外に設ける場合であ
り、基板1にLSIパッケージ10a、及び同一仕様の
LSIパッケージ10b、10cが実装され、これらが
信号配線2で接続される。
In the case shown in FIG. 5, a termination resistor is provided outside the LSI, and an LSI package 10a and LSI packages 10b and 10c having the same specifications are mounted on a substrate 1, and these are connected by a signal wiring 2.

そして、終端抵抗3が各別に実装されて、パッケージ1
0b、10cと接続しである。
Then, the terminating resistors 3 are mounted separately, and the package 1
It is connected to 0b and 10c.

ここで、第4図、第5図に示すように、同一仕様の複数
個のLSIパッケージ10b、10cを同一の信号配線
2に接続して使用する方法は、良く用いられるLSIの
使用方法の一つであることに注意されたい。
Here, as shown in FIGS. 4 and 5, a method of connecting a plurality of LSI packages 10b, 10c with the same specifications to the same signal wiring 2 is one of the commonly used methods of using LSI. Please note that

第6図は終端抵抗をLSIの外に各別に設ける場合の詳
細図であり、LSIパッケージ10 (第5図の100
に相当)はパッケージ本体11の内部にチップ12が収
容され、このチップ12がワイヤ13によりパッド14
にボンディングされ、パッド14からパッケージ内配線
15によりリード16に接続される。そして、リード1
6は基板1の信号配線2に半田付けされるのであり、か
かる配線2に対し配線4を介してパッケージ10と各別
の終端抵抗3 (第5図の3に相当)に接続しである。
FIG. 6 is a detailed diagram of the case where the terminating resistors are provided separately outside the LSI, and shows the LSI package 10 (100 in FIG. 5).
), a chip 12 is housed inside a package body 11, and this chip 12 is connected to a pad 14 by a wire 13.
The pad 14 is connected to the lead 16 by the in-package wiring 15. And lead 1
6 is soldered to the signal wiring 2 of the substrate 1, and the wiring 2 is connected to the package 10 and each termination resistor 3 (corresponding to 3 in FIG. 5) via the wiring 4.

第7図のものは上述の第6図に関係し、LSIのリード
、パッケージの配線部をマイクロストリップラインにし
、その特性インピーダンスを基板の信号配線のものと等
しくする場合である。そこで、パッケージ10において
パッド14からマイクロストリップラインの配線15a
1リード16aを介して信号配線2に、他の配線15b
、リード16bを介して終端抵抗3に接続しである。
The diagram in FIG. 7 is related to the above-mentioned diagram in FIG. 6, and is a case where the leads of the LSI and the wiring part of the package are made into microstrip lines, and the characteristic impedance thereof is made equal to that of the signal wiring of the board. Therefore, in the package 10, from the pad 14 to the microstrip line wiring 15a.
1 lead 16a to the signal wiring 2, and the other wiring 15b
, and are connected to the terminating resistor 3 via the lead 16b.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

ここで、第4図のものは、各LSIパッケージ10b、
10cに終端抵抗3b、3cを内蔵するので、1本の信
号配線2に2個以上の抵抗3b、3cが接続されてしま
い、A、Bの伝送波形が乱れる。
Here, in FIG. 4, each LSI package 10b,
Since the terminal resistors 3b and 3c are built into the signal line 10c, two or more resistors 3b and 3c are connected to one signal line 2, and the transmission waveforms of A and B are disturbed.

第5図のものは信号がそれほど高速でない場合に一般的
に用いられており、同一仕様のLSIパッケージ10b
、10Cに対し1個の終端抵抗3であるから、A、Bの
波形は乱れない。また、一般に基板1の信号配線2の特
性インピーダンス(通常50〜150Ω)と同じ抵抗を
LSIチップ上に精度良く作るのは難しく、この抵抗に
比較的大きなスペースを要して高密度化の妨げになるの
で、この点でも有利である。しかるに、第6図において
述べるように、高速化に適さないという問題点を有する
The one in Figure 5 is generally used when the signal is not very high speed, and is an LSI package 10b with the same specifications.
, 10C, there is one terminating resistor 3, so the waveforms of A and B are not disturbed. In addition, it is generally difficult to accurately create a resistor on an LSI chip that is the same as the characteristic impedance (usually 50 to 150Ω) of the signal wiring 2 on the board 1, and this resistor requires a relatively large space, which hinders high density. Therefore, it is advantageous in this respect as well. However, as described in FIG. 6, there is a problem that it is not suitable for increasing speed.

第6図は終端抵抗3を外に設けた第5図において、信号
が高速になった場合の詳細説明図である。回路の動作が
高速になり信号の立上り、立下り時間が小さくなると、
伝送波形に乱れを生じ、誤動作の恐れがある。これは、
パッケージ10のパターン15、リード16のし、、C
1及びチップ12の回路のCが分岐負荷となり、信号が
高速になるほど伝送波形に影響するためである。この点
ではパッケージ10のり、Cの影響を小さくできる終端
抵抗内蔵式が好ましい。
FIG. 6 is a detailed explanatory diagram of a case where the signal speed increases in FIG. 5 in which the termination resistor 3 is provided outside. As the circuit operates faster and the signal rise and fall times become smaller,
This may disrupt the transmission waveform and cause malfunction. this is,
Pattern 15 of package 10, lead 16, C
This is because C of the circuits of the chips 1 and 12 becomes a branch load, and the higher the signal speed, the more it affects the transmission waveform. In this respect, it is preferable to use a built-in termination resistor type that can reduce the influence of the adhesive and C on the package 10.

第7図のものは高速化に適し伝送波形の乱れも少ないが
、1本の信号に対し2つのリード16a、L6bを必要
として、このためLSIの入出力信号数が制限されて高
密度化の妨げとなる。
The one in Figure 7 is suitable for high speeds and has little disturbance in the transmission waveform, but it requires two leads 16a and L6b for one signal, which limits the number of LSI input/output signals and makes it difficult to increase density. It becomes a hindrance.

こうして、LSIパッケージの使い方により終端抵抗の
内外配置がそれぞれ長所と短所を生じるという問題があ
った。
Thus, there has been a problem in that the placement of the termination resistor inside and outside has its own advantages and disadvantages depending on how the LSI package is used.

本発明は、このような点に鑑みて創作されたもので、高
速動作や同一仕様の複数接続にそれぞれ適し、高密度化
が可能な集積回路部品パッケージを提供することを目的
としている。
The present invention was created in view of the above points, and an object of the present invention is to provide an integrated circuit component package that is suitable for high-speed operation and multiple connections of the same specifications, and is capable of increasing density.

〔問題点を解決するための手段〕[Means for solving problems]

上記目的を達成するため、本発明は実施例に対応した第
1図と第2図に示すように、パッケージ本体11の内部
に電源19を備えた終端抵抗3を実装する。
In order to achieve the above object, the present invention mounts a terminating resistor 3 equipped with a power source 19 inside a package body 11, as shown in FIGS. 1 and 2 corresponding to embodiments.

そして、パッド14とリード16をパターン17で、電
源19、終端抵抗3をパターン18.20によりパター
ン17に、更にパターン18と17をパターン21で接
続し、このパターンの一部をパッケージ表面に設けて切
断可能に構成されている。
Then, the pad 14 and the lead 16 are connected to the pattern 17, the power supply 19 and the terminating resistor 3 are connected to the pattern 17 by the patterns 18 and 20, and the patterns 18 and 17 are connected to the pattern 21, and a part of this pattern is provided on the package surface. It is configured so that it can be cut.

〔作用〕[Effect]

上記構成に基づき、パターン力・ノドにより高速動作に
適した終端抵抗有り、同一仕様の複数接続の場合の終端
抵抗無し、更に終端抵抗3を直列に入れてダンピング抵
抗に使用する3種類の回路を選択的に構成するようにな
る。
Based on the above configuration, three types of circuits are available: one with a terminating resistor suitable for high-speed operation due to pattern force/node, one without a terminating resistor in case of multiple connections with the same specifications, and one with a terminating resistor 3 in series to be used as a damping resistor. Become selective.

こして本発明では、高速動作、同一仕様の複数接続、多
数のLSI接続の各用途に使用して、波形の乱れを少な
くすることが可能となる。
Thus, the present invention can be used for high-speed operation, multiple connections with the same specifications, and connections to a large number of LSIs, thereby reducing waveform disturbances.

〔実施例〕〔Example〕

以下、本発明の実施例を図面に基づいて説明する。 Embodiments of the present invention will be described below based on the drawings.

第1図において、本発明の原理について述べると、符号
10はLSIパッケージ、11はパッケージ本体、12
はチップ、13はワイヤ、14はバンド、16はリード
である。そこで、パッケージ本体11の内部においてバ
ッド14とリード16がパターン17で接続され、内蔵
された終端抵抗3にパターン18を介して電源(又はグ
ランド)19が接続する。また、終端抵抗3をパターン
17に直、並列接続するため、抵抗3の一端がパターン
20によりパターン17に、その他端のパターン18が
パターン21によりパターン17に接続される。そして
、これらのパターンの一部が種々の用途に適するように
切断可能になっている。
In FIG. 1, to describe the principle of the present invention, reference numeral 10 is an LSI package, 11 is a package body, and 12 is an LSI package.
13 is a chip, 13 is a wire, 14 is a band, and 16 is a lead. Therefore, inside the package body 11, the pad 14 and the lead 16 are connected by a pattern 17, and a power supply (or ground) 19 is connected to the built-in terminating resistor 3 via a pattern 18. Furthermore, in order to connect the terminating resistor 3 directly and in parallel to the pattern 17, one end of the resistor 3 is connected to the pattern 17 through the pattern 20, and the other end of the pattern 18 is connected to the pattern 17 through the pattern 21. Some of these patterns can be cut to suit various uses.

第2図において、パターン等の配線状態について述べる
と、電fi19が本体11の表面に設けられる。また、
電源19からのパターン1Bの一部分18a、パターン
21、パターン17の終端抵抗3と並列な一部分17a
が表面に設けられ、レーザ光等で切断可能になっている
Referring to FIG. 2, regarding the state of wiring such as patterns, an electric fi 19 is provided on the surface of the main body 11. Also,
Part 18a of pattern 1B from power supply 19, pattern 21, part 17a of pattern 17 parallel to terminating resistor 3
is provided on the surface and can be cut with a laser beam or the like.

次いで、このように構成されたパッケージの作用につい
て述べる。
Next, the operation of the package configured in this way will be described.

先ず、高速動作に適した終端抵抗有りの場合はパターン
21を切断するのであり、これによりパッケージ本体1
1内でリード16へのパターン17に電源19を備えた
終端抵抗3が接続する。
First, in the case of a terminal resistor suitable for high-speed operation, the pattern 21 is cut, thereby cutting the package body 1.
A terminating resistor 3 equipped with a power source 19 is connected to a pattern 17 to a lead 16 within the terminal 1 .

このため、第6図の場合に比べてパッケージ内部のり、
Cの影響が少なくなり、高速動作時の波形の乱れが小さ
くなる。
Therefore, compared to the case shown in Figure 6, the glue inside the package is
The influence of C is reduced, and waveform disturbances during high-speed operation are reduced.

同一仕様の複数接続の場合は終端抵抗有り及び終端抵抗
無しをパターンカットにより使い分ける。信号配線の最
終端のLSI(図4で10cに相当)は、前記の終端抵
抗有りのパターンカットとする。信号配線の途中のLS
I(図4で10bに相当)は、パターン18の部分18
aを切断するのであり、これにより終端抵抗3は無いの
と同様になりパターン17のみによる内部配線になる。
In the case of multiple connections with the same specifications, use one with or without a terminating resistor depending on the pattern cut. The LSI at the final end of the signal wiring (corresponding to 10c in FIG. 4) is cut into a pattern with the above-mentioned terminating resistor. LS in the middle of signal wiring
I (corresponding to 10b in FIG. 4) is part 18 of pattern 18
By cutting the terminal a, it is as if the terminating resistor 3 were not provided, and the internal wiring is made up of only the pattern 17.

このため、第5図の場合と同様に同一仕様の複数接続で
波形の乱れを少なくし得る。
Therefore, as in the case of FIG. 5, it is possible to reduce waveform disturbance by connecting a plurality of devices with the same specifications.

更に多数個のLSIを接続する場合は、パターン18の
一部分18aとパターン17の一部分17a切断すると
、パッド14が終端抵抗3を介しり−ド16に直列接続
し、この抵抗3がダンピング抵抗して作用する。そのた
め、同一信号配線上に多数個のLSIを接続した場合に
、第3図のように波形が滑らかに減衰してLSIからの
反射ノイズを減少させ得る。
When connecting a larger number of LSIs, by cutting off a portion 18a of the pattern 18 and a portion 17a of the pattern 17, the pad 14 is connected in series to the node 16 via the terminating resistor 3, and this resistor 3 acts as a damping resistor. act. Therefore, when a large number of LSIs are connected on the same signal wiring, the waveform attenuates smoothly as shown in FIG. 3, and reflection noise from the LSIs can be reduced.

コラして、パターンカット状態により3種類の用途に使
用されるのである。
In general, it can be used for three different purposes depending on the state of the pattern cut.

〔発明の効果〕〔Effect of the invention〕

以上述べてきたように、本発明によれば、終端抵抗3の
パッケージ内実装により高速動作に適する。
As described above, according to the present invention, the termination resistor 3 is mounted within the package, making it suitable for high-speed operation.

パターンカットにより終端抵抗3を不要にして同一仕様
のLSIの複数接続に適する。
Pattern cutting eliminates the need for a terminating resistor 3, making it suitable for connecting multiple LSIs with the same specifications.

終端抵抗3のダンピング抵抗としての使用により多数の
LSI接続に適する。
By using the terminating resistor 3 as a damping resistor, it is suitable for connecting a large number of LSIs.

リード数の増大を生しないので、高密度化を妨げない。Since the number of reads does not increase, high density is not hindered.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明のパッケージの実施例の原理図、 第2図は具体的な実施例の切欠き斜視図、第3図はダン
ピング抵抗使用の等価回路と波形の図、 第4図ないし第7図は従来例の実装状態、等価回路、波
形を示す図である。 第1図と第2図において、 3は終端抵抗、 11はパッケージ本体、 14はパッド、 16はリード、 19は電源、 17.18.20.21はパターン、 18a、17a、21は切断部分である。 5′・臣ン さrイMJ+q品8、 従朶イ列乞示す図 夕゛〉ピング抵ぜい史用址示す図 第3図 夜呆例を示す図 第4 図 従来伊j左示す図 仝A゛ ρ  M 木 U 國1
Fig. 1 is a principle diagram of an embodiment of the package of the present invention, Fig. 2 is a cutaway perspective view of a specific embodiment, Fig. 3 is an equivalent circuit and waveform diagram using a damping resistor, and Figs. FIG. 7 is a diagram showing a mounting state, an equivalent circuit, and waveforms of a conventional example. In Figures 1 and 2, 3 is the termination resistor, 11 is the package body, 14 is the pad, 16 is the lead, 19 is the power supply, 17, 18, 20, and 21 are the patterns, and 18a, 17a, and 21 are the cutting parts. be. 5'・Representative MJ + Q Product 8, A figure showing a sequence of subordinates. A゛ ρ M tree U country 1

Claims (1)

【特許請求の範囲】 パッケージ本体(1)の内部に電源(又はグランド)(
19)を備えた終端抵抗(3)を実装し、 ワイヤパッド(14)、リード(16)、終端抵抗(3
)及び電源(19)をパターン(17、18、20、2
1)により、その一部の切断で少なくとも3種類の回路
構成するように接続する集積回路部品パッケージ。
[Claims] A power supply (or ground) (
A terminating resistor (3) with a wire pad (14), a lead (16), and a terminating resistor (3) is mounted.
) and power supply (19) in the pattern (17, 18, 20, 2
According to 1), an integrated circuit component package that is connected to form at least three types of circuits by cutting a part of the package.
JP62005434A 1987-01-13 1987-01-13 Package for integrated circuit part Pending JPS63173347A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62005434A JPS63173347A (en) 1987-01-13 1987-01-13 Package for integrated circuit part

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62005434A JPS63173347A (en) 1987-01-13 1987-01-13 Package for integrated circuit part

Publications (1)

Publication Number Publication Date
JPS63173347A true JPS63173347A (en) 1988-07-16

Family

ID=11611088

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62005434A Pending JPS63173347A (en) 1987-01-13 1987-01-13 Package for integrated circuit part

Country Status (1)

Country Link
JP (1) JPS63173347A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03288463A (en) * 1990-04-05 1991-12-18 Mitsubishi Materials Corp Multilayer board with interposed resistor
JPH05183420A (en) * 1991-12-27 1993-07-23 Nec Corp Circuit component
US5811880A (en) * 1996-03-28 1998-09-22 Intel Corporation Design for mounting discrete components inside an integrated circuit package for frequency governing of microprocessors

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03288463A (en) * 1990-04-05 1991-12-18 Mitsubishi Materials Corp Multilayer board with interposed resistor
JPH05183420A (en) * 1991-12-27 1993-07-23 Nec Corp Circuit component
US5811880A (en) * 1996-03-28 1998-09-22 Intel Corporation Design for mounting discrete components inside an integrated circuit package for frequency governing of microprocessors

Similar Documents

Publication Publication Date Title
KR100340285B1 (en) Memory module having series-connected printed circuit boards
JPS63173347A (en) Package for integrated circuit part
JPH0786509A (en) Semiconductor integrated circuit
JP2630311B2 (en) Semiconductor integrated circuit device
JPS5814544A (en) Vessel for monolithic ic
JPH01132150A (en) Carrier substrate of semiconductor chip
JP2001094032A (en) Semiconductor device
JPS63188961A (en) Package for semiconductor integrated circuit
JP3166721B2 (en) Stack structure of stacked semiconductor device
JP3157547B2 (en) Semiconductor package
JP2662156B2 (en) Noise reduction device for integrated circuits
JPH0217692A (en) Repair wiring
JP3339521B2 (en) Signal transmission circuit
TW200307363A (en) Electronic circuit device and electronic device package
JPS62196854A (en) Semiconductor device
JPH0786446A (en) Ic package
JPH04243329A (en) Crosstalk reduction transmission circuit
JPS5932898B2 (en) High-density mounting structure
JP3112270B2 (en) High-speed logic circuit
JPH1012660A (en) Integrated circuit for surface mounting
JPH11135920A (en) Printed wiring board and clock skew control method
JPH03261152A (en) Semiconductor integrated circuit device
JPH04181748A (en) Tab tape
JPH07114217B2 (en) Tape carrier type semiconductor device
JPH02180062A (en) Package for semiconductor integrated circuit