JPH03274720A - Formation of semiconductor device - Google Patents
Formation of semiconductor deviceInfo
- Publication number
- JPH03274720A JPH03274720A JP7512190A JP7512190A JPH03274720A JP H03274720 A JPH03274720 A JP H03274720A JP 7512190 A JP7512190 A JP 7512190A JP 7512190 A JP7512190 A JP 7512190A JP H03274720 A JPH03274720 A JP H03274720A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- resist
- resist pattern
- pattern
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 230000015572 biosynthetic process Effects 0.000 title abstract description 3
- 238000000034 method Methods 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 239000000463 material Substances 0.000 claims description 5
- 239000010410 layer Substances 0.000 abstract description 19
- 238000005468 ion implantation Methods 0.000 abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 6
- 239000002344 surface layer Substances 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 238000011109 contamination Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 230000002209 hydrophobic effect Effects 0.000 description 1
- 125000002887 hydroxy group Chemical group [H]O* 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000002052 molecular layer Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Formation Of Insulating Films (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体基板上の絶縁膜の上にレジストパター
ンを形成する際、そのレジストパターンの付着力を向上
を図った半導体装置の形成方法に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for forming a semiconductor device that improves the adhesion of a resist pattern when forming a resist pattern on an insulating film on a semiconductor substrate. It is something.
第3図は従来の半導体装置のレジストパターンの形成方
法を示す製造工程断面図である。図において、(1)は
半導体基板、(2)は半導体基板(1)の上に形成しで
ある絶縁膜、+4)は絶縁膜(2)の膜上にパターン(
5)を形成するためのフォトレジストである。FIG. 3 is a cross-sectional view of a manufacturing process showing a conventional method of forming a resist pattern for a semiconductor device. In the figure, (1) is a semiconductor substrate, (2) is an insulating film formed on the semiconductor substrate (1), and +4) is a pattern (+4) on the insulating film (2).
5) is a photoresist for forming.
次に製造工程について説明する。Next, the manufacturing process will be explained.
半導体プロセスでは半導体基板(11の表面を汚染やご
みから保護する目的で絶縁膜(2)でカバーした機番こ
((a)図〉、プロセスを流すのが一般的である。In the semiconductor process, it is common to run the process by covering the surface of the semiconductor substrate (11) with an insulating film (2) to protect it from contamination and dust.
次に、その絶縁膜(2)の加工等を行うため、その絶縁
[(21の上にフォトレジスト(4)の塗布を行いくイ
)図) レジストのパターン(41)を形成する((
C)図)。Next, in order to process the insulating film (2), a resist pattern (41) is formed ((Fig.
C) Diagram).
そして次工程で、レジストパターン(41)をマスク材
として加工を行い、所望のパターン(5)を半導体基板
(1)の表面に形成する。((d)図)〔発明が解決し
ようとする課題〕
従来の半導体装置のレジストパターンの形成方法は以上
のように形成されていたので、その表面は物理吸着した
HJ と表面のOH基に化学吸着したHtOが多分子層
になって形成され、このままの状態でフォトレジストの
塗布を行ってレジストパターンの形成を行うと、レジス
トのOH基と表面のHz0との水素結合による接着が起
こり、レジストの接着性が低下して、レジストパターン
の浮きや剥れが発生する等の問題点が発生し、この状態
では次工程において、レジストをマクス材として加工す
る事は、不可能となってしまうなどの問題点があった。In the next step, processing is performed using the resist pattern (41) as a mask material to form a desired pattern (5) on the surface of the semiconductor substrate (1). (Figure (d)) [Problems to be Solved by the Invention] In the conventional method of forming resist patterns for semiconductor devices, the resist pattern was formed as described above. The adsorbed HtO is formed as a multi-molecular layer, and when a photoresist is applied in this state to form a resist pattern, adhesion occurs due to hydrogen bonds between the OH groups of the resist and the Hz0 on the surface, and the resist The adhesiveness of the resist decreases, causing problems such as lifting and peeling of the resist pattern, and in this state, it becomes impossible to process the resist as a masking material in the next process. There was a problem.
この発明は上記のような問題点を解消するためになされ
たもので、この発明は絶縁膜の表面を改質してレジスト
の付着力を向上させた後にレジストパターンを形成して
、それをマスク材として所望のパターンを基板表面に加
工できるようにする事を目的とする。This invention was made in order to solve the above-mentioned problems.This invention improves the adhesion of the resist by modifying the surface of the insulating film, forms a resist pattern, and uses it as a mask. The purpose is to make it possible to process a desired pattern on the surface of a substrate as a material.
(llflを解決するための手段〕
この発明に係る半導体装置の形成方法は、半導体基板表
面上に絶縁膜を形成した後に、絶縁膜の表面層にレジス
ト付着力が向上するように例えば、イオン注入法によっ
てダメージ層を形成するようにしたものである。(Means for Solving llfl) In the method for forming a semiconductor device according to the present invention, after forming an insulating film on the surface of a semiconductor substrate, for example, ion implantation is performed to improve resist adhesion to the surface layer of the insulating film. The damaged layer is formed by a method.
この発明における半導体装置の形成方法は、絶縁膜の表
面層にイオン注入法によりダメージ層を形成し、このダ
メージ層によりレジストの付着力が向上しレジストパタ
ーン剥れの発生が防止され、レジストパターンをマクス
材として基板表面に所望のパターンを加工する事が可能
となる。In the method for forming a semiconductor device according to the present invention, a damaged layer is formed on the surface layer of an insulating film by ion implantation, and this damaged layer improves the adhesion of the resist and prevents the occurrence of resist pattern peeling. It becomes possible to process a desired pattern on the surface of a substrate as a masking material.
以下、この発明の一実施例を図について説明する。第1
図において、(1)は半導体基板、(2)は絶縁膜、(
3)は絶縁膜(2)の表面層に形成したダメージ層、(
4)はフォトレジスト、(5)は形成された所望のパタ
ーンである。An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, (1) is a semiconductor substrate, (2) is an insulating film, (
3) is a damaged layer formed on the surface layer of the insulating film (2), (
4) is a photoresist, and (5) is a desired pattern formed.
次にその製造工程について説明する。前記従来のものと
同様に半導体基板(11に絶縁ill 121を形成す
る((a)図)。次いでその絶縁1a(2)の表面層に
イオン注入を行ってダメージ層(3)を形成する(Cb
1図)。Next, the manufacturing process will be explained. As in the conventional case, an insulating ill 121 is formed on the semiconductor substrate (11 (Figure (a)). Next, ions are implanted into the surface layer of the insulating layer 1a (2) to form a damaged layer (3). Cb
Figure 1).
次に、フォトレジスト(4)膜を塗布しく(C)図)、
所望のレジストパターン(41)を形成する。この際、
レジストパターン(41)は絶縁膜(2)の表面に形成
されたダメージ層(3)の効果によって付着力が向上し
ており、レジストパターン(41)の浮きや剥れといっ
た問題は発生しない。最後にレジストパターン(41)
をマスクとして、絶縁膜(2)を加工して所望のパター
ン(5)を得る。Next, apply a photoresist (4) film (Figure C).
A desired resist pattern (41) is formed. On this occasion,
The adhesion of the resist pattern (41) is improved by the effect of the damage layer (3) formed on the surface of the insulating film (2), and problems such as lifting and peeling of the resist pattern (41) do not occur. Finally, the resist pattern (41)
Using as a mask, the insulating film (2) is processed to obtain a desired pattern (5).
特に、絶縁Ill 121の表面にダメージ層(3)を
形成した場合と形成しない場合、又は、そのダメージ層
(3)と付着力強度の関係を第2図に示す。図中、縦軸
はウェハ表面の状態(親水性か2疎水性か)を表わす水
滴の接触角を表わしている。一般に、接触角が大きけれ
ば疎水性となりレジストの付着力は大きくなり、小さく
なればその逆である。ゆえに、接触角とレジストの付着
力の大きさは比例関係にある。又、横軸はイオン注入エ
ネルギーを表わしており、これもダメージ層のダメージ
の大きさを表わしていることとなり比例関係がある。図
中、イオン注入を行わない場合と行なった場合とでは、
表面の接触角に大きな違いが確認できる。In particular, FIG. 2 shows the cases in which a damaged layer (3) is formed on the surface of the insulating layer 121 and the cases in which it is not formed, as well as the relationship between the damaged layer (3) and the adhesion strength. In the figure, the vertical axis represents the contact angle of a water droplet, which indicates the state of the wafer surface (hydrophilic or dihydrophobic). Generally, the larger the contact angle, the more hydrophobic the resist will be, and the stronger the adhesion of the resist will be, and vice versa, if the contact angle is smaller. Therefore, the contact angle and the magnitude of the adhesive force of the resist are in a proportional relationship. Further, the horizontal axis represents the ion implantation energy, which also represents the magnitude of damage to the damaged layer, so there is a proportional relationship. In the figure, when ion implantation is not performed and when it is performed,
A large difference can be seen in the contact angle of the surfaces.
これは、表面にダメージ層を形成した場合レジストの付
着力が改善されている事を示している。This indicates that the adhesion of the resist is improved when a damaged layer is formed on the surface.
なお、上記実施例では絶縁膜(2)の表面にダメージ層
(3)を形成する方法としてイオン注入法による場合に
ついて説明したが、例えばプラズマイオン等による方法
であっても上記実施例と同様の効果を奏する。In addition, in the above embodiment, the method of forming the damaged layer (3) on the surface of the insulating film (2) was explained using the ion implantation method. be effective.
又、上記実施例ではレジストパターンをマスクとして加
工する場合について説明したが、それ以外の工程、例え
ばイオン注入、電極形成等の工程に適用しても同様の効
果を奏する。Further, in the above embodiments, the case where processing is performed using a resist pattern as a mask has been described, but the same effect can be obtained even if the present invention is applied to other processes such as ion implantation, electrode formation, etc.
以上のようにこの発明によれば、絶縁膜の表面にダメー
ジ層を形成する事により、レジストの付着力を改善する
事が可能となり、所望のパターンを半導体基板表面に高
精度に問題なく形成する事ができ、高品質な半導体装置
を大量に得ることが可能となる。As described above, according to the present invention, by forming a damaged layer on the surface of an insulating film, it is possible to improve the adhesion of the resist, and a desired pattern can be formed on the surface of a semiconductor substrate with high precision and without problems. This makes it possible to obtain high-quality semiconductor devices in large quantities.
第1図+al〜(e)はこの発明の一実施例による半導
体装置の形成方法を示す製造工程断面図、第2図はこの
発明のレジストの付着力強度を表わす表面接触角とダメ
ージ層の強度を表わすイオン注入の注入エネルギーの関
係を示したグラフ、第3図は従来の半導体装置の形成方
法を示す製造工程断面図である。
図中、(1)は半導体基板、(2)は絶縁膜、(3)は
ダメージ層、(4)はフォトレジスト、(41)はレジ
ストパターン、(5)は加工されたパターンを示す。
なお、図中、同一符号は同一、又は相当部分を示す。Figures 1+al to (e) are manufacturing process cross-sectional views showing a method for forming a semiconductor device according to an embodiment of the present invention, and Figure 2 is a surface contact angle showing the adhesive strength of the resist of the present invention and the strength of the damaged layer. FIG. 3 is a graph showing the relationship between the implantation energy of ion implantation and FIG. 3 is a cross-sectional view of the manufacturing process showing a conventional method for forming a semiconductor device. In the figure, (1) is a semiconductor substrate, (2) is an insulating film, (3) is a damaged layer, (4) is a photoresist, (41) is a resist pattern, and (5) is a processed pattern. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
した後に、前記レジストパターンをマスク材として処理
を行う工程において、前記絶縁膜の表面に、ダメージ層
を形成することによって、前記レジストパターンの付着
力向上を図り、所望のパターンを形成できる様にしたこ
とを特徴とする半導体装置の形成方法。After forming a resist pattern on an insulating film on a semiconductor substrate, in a process of using the resist pattern as a mask material, a damaged layer is formed on the surface of the insulating film to improve the adhesion of the resist pattern. 1. A method for forming a semiconductor device, characterized by improving the ability to form a desired pattern.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7512190A JPH03274720A (en) | 1990-03-23 | 1990-03-23 | Formation of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7512190A JPH03274720A (en) | 1990-03-23 | 1990-03-23 | Formation of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03274720A true JPH03274720A (en) | 1991-12-05 |
Family
ID=13567054
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7512190A Pending JPH03274720A (en) | 1990-03-23 | 1990-03-23 | Formation of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03274720A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007184515A (en) * | 2005-12-30 | 2007-07-19 | Hynix Semiconductor Inc | Method of forming mask pattern for ion implantation and manufacturing method of semiconductor element |
-
1990
- 1990-03-23 JP JP7512190A patent/JPH03274720A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007184515A (en) * | 2005-12-30 | 2007-07-19 | Hynix Semiconductor Inc | Method of forming mask pattern for ion implantation and manufacturing method of semiconductor element |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4783238A (en) | Planarized insulation isolation | |
US20200156932A1 (en) | Method for Forming Hermetic Seals in MEMS Devices | |
JPH03274720A (en) | Formation of semiconductor device | |
JPS58166725A (en) | Forming method for opening section of laminated coating layer | |
JPH0297023A (en) | Manufacture of semiconductor device | |
KR960013140B1 (en) | Fabricating method of semiconductor device | |
JPH0346328A (en) | Manufacture of semiconductor device | |
JPH01123452A (en) | Formation of trench capacitor insulating film | |
JPS6312131A (en) | Manufacture of semiconductor device | |
JP2811724B2 (en) | Etching method | |
JPH0282527A (en) | Manufacture of semiconductor device | |
JPS6226812A (en) | Manufacture of semiconductor device | |
JPS59102235A (en) | Photomask | |
JPS57134929A (en) | Method for interconnection-pattern forming | |
JPS62222658A (en) | Formation of conductor wiring | |
JPS59145529A (en) | Method for formation of liftoff spacer | |
JPS6340367A (en) | Manufacture of semiconductor device | |
JPS61116842A (en) | Manufacture of semiconductor device | |
JPS61288426A (en) | Taper etching method for aluminum film | |
JPH054806B2 (en) | ||
JPS60254731A (en) | Manufacture of semiconductor device | |
JPH03254123A (en) | Selective etching method | |
JPH01204414A (en) | Manufacture of semiconductor device | |
JPS6314481A (en) | Manufacture of compound semiconductor element | |
JPH04158533A (en) | Fabrication of compound semiconductor device |