JPS60254731A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS60254731A
JPS60254731A JP11141184A JP11141184A JPS60254731A JP S60254731 A JPS60254731 A JP S60254731A JP 11141184 A JP11141184 A JP 11141184A JP 11141184 A JP11141184 A JP 11141184A JP S60254731 A JPS60254731 A JP S60254731A
Authority
JP
Japan
Prior art keywords
aluminum
alumina layer
resist
oxide film
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11141184A
Other languages
Japanese (ja)
Other versions
JPH0669033B2 (en
Inventor
Kiyoshi Watabe
渡部 潔
Katsunori Shimizu
清水 活憲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59111411A priority Critical patent/JPH0669033B2/en
Publication of JPS60254731A publication Critical patent/JPS60254731A/en
Publication of JPH0669033B2 publication Critical patent/JPH0669033B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To obtain a semiconductor device having flat surface of oxide film by executing dry etching after eliminating perfectly the alumina layer at the aluminum surface by the wet etching. CONSTITUTION:Aluminum 9 is vacuum deposited on an oxide film 7 formed on a silicon substrate 6 and an aperture 8 thereof and an alumina layer 10 is formed on aluminum 9 by natural oxidation or anode oxidation. Moreover, the alumina layer 10 is coated with the resist 11 only at the required area as the electrode of semiconductor device. The section of the alumina layer 10, where is not coated with resist 11 is eliminated by the wet etching utilizing acetic acid and ammonium fluoride. In this case, since the alumina layer 10 is perfectly removed, the surface of aluminum 9 can also be removed in such a thickness as 1,000-2,000Angstrom by the wet etching using organic alkali system or phosphoric acid. Moreover, aluminum 9 at the area not coated with resist 11 is removed by dry etching utilizing reactive ion etching and the resist 11 is finally removed.

Description

【発明の詳細な説明】 (1) 発明の技術分野 本発明は、アルミニウム電極のパターニングに係り、特
に酸化膜上に形成されるアルミニウム電極をドライエツ
チングによりパターニングする際。
DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to patterning of aluminum electrodes, and particularly to patterning of aluminum electrodes formed on oxide films by dry etching.

酸化膜を荒らさない半導体装置の製造方法に関するもの
である。
The present invention relates to a method of manufacturing a semiconductor device that does not damage an oxide film.

(2) 発明の背景 プレーナトランジスタ等の半導体装置の製造上。(2) Background of the invention For manufacturing semiconductor devices such as planar transistors.

アルミニウム電極の加工やフォトレジストの除去にエツ
チングが繰返し行なわれる。通寓このエツチングは不要
のアルミニウムやフォトレジストを液体を用いて除去す
るウェットエツチングと不要のアルミニウムやフォトレ
ジストをフン化炭素等のガス中で、プラズマを用いて溶
かすドライエツチングがある。
Etching is repeatedly performed to process aluminum electrodes and remove photoresist. Generally speaking, there are two types of etching: wet etching, which uses a liquid to remove unnecessary aluminum and photoresist, and dry etching, which uses plasma to dissolve unnecessary aluminum and photoresist in a gas such as carbon fluoride.

ドライエツチングは人手による薬品の純度等の管理が不
要で2作業工程を機械作業に置き換えることが簡単にで
きるので現在特に利用されている。
Dry etching is particularly used at present because it does not require manual control of the purity of chemicals and can easily replace two work steps with machine work.

(3) 従来技術と問題点 第1図+al〜tc)は半導体装置において、アルミニ
ウム電極をドラ・イエソチングにより加工する製造プロ
セスを示すものである。
(3) Prior art and problems FIG. 1 +al to tc) shows a manufacturing process in which an aluminum electrode is processed by dry isoetching in a semiconductor device.

まず、同図(alに示すようにシリコン(St)基板1
上に形成した酸化ケイ素(SiO2)の酸化膜2と酸化
膜2の開口部2a上にアルミニウム(Aβ)3を蒸着さ
せ、アルミニウム3上にアルミナ層4を自然酸化または
陽極酸化により形成し、さらにアルミナ層4上に電極と
して必要な部分のみレジスト5を塗布してアルミニウム
電極のパターニングを行う。次に同図(b)に示すよう
に、レジスト5が塗布されていない部分のアルミナ層4
をドライエンチングにより除去する。さらに同図tel
に示すプロセスでレジストが塗布されていない部分のア
ルミニウム3をドライエツチングにより除去し。
First, as shown in the same figure (al), a silicon (St) substrate 1
Aluminum (Aβ) 3 is deposited on the silicon oxide (SiO2) oxide film 2 formed above and the opening 2a of the oxide film 2, and an alumina layer 4 is formed on the aluminum 3 by natural oxidation or anodic oxidation. A resist 5 is applied onto the alumina layer 4 only on the portions required as electrodes, and the aluminum electrodes are patterned. Next, as shown in FIG.
is removed by dry enching. In addition, the same figure tel.
In the process shown in Figure 3, the aluminum 3 in the areas where the resist is not coated is removed by dry etching.

最後にレジスト5を除去する。Finally, the resist 5 is removed.

以上のようなプロセスにより酸化膜2および酸化膜2の
開口部にアルミニウム3の電極パターニングを行なって
いた。
Through the process described above, electrode patterning of aluminum 3 was performed on the oxide film 2 and the openings of the oxide film 2.

しかしながら、この際、ドライエツチングとしてリアク
ティブイオンエツチング(RIE)を用いるため、アル
ミニウム3表面に形成されたアルミナ層4は同図(b)
に示すように凹凸をもった段差のあるエツチングが行な
われる。
However, since reactive ion etching (RIE) is used as dry etching at this time, the alumina layer 4 formed on the surface of the aluminum 3 is
As shown in the figure, etching with uneven steps is performed.

さらにこの段差はアルミニウム3をエツチングする際、
絶縁層である酸化膜2まで影響し、同図(C)に示す様
に酸化膜2の表面に凹凸ができる。すなわち、ドライエ
ツチング前の酸化膜2は4000人程の厚さであるが、
ドライエツチング後には凸部は約3000人、凹部は約
1000人の厚さとなる。この酸化膜2は半導体装置の
絶縁層であり、酸化膜2に凹凸が生じると凹部で絶縁不
良を起こし短絡の原因ともなる。
Furthermore, this step is created when etching aluminum 3.
The oxide film 2, which is an insulating layer, is also affected, and the surface of the oxide film 2 becomes uneven, as shown in FIG. 2(C). In other words, the oxide film 2 before dry etching has a thickness of about 4000 mm.
After dry etching, the thickness of the convex portions is approximately 3000 mm and the thickness of the concave portions is approximately 1000 mm. This oxide film 2 is an insulating layer of a semiconductor device, and when unevenness occurs in the oxide film 2, insulation failure occurs in the depressions, which may cause a short circuit.

また、酸化膜2に生じる凹部がシリコン基板1にまで達
することを少なくするためには、アルミニウム3のドラ
イエツチングの時間を微細に管理せねばならないという
欠点があった。
Furthermore, in order to prevent the recesses formed in the oxide film 2 from reaching the silicon substrate 1, the dry etching time of the aluminum 3 must be carefully controlled.

(4) 発明の目的 本発明は、上述の従来の欠点に鑑み、アルミニウム表面
のアルミナ層をウェットエツチングにより完全に除去し
た後、ドライエツチングを行なうことにより酸化膜の表
明に凹凸が生じることのない半導体装置の製造方法を提
供することを目的とする。
(4) Purpose of the Invention In view of the above-mentioned conventional drawbacks, the present invention provides a method to completely remove the alumina layer on the aluminum surface by wet etching, and then perform dry etching to prevent unevenness from occurring on the surface of the oxide film. The purpose of the present invention is to provide a method for manufacturing a semiconductor device.

(5) 発明の要点 上記目的は1本発明によれば、半導体基板の表面に絶縁
膜を形成し、該絶縁膜上にアルミニウム層を形成する工
程と、該アルミニウム層上に所定のパターン膜を形成し
該パターン膜をマスクにしてアルミニウム層表面のアル
ミナ層をウェットエツチングによって完全に除去する工
程と、該パターン膜をマスクにしてアルミニウム層をド
ライエツチングによって除去する工程とよりなる半導体
装置の製造方法を提供することによって達成される。
(5) Summary of the Invention The above object is achieved by the following steps: (1) According to the present invention, an insulating film is formed on the surface of a semiconductor substrate, an aluminum layer is formed on the insulating film, and a predetermined pattern film is formed on the aluminum layer. A method for manufacturing a semiconductor device comprising the steps of: completely removing the alumina layer on the surface of the aluminum layer by wet etching using the patterned film as a mask; and removing the aluminum layer by dry etching using the patterned film as a mask. This is achieved by providing

(6) 発明の実施例 以下2本発明の実施例を添付図面にしたがって詳述する
(6) Embodiments of the Invention The following two embodiments of the present invention will be described in detail with reference to the accompanying drawings.

第2図において、シリコン基板6上に形成した酸化膜7
及び酸化膜7の開口部8に、同図+a)で示すプロセス
でアルミニウム9をたとえば1μm厚に蒸着させ、アル
ミニウム9上にアルミナ層1゜を自然酸化または陽極酸
化により形成する。さらにアルミナ層10上に半導体装
置の電極として必要な部分のみレジスト11を塗布する
。次に同図Tblに示すプロセスで、酢酸とフン化アン
モニウムを用いたウェットエツチングによりレジスト1
1を塗布していない部分のアルミナ層10を除去する。
In FIG. 2, an oxide film 7 formed on a silicon substrate 6
Then, aluminum 9 is deposited to a thickness of, for example, 1 μm in the opening 8 of the oxide film 7 by the process shown in +a) in the figure, and an alumina layer of 1° is formed on the aluminum 9 by natural oxidation or anodic oxidation. Furthermore, a resist 11 is applied onto the alumina layer 10 only in the portions required as electrodes of the semiconductor device. Next, in the process shown in Tbl in the same figure, the resist 1 is etched by wet etching using acetic acid and ammonium fluoride.
The portions of the alumina layer 10 to which 1 is not coated are removed.

この時アルミナ層10を完全に除去するため。In order to completely remove the alumina layer 10 at this time.

有機アルカリ系またはリン酸を用いてウェットエツチン
グによりアルミニウム9の表面も厚さ1000人〜20
00人程度除去する。さらに同図(C1に示すプロセス
でレジスト11が塗布されていない部分のアルミニウム
9をリアクティブイオンエツチングを用いたをドライエ
ツチングにより除去し、最後にレジスト11を除去する
The surface of aluminum 9 can also be etched to a thickness of 1,000 to 20 mm by wet etching using organic alkali or phosphoric acid.
About 00 people will be removed. Further, in the process shown in the same figure (C1), the portions of the aluminum 9 on which the resist 11 is not applied are removed by dry etching using reactive ion etching, and finally the resist 11 is removed.

以上のようなプロセスによりシリコン基板6上にアルミ
ニウム9の電極を設けることができる。
Through the process described above, an electrode made of aluminum 9 can be provided on the silicon substrate 6.

このようにアルミニウム9表面のアルミナ層10をまず
ウェットエツチングを行なうことにより除去すると、従
来アルミナ層10をドライエツチングによって除去する
際生じた凹凸は生じない。
When the alumina layer 10 on the surface of the aluminum 9 is first removed by wet etching in this way, the unevenness that conventionally occurs when the alumina layer 10 is removed by dry etching does not occur.

さらにアルミナ層10に凹凸が発生しないため。Furthermore, unevenness does not occur in the alumina layer 10.

その後ドライエツチングを行なってアルミニウム9を全
て除去しても、酸化膜7の表面が凹凸になることはない
。したがって酸化膜7の表面は平坦であり、酸化膜7の
厚さは3000A程度を有し酸化膜7の各部で一定厚で
ある。したがって外部の導電物質に対してアルミニウム
9の電極とシリコン6は確実な絶縁が行なわれる。
Even if dry etching is then performed to remove all of the aluminum 9, the surface of the oxide film 7 will not become uneven. Therefore, the surface of the oxide film 7 is flat, the thickness of the oxide film 7 is about 3000 Å, and the thickness is constant at each part of the oxide film 7. Therefore, the aluminum electrode 9 and the silicon 6 are reliably insulated from the external conductive material.

本発明は以上の実施例に限るわけではなく、アルミニウ
ム9とアルミナ層10をウェットエツチングにより除去
する際、アルミニウム9を除去する厚さは1000人〜
2000人に限らず他の厚さ分除去しても実施すること
ができる。
The present invention is not limited to the above embodiments, and when removing the aluminum 9 and the alumina layer 10 by wet etching, the thickness of the aluminum 9 to be removed is 1000 ~
The removal is not limited to 2,000 people, but can be performed even if other thicknesses are removed.

(7) 発明の効果 以上詳細に説明したように本発明によれば、半導体の絶
縁膜である酸化膜に凹凸が生じないので半導体装置の絶
縁を確実に行うことができる。
(7) Effects of the Invention As described in detail above, according to the present invention, since no unevenness occurs in the oxide film which is the insulating film of the semiconductor, it is possible to reliably insulate the semiconductor device.

また、酸化膜7に凹凸を生じないので、アルミニウム9
のドライエツチングのエツチング時間の管理が容易とな
る。
In addition, since the oxide film 7 does not have any unevenness, the aluminum 9
Etching time for dry etching can be easily managed.

【図面の簡単な説明】[Brief explanation of drawings]

第1図+al〜(C1は従来の半導体装置の製造工程図
第2図+a)〜lc)は本発明の半導体装置の製造工程
図である。 6・・・シリコン、 7・・・酸化膜。 9・・・アルミニウム、 10・・・アルミナ層、 1
1・・・レジスト 第1図 (b) (C) 第2図 (b) (C)
1+al~(C1 is a manufacturing process diagram of a conventional semiconductor device. FIGS. 2+a)~lc) are manufacturing process diagrams of a semiconductor device of the present invention. 6...Silicon, 7...Oxide film. 9... Aluminum, 10... Alumina layer, 1
1...Resist Figure 1 (b) (C) Figure 2 (b) (C)

Claims (2)

【特許請求の範囲】[Claims] (1)半導体基板の表面に絶縁膜を形成し、該絶縁膜上
にアルミニウム層を形成する工程と、該アルミニウム層
上に所定のパターン膜を形成し該パターン膜をマスクに
してアルミニウム眉表面のアルミナ層をウェットエツチ
ングによって完全に除去する工程と、該パターン膜をマ
スクにしてアルミニウム層をドライエツチングによって
除去する゛工程とよりなる半導体装置の製造方法。
(1) A process of forming an insulating film on the surface of a semiconductor substrate and forming an aluminum layer on the insulating film, forming a predetermined pattern film on the aluminum layer, and using the pattern film as a mask to form an aluminum layer on the aluminum surface. A method for manufacturing a semiconductor device comprising the steps of completely removing an alumina layer by wet etching, and removing the aluminum layer by dry etching using the patterned film as a mask.
(2)前記ウェットエツチング工程はアルミナ層を除去
してからアルミニウム層の極表面層もエソチチングする
ことを特徴とする特許請求の範囲第1項記載の半導体装
置の製造方法。
(2) The method of manufacturing a semiconductor device according to claim 1, wherein the wet etching step includes etching the extreme surface layer of the aluminum layer after removing the alumina layer.
JP59111411A 1984-05-31 1984-05-31 Method for manufacturing semiconductor device Expired - Lifetime JPH0669033B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59111411A JPH0669033B2 (en) 1984-05-31 1984-05-31 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59111411A JPH0669033B2 (en) 1984-05-31 1984-05-31 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS60254731A true JPS60254731A (en) 1985-12-16
JPH0669033B2 JPH0669033B2 (en) 1994-08-31

Family

ID=14560476

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59111411A Expired - Lifetime JPH0669033B2 (en) 1984-05-31 1984-05-31 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH0669033B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7196016B2 (en) * 2003-09-29 2007-03-27 Hitachi Global Storage Technologies Netherlands, B.V. Fabrication process for preparing recording head sliders made from silicon substrates with SiO2 overcoats

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57180149A (en) * 1981-04-30 1982-11-06 Nec Corp Manufacture of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57180149A (en) * 1981-04-30 1982-11-06 Nec Corp Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7196016B2 (en) * 2003-09-29 2007-03-27 Hitachi Global Storage Technologies Netherlands, B.V. Fabrication process for preparing recording head sliders made from silicon substrates with SiO2 overcoats

Also Published As

Publication number Publication date
JPH0669033B2 (en) 1994-08-31

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