JPH03273696A - Manufacture of multilayer ceramic circuit substrate - Google Patents
Manufacture of multilayer ceramic circuit substrateInfo
- Publication number
- JPH03273696A JPH03273696A JP7188090A JP7188090A JPH03273696A JP H03273696 A JPH03273696 A JP H03273696A JP 7188090 A JP7188090 A JP 7188090A JP 7188090 A JP7188090 A JP 7188090A JP H03273696 A JPH03273696 A JP H03273696A
- Authority
- JP
- Japan
- Prior art keywords
- green sheet
- void volume
- multilayer ceramic
- ceramic circuit
- circuit substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 239000000758 substrate Substances 0.000 title abstract description 3
- 239000000843 powder Substances 0.000 claims abstract description 5
- 239000011347 resin Substances 0.000 claims abstract description 5
- 229920005989 resin Polymers 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 4
- 239000010410 layer Substances 0.000 abstract description 10
- 230000032798 delamination Effects 0.000 abstract description 9
- 239000011229 interlayer Substances 0.000 abstract description 7
- 238000001035 drying Methods 0.000 abstract description 6
- 239000000203 mixture Substances 0.000 abstract description 6
- 238000003475 lamination Methods 0.000 abstract description 3
- 239000011800 void material Substances 0.000 abstract 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000011230 binding agent Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000004014 plasticizer Substances 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000007606 doctor blade method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
多層セラミック回路基板の製法に関し、４０層以上でも
デラミネーションのない多層セラミック回路基板を提供
することを目的とし、グリーンシートとして空隙率５０
％以上のものを使用するように構成する。[Detailed Description of the Invention] [Summary] Regarding the manufacturing method of a multilayer ceramic circuit board, the purpose is to provide a multilayer ceramic circuit board without delamination even with 40 or more layers, and the purpose is to provide a multilayer ceramic circuit board with a porosity of 50 as a green sheet.
% or more.
本発明はコンピュータ等の電子機器に用いられる多層セ
ラミック回路基板の製法に係る。近年、コンピュータの
システムの高速化の要求に伴い、回路基板中での信号の
遅延を抑えることが必要になっできている。このため、
微細回路網を３次元的に、限られたスペース内で形成で
きる多層セラミック回路基板が注目され、現在回路基板
の主流になりつつある。複雑な長距離回路を基板内に収
めるためには、回路基板の暦数を増すことが望ましい。The present invention relates to a method for manufacturing a multilayer ceramic circuit board used in electronic equipment such as computers. In recent years, with the demand for faster computer systems, it has become necessary to suppress signal delays in circuit boards. For this reason,
Multilayer ceramic circuit boards that can form fine circuit networks three-dimensionally within a limited space have attracted attention and are currently becoming the mainstream of circuit boards. In order to accommodate complex long distance circuits within a board, it is desirable to increase the number of circuit boards.
従来法ではグリーンシートの積層体はつぎのように作製
していた。すなわち、セラミック粉末とバインダ、可塑
剤等の有機成分からなるグリーンシートを加熱し、グリ
ーンシート内の有機成分を再軟化させる。これが接着剤
として働く。さらに、加熱と同時に一軸方向に圧力を加
える。この温度を上げたときに得られる接着作用と圧力
によりグリーンシート積層体が得られる。すなわち、従
来は再軟化した樹脂を機械的に密着させていた。In the conventional method, a green sheet laminate was produced as follows. That is, a green sheet made of ceramic powder and organic components such as a binder and a plasticizer is heated to re-soften the organic components within the green sheet. This acts as an adhesive. Furthermore, pressure is applied in a uniaxial direction at the same time as heating. A green sheet laminate is obtained by the adhesive action and pressure obtained when the temperature is increased. That is, conventionally, re-softened resin was mechanically brought into close contact.
このような従来法による多層セラミック回路基板の層数
は４０層以下が一般的であった。これ以上、層数を増や
すと、層間のデラミネーションが起きていた。The number of layers of such a conventional multilayer ceramic circuit board is generally 40 or less. If the number of layers was increased beyond this point, delamination between the layers would occur.
これは、各層の配線パターンによる凹凸部に対して積層
時にグリーンシートが完全に密着するまで変形しきれな
い部分が残るためである。This is because there remains a portion that cannot be fully deformed until the green sheet is completely adhered to the uneven portions caused by the wiring patterns of each layer during lamination.
そこで、本発明は各層のグリーンシートの接着をより良
好にして層間デラミネーションを防止し、４０層以上の
多層セラミック回路基板の製造を可能にする方法を提供
することを目的とする。Therefore, an object of the present invention is to provide a method that improves the adhesion of green sheets of each layer to prevent interlayer delamination, thereby making it possible to manufacture a multilayer ceramic circuit board having 40 or more layers.
上記目的を遠戚するために、本発明はセラミック粉末と
樹脂を含んで成り空隙率が５０％以上のグリーンシート
を用いることを特徴とする多層セラミック回路基板の製
法を提供する。In order to achieve the above object, the present invention provides a method for manufacturing a multilayer ceramic circuit board using a green sheet containing ceramic powder and resin and having a porosity of 50% or more.
グリーンシートの空隙率は組成と乾燥条件により制御す
ることが可能である。普通のグリーンシートの製造条件
と自然乾燥では４０％位の空隙率が得られる。本発明は
これを５０％以上にしたことが特徴であるが、空隙率は
例えば９０％でも容易に調整できる。空隙率が５０％よ
り小さいと、積層時のグリーンシートの伸びが不足し、
配線パターンによる凹凸部を完全に包むように変形する
ことができないため、層間デラミネーションの原因にな
る。The porosity of the green sheet can be controlled by the composition and drying conditions. Under normal green sheet manufacturing conditions and natural drying, a porosity of about 40% can be obtained. The present invention is characterized in that the porosity is set to 50% or more, but the porosity can be easily adjusted to, for example, 90%. If the porosity is less than 50%, the elongation of the green sheet during lamination will be insufficient,
Since it cannot be deformed so as to completely envelop the irregularities caused by the wiring pattern, it causes interlayer delamination.
グリーンシート上加圧加熱すると、樹脂の軟化によりグ
リーンシートが伸びるほか、空隙が潰れてグリーンシー
トの伸び量が大きくなるように作用する。そのため、配
線パターンの凹凸部もより良好に包み込まれた一体化し
た積層体を得ることができる。このため、層間デラミネ
ーションも防止される。When the green sheet is pressurized and heated, the green sheet not only stretches due to the softening of the resin, but also works to collapse the voids and increase the amount of elongation of the green sheet. Therefore, it is possible to obtain an integrated laminate in which the uneven portions of the wiring pattern are better covered. Therefore, interlayer delamination is also prevented.
表１に示す組成のセラミック、ガラス粉末とバインダ、
可塑剤、溶剤を表２の割合に調合し、ボールミルで２０
時間混練した。得られたスラリーをドクターブレード法
で厚さ２００ｊ−のグリーンシートに成形した。なお、
この時成形後の乾燥は４０℃で中千民半ミ行った。得ら
れたグリーンシートは厚みと重量より空隙率を求めたと
ころ、空隙率は５３％であった。Ceramic, glass powder and binder having the composition shown in Table 1,
Mix the plasticizer and solvent in the proportions shown in Table 2, and use a ball mill to
Kneaded for hours. The obtained slurry was formed into a green sheet with a thickness of 200J- by a doctor blade method. In addition,
At this time, drying after molding was carried out at 40°C for half a minute. The porosity of the obtained green sheet was determined from the thickness and weight and was found to be 53%.
次に、これらのグリーンシートを１００ｆｉ角に切断し
、さらにパンチによりピアホールを形成した。Next, these green sheets were cut into 100fi square pieces, and pier holes were formed by punching.
この後、ピアホール中に銅ペーストを印刷充填した。つ
ぎに、表面の回路を銅ペーストを用いて印刷した。つぎ
に、これらの印刷済グリーンシートを４５枚重ね合わせ
、金型内に入れ、温度１５０℃、圧力２０ＭＰａでプレ
スし、積層した。このグリーンシート積層体を窒素雰囲
気、１０００℃、５時間で焼成し、回路基板を得た。After this, copper paste was printed and filled into the pier holes. Next, a circuit on the surface was printed using copper paste. Next, 45 of these printed green sheets were stacked, placed in a mold, and pressed at a temperature of 150° C. and a pressure of 20 MPa to laminate them. This green sheet laminate was fired in a nitrogen atmosphere at 1000° C. for 5 hours to obtain a circuit board.
表１ セラミック、ガラスの調合組成
表２ グリーンシートの調合組成
次に上記と同様にして、但し、乾燥条件を変えたり、圧
縮して空隙率を調整したグリーンシートを用い、かつ積
層数を変えて多層基板を作製し、層間デラミネーション
の有無を調べた。結果を表３に示す。Table 1 Preparation composition of ceramic and glass Table 2 Preparation composition of green sheet Next, do the same as above, but change the drying conditions, use a green sheet whose porosity has been adjusted by compressing it, and change the number of laminated layers. A multilayer substrate was manufactured and the presence or absence of interlayer delamination was examined. The results are shown in Table 3.
表３
〔発明の効果〕
本発明によれば、密着性の良い一体の超多層グリーンシ
ート積層体が得られるので、層間デラミのない超多層セ
ラミック回路基板が得られる。Table 3 [Effects of the Invention] According to the present invention, an integrated super-multilayer green sheet laminate with good adhesion can be obtained, and therefore a super-multilayer ceramic circuit board without interlayer delamination can be obtained.
Claims (1)
上のグリーンシートを用いることを特徴とする多層セラ
ミック回路基板の製法。1. A method for manufacturing a multilayer ceramic circuit board characterized by using a green sheet containing ceramic powder and resin and having a porosity of 50% or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7188090A JPH03273696A (en) | 1990-03-23 | 1990-03-23 | Manufacture of multilayer ceramic circuit substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7188090A JPH03273696A (en) | 1990-03-23 | 1990-03-23 | Manufacture of multilayer ceramic circuit substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03273696A true JPH03273696A (en) | 1991-12-04 |
Family
ID=13473278
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7188090A Pending JPH03273696A (en) | 1990-03-23 | 1990-03-23 | Manufacture of multilayer ceramic circuit substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03273696A (en) |
-
1990
- 1990-03-23 JP JP7188090A patent/JPH03273696A/en active Pending
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