JPH0417392A - Manufacture of multilayer ceramic wiring board - Google Patents

Manufacture of multilayer ceramic wiring board

Info

Publication number
JPH0417392A
JPH0417392A JP11983290A JP11983290A JPH0417392A JP H0417392 A JPH0417392 A JP H0417392A JP 11983290 A JP11983290 A JP 11983290A JP 11983290 A JP11983290 A JP 11983290A JP H0417392 A JPH0417392 A JP H0417392A
Authority
JP
Japan
Prior art keywords
wiring
laminate
substrate
wiring board
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11983290A
Other languages
Japanese (ja)
Inventor
Akizo Toda
堯三 戸田
Takeji Shiokawa
武次 塩川
Masao Sekihashi
関端 正雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11983290A priority Critical patent/JPH0417392A/en
Publication of JPH0417392A publication Critical patent/JPH0417392A/en
Pending legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To reduce the warps of a wiring board by printing wiring conductors on ceramic green sheets, and laminating a plurality of them to make a laminate, and then forming ceramic layers without wiring on both top and under surfaces of the laminate, and, after sintering, removing the wiring-free layer by polishing. CONSTITUTION:A hole for through hole is opened in ceramic green sheet, and tungsten paste is filled up in this hole to form a green sheet where a tungsten conductor is wired, and ten green sheets are laminated to make a laminate, and further green sheets 20-250mum in thickness are put on both top and under surfaces of this laminate. This complete laminate is sintered in humidified hydrogen-nitrogen atmosphere to get a mullite ceramic sintered body which includes a tungsten wiring layer. Next, the top and the under surfaces 3 of this sintered body are ground with a diamond stone to remove wiring-free layers, thus a normal circuit board is obtained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、!子機器用多層セラミック配線基板に係り、
特に電子計算機用として好適な多層セラミンク基板に関
する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention has the following features: Regarding multilayer ceramic wiring boards for child devices,
In particular, the present invention relates to a multilayer ceramic substrate suitable for use in electronic computers.

〔従来の技術〕[Conventional technology]

近年、電子機器の小型化、高性能化、多機能化に伴い、
これに用いられる電子回路基板に対しても、高密度配線
化、高信頼度化が望まれている。
In recent years, as electronic devices have become smaller, more sophisticated, and more multifunctional,
High density wiring and high reliability are also desired for the electronic circuit boards used for this purpose.

殊に電子計算機用回路基板としては、高密度微細配線、
高速性、高信頼性などが重要であるため、回路基板素材
としては印刷配線を施したセラミックスが用いられてい
る。
Especially for computer circuit boards, high-density fine wiring,
Since high speed and high reliability are important, ceramics with printed wiring are used as the circuit board material.

一般に、多層セラミック回路基板は、絶縁体となるセラ
ミ−ツクスと導体となる金属とから構成されているが、
この両者の物理的、化学的性質は大きく異なっている。
Generally, a multilayer ceramic circuit board is composed of ceramics as an insulator and metal as a conductor.
The physical and chemical properties of the two are significantly different.

したがって、このような性質の異なる2種の物質を含む
複合体を高温に加熱して焼結すると、各々異なった収縮
挙動を示すために、焼結後の複合体は必然的に反りを生
ずる。
Therefore, when a composite body containing two types of materials having different properties is heated to a high temperature and sintered, the composite body after sintering inevitably warps because each material exhibits different shrinkage behavior.

この反りの大きさは、セラミックスと金属との比率、つ
まり基板の配線密度や、基板の上下面における配線パタ
ーンの対称性に依存し、さらに基板が大きくなるほど反
りも大きくなることが知られている。通常のセラミック
基板の反りは、基板長さ25m+n当り0.1mn、5
0mm当り0.15+nnであり、通常の回路基板では
この程度の反りがあっても十分使用可能である。しかし
高密度、多層配線を施す必要のある電子計算機用回路基
板では、長さ100圃当り0.05mn以下であること
が不可欠である。
The magnitude of this warpage depends on the ratio of ceramic to metal, that is, the wiring density of the board, and the symmetry of the wiring pattern on the top and bottom surfaces of the board, and it is known that the warp increases as the board becomes larger. . The warpage of a normal ceramic substrate is 0.1 mm per 25 m+n of substrate length, 5
This is 0.15+nn per 0 mm, and a normal circuit board can be sufficiently used even with this degree of warpage. However, for electronic computer circuit boards that require high-density, multilayer wiring, it is essential that the length be 0.05 mm or less per 100 fields.

従来、このようなセラミック基板の反り低減のために、
次のような方法が知られている。
Conventionally, in order to reduce warpage of such ceramic substrates,
The following methods are known.

1)焼結時のセラミック基板内の温度の不均一性が反り
の原因であると考え、できるだけ温度分布が均一になる
ように焼結条件を設定する方法。
1) A method of setting sintering conditions to make the temperature distribution as uniform as possible, assuming that the uneven temperature within the ceramic substrate during sintering is the cause of warping.

しかし、セラミック基板の構造から見て、この方法で基
板の反りを大幅に低減することは根本的に不可能に近い
However, considering the structure of the ceramic substrate, it is fundamentally impossible to significantly reduce the warpage of the substrate using this method.

2)−度焼結した基板に適量の重さの荷重を加えながら
再加熱し、この荷重によって基板の反りを修正する方法
。発明者らの検討によればこの方法によって基板の反り
を、修正前のそれよりも約半分に低減することができる
。しかし、元の基板の反りが大きいとき、あるいは反り
の形状が不規則なときには、上記荷重修正法によっても
反りを大幅に低減することはできなかった。
2) A method in which a sintered substrate is reheated while applying an appropriate amount of load, and the warpage of the substrate is corrected by this load. According to studies conducted by the inventors, this method can reduce the warpage of the substrate to approximately half of that before modification. However, when the original substrate has a large degree of warpage, or when the shape of the warp is irregular, it has not been possible to significantly reduce the warpage even by the above-mentioned load correction method.

3)反りのある焼結されたセラミック基板の表面を、研
削砥石などで平らに研削する方法。この方法は、反りを
無くするという点では非常に効果的であるが、第3図の
ように研削量が基板の場所によって異なるため基板内部
の配線導体の高さが不ぞろいになること、及び基板端部
の封止パターンが研削によって削りとられたり、パター
ン厚さが不足するなどの問題がある。
3) A method of grinding the warped surface of a sintered ceramic substrate flat using a grinding wheel or the like. This method is very effective in eliminating warpage, but as shown in Figure 3, the amount of grinding varies depending on the location of the board, so the height of the wiring conductor inside the board becomes uneven, and the board There are problems such as the end sealing pattern being removed by grinding or the pattern thickness being insufficient.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上記従来技術は、セラミック配線基板の反り低減に対す
る根本的対策が施されておらず、基板上に能動素子を搭
載したときの接続不良や、基板周辺の封止時の気密不良
を生ずるため、電子計算機などに必要とされる高密度配
線基板が得られないという問題があった。
The above-mentioned conventional technology does not take fundamental measures to reduce warpage of ceramic wiring boards, resulting in poor connections when active elements are mounted on the board and poor airtightness when sealing the periphery of the board. There was a problem in that high-density wiring boards required for computers and the like could not be obtained.

本発明の目的は、配線基板がセラミックスと導体金属と
いう異質の材料から成り、基板の反りはこの異種材料の
共存によって発生するという基本的考え方に立ち、上記
異種材料の効果を緩和させる作用をもつような基板構成
とすることによって配線基板の反りを低減させる方法を
堤供することにある。
The purpose of the present invention is based on the basic idea that wiring boards are made of different materials such as ceramics and conductive metals, and that the warpage of the board occurs due to the coexistence of these different materials, and that the present invention has an effect of mitigating the effects of the above-mentioned different materials. An object of the present invention is to provide a method for reducing warpage of a wiring board by having such a board configuration.

〔課題を解決するための手段〕[Means to solve the problem]

上記目的を達成するために本発明においては、セラミッ
クグリーンシートの上に配線導体を印刷形成し、これを
複数枚積層した積層体の上下両面に、無配線のセラミッ
ク層を、積層法あるいは印刷法によって形成し、これを
高温で焼結後、上記無配線層を研磨によって除去し、反
りの少ない配線基板を得るものである。
In order to achieve the above object, in the present invention, a wiring conductor is printed on a ceramic green sheet, and a non-wiring ceramic layer is placed on both upper and lower surfaces of a laminate made by laminating a plurality of these sheets using a laminating method or a printing method. After sintering this at high temperature, the non-wiring layer is removed by polishing to obtain a wiring board with less warpage.

〔作用〕[Effect]

前記のように、セラミック配線基板は2種の異質な材料
から構成されているため、その焼結過程における収縮率
差に起因して基板の反りを発生する9基板内における配
線パターンが上下左右で対象で、かつ焼結時の加熱が均
一に行われるならば基板に反りを生じないが、通常の配
線基板では、その上下面における配線パターンが同じで
対称形になることはないので反りを生ずることになる。
As mentioned above, since the ceramic wiring board is composed of two different materials, the wiring pattern within the board may warp due to the difference in shrinkage rate during the sintering process. If the substrate is symmetrical and heated evenly during sintering, the board will not warp, but in a normal wiring board, the wiring patterns on the top and bottom surfaces are the same and are not symmetrical, so warping occurs. It turns out.

そこで本発明は、実質的に上下面に配線パターンが異な
る基板であっても、その上下面に配線パターンを全く含
まないセラミック絶縁層を形成することにより、基板の
上下面におけるセラミックスが等価的に同じ配線パター
ンを持つようにしたものである。
Therefore, even if the wiring pattern is substantially different on the upper and lower surfaces of the substrate, the present invention forms a ceramic insulating layer that does not include any wiring pattern on the upper and lower surfaces, so that the ceramic on the upper and lower surfaces of the substrate is equivalently They are designed to have the same wiring pattern.

このような構成の基板を焼結すると、配線層を含む基板
内部の収縮は、従来構成の基板と同様に配線パターンの
対称性や比率に依存して進行し、反りが発生し易い状態
にある。しかし、基板上下面に存在する無配線層は、内
部の不均一収縮に逆らって均一に収縮するように作用し
、その結果基板の反りが減少するものである。このよう
にして作製した基板の上下面には、当然配線パターンが
存在せず、このままでは配線基板の役目を持たないので
、焼結後の基板の上下面を研削して無配線層のみを除去
し、配線パターンを露出させることにより配線基板が得
られる。
When a board with such a configuration is sintered, the shrinkage inside the board, including the wiring layer, progresses depending on the symmetry and ratio of the wiring pattern, as in the case of a board with a conventional configuration, and warping is likely to occur. . However, the non-wiring layers existing on the upper and lower surfaces of the substrate act to uniformly shrink against the non-uniform shrinkage inside, and as a result, the warpage of the substrate is reduced. Naturally, there is no wiring pattern on the top and bottom surfaces of the board manufactured in this way, and it does not have the role of a wiring board as it is, so the top and bottom surfaces of the board after sintering are ground to remove only the non-wiring layer. Then, by exposing the wiring pattern, a wiring board is obtained.

〔実施例〕〔Example〕

以下、本発明の実施例について述べる。 Examples of the present invention will be described below.

〔実施例1〕 ムライト微粉末(純度99.9% 、平均粒子径2μm
)75重量%に、5in2(純度99.9%平均粒子径
1.5μm )90重量%、Al1.0゜(純度99.
5% 、平均粒子径0.6μm)7重量%、MgO(純
度99.8%、平均粒子径0.3μm)3重量%の組成
を有する焼結助剤を25重量%添加し、さらに成形助剤
としてポリビニルブチラール樹脂、可塑剤としてフタル
酸エステル。
[Example 1] Mullite fine powder (purity 99.9%, average particle diameter 2 μm
) 75% by weight, 5in2 (purity 99.9% average particle diameter 1.5 μm) 90% by weight, Al 1.0° (purity 99.
25% by weight of a sintering aid having a composition of 7% by weight, MgO (purity 99.8%, average particle size 0.3μm), Polyvinyl butyral resin as an agent and phthalate as a plasticizer.

分散溶媒としてトリクロールエチレンを各々適量加え、
ボールミルにより十分混合した。
Add an appropriate amount of trichlorethylene as a dispersion solvent,
Thoroughly mixed using a ball mill.

このようにして得られたスラリー状の混合物を、ドクタ
ーブレード法により厚さ0.3mn のシートを成形し
た。このシートはグリーンシートと呼ばれ、多層セラミ
ックの基板の素材となるものである。
The slurry-like mixture thus obtained was formed into a sheet with a thickness of 0.3 mm by a doctor blade method. This sheet is called a green sheet and is the material for the multilayer ceramic substrate.

次に、このグリーンシート(120X120mm)にス
ルーホール用の穴をあけ、タングステンペーストをこの
穴の中に密充填して、基板の縦方向の配線とした。平面
方向の配線は、タングステンペーストを用いて行った。
Next, holes for through holes were made in this green sheet (120 x 120 mm), and tungsten paste was densely filled into the holes to form wiring in the vertical direction of the board. Wiring in the planar direction was performed using tungsten paste.

ここで用いたタングステンペーストは、平均粒子径1μ
mのタングステン粒末80重量%、ジエチレングリコー
ル・モノ・n−ブチルエーテルアセテート17.5重量
%エチルセルロース2.0重量% 、ポリビニルブチラ
ール0.5重量%より成るものである。
The tungsten paste used here had an average particle size of 1 μm.
80% by weight of tungsten powder, 17.5% by weight of diethylene glycol mono-n-butyl ether acetate, 2.0% by weight of ethyl cellulose, and 0.5% by weight of polyvinyl butyral.

以上のようにして、タングステン導体が配線されたグリ
ーンシート2を10枚積層し、さらにこの積層体の上下
両面に、0.3mn厚さのグリーンシート1を重ねて積
層した。この積層体を1630℃。
As described above, ten green sheets 2 each having a tungsten conductor wired thereon were laminated, and further, green sheets 1 having a thickness of 0.3 mm were laminated on both the upper and lower surfaces of this laminate. This laminate was heated to 1630°C.

2時間、加湿水素−窒素雰囲気中で焼結することにより
、第1図のようなタングステン配線層を含むムライト系
セラミック焼結体を得た。
By sintering in a humidified hydrogen-nitrogen atmosphere for 2 hours, a mullite ceramic sintered body including a tungsten wiring layer as shown in FIG. 1 was obtained.

この焼結体の反りは、長さ100m+n当り0.18m
mであった。このように本発明による基板の反りが小さ
いのは、積層時に積層体の上下面に無配線層を形成させ
て、焼結時の基板の上下面の収縮を均等に行わせたこと
によるものである。次にこの焼結体の上下面3を、ダイ
ヤモンド砥石で研削して第2図のように無配線層(約2
50μm)を除去して正常な回路基板を得た。この研磨
された基板の反りは、100nn長さ当り、0.008
mn  と非常に小さく、この上に薄膜パターンなどを
形成する上で十分な平坦性を有していた。
The warpage of this sintered body is 0.18m per 100m+n of length.
It was m. The reason why the substrate according to the present invention exhibits little warpage is due to the fact that non-wiring layers are formed on the top and bottom surfaces of the laminate during lamination, and the top and bottom surfaces of the substrate shrink evenly during sintering. be. Next, the upper and lower surfaces 3 of this sintered body are ground with a diamond grindstone to form a non-wiring layer (approximately 2
50 μm) was removed to obtain a normal circuit board. The warpage of this polished substrate is 0.008 per 100 nn length.
It had a very small mn, and had sufficient flatness to form a thin film pattern thereon.

一方、積層時に積層体の上下面に無配線層を設けず従来
法で作製した基板の反りは、長さ10011111当り
0 、32 no  と非常に大きかった。さらに、従
来法によるこの基板を平滑研削した結果、第3図のよう
に基板の内層の導体も研削されて失われてしまい1回路
基板としての性能を保持し得ないことが明らかになった
On the other hand, the warpage of the substrate produced by the conventional method without providing a non-wiring layer on the upper and lower surfaces of the laminate during lamination was as large as 0.32 no per 10011111 of the length. Furthermore, as a result of smooth grinding of this board using the conventional method, it became clear that the conductors in the inner layer of the board were also ground and lost, as shown in FIG. 3, and the performance as a single circuit board could not be maintained.

〔実施例2〕 実施例1と同様の方法で、ムライト系セラミックスのグ
リーンシート上にタングステン導体を印刷配線したシー
ト55枚を積層し、さらにその積層体の上下両面に、導
体無配線のグリーンシート(厚さ70μm)を各−枚ず
つ積層し、これを1630℃、3時間、加湿水素−窒素
中で焼結した。得られた基板の反りは、長さ10100
l当り0.006mbであった。次にこの基板の上下両
面をダイヤモンド砥石で平滑研削し、導体無配線層(厚
さ70μm)のみを除去した。この研磨基板の反りは長
さ100m当り、0.004mmで非常に平坦であった
[Example 2] In the same manner as in Example 1, 55 sheets with printed wiring of tungsten conductors were laminated on green sheets of mullite-based ceramics, and green sheets without conductor wiring were placed on both the top and bottom surfaces of the laminate. (thickness: 70 μm) were laminated one by one, and this was sintered at 1630° C. for 3 hours in a humidified hydrogen-nitrogen atmosphere. The warpage of the obtained substrate is 10100 mm in length.
It was 0.006 mb per liter. Next, both the upper and lower surfaces of this substrate were smooth-ground using a diamond grindstone to remove only the conductor-free layer (thickness: 70 μm). The warpage of this polished substrate was 0.004 mm per 100 m length, which was very flat.

これに対して、従来法によって作製した45層の積層体
を焼結したところ、基板の反りは長さ10010111
当り0.25mm と大きかった。この基板の上下両面
を平滑研磨した結果、基板の表面部に近い内層の厚さが
不均一となり5配線基板として不適当であった。
On the other hand, when we sintered a 45-layer stack made by the conventional method, the warpage of the substrate was 10010111
It was large at 0.25mm per hit. As a result of polishing the upper and lower surfaces of this substrate, the thickness of the inner layer near the surface of the substrate became uneven, making it unsuitable for use as a 5-wiring substrate.

〔実施例3〕 アルミナ微粉末(純度99.5% 、平均粒子径3μm
)92重量%と、5in2粉末(純度99.7%、平均
粒子径1.0μm ) 6重量%と、MgO粉末(純度
99.5%、平均粒子径0.5μm)2重量%、それに
実施例1と同様の有機バインダー、可塑剤2分散溶剤を
加えて十分混合後、ドクターブレード法によって厚さ0
.25nn+ のアルミナグリーンシートを作製した。
[Example 3] Alumina fine powder (purity 99.5%, average particle size 3 μm
) 92% by weight, 6% by weight of 5in2 powder (purity 99.7%, average particle size 1.0 μm), 2% by weight MgO powder (purity 99.5%, average particle size 0.5 μm), and Examples After adding the same organic binder and plasticizer 2 dispersion solvent as in 1 and mixing thoroughly, use the doctor blade method to reduce the thickness to 0.
.. A 25nn+ alumina green sheet was produced.

次に、このグリーンシート上に、実施例1と同様の方法
でタングステン導体の配線を施し、このようなシートを
30枚積層後、さらに積層体上下両面に無配線のアルミ
ナグリーンシート(厚さ120μm)を各−枚ずつ積層
した。続いてこの積層体を1590’C,2時間、加湿
水素−窒素中で焼結した。
Next, tungsten conductor wiring was applied to this green sheet in the same manner as in Example 1, and after laminating 30 such sheets, unwired alumina green sheets (thickness 120 μm ) were laminated one by one. The laminate was then sintered at 1590'C for 2 hours in a humidified hydrogen-nitrogen atmosphere.

得られた基板の反りは、長さ100mm当り0.11I
nと小さく、これを実施例1と同様に平滑研磨(研磨厚
さ約110μm)したところ、長さ100I当りの反り
が0.007nn という非常に平坦性の良い基板が得
られ、基板表面の配線層厚さにも問題はなかった。
The warpage of the obtained substrate was 0.11I per 100mm of length.
When this was polished smooth (polishing thickness: about 110 μm) in the same manner as in Example 1, a very flat substrate with a warp of 0.007 nn per 100 I of length was obtained, and the wiring on the surface of the substrate There was no problem with the layer thickness.

〔実施例4〕 アルミナ微粉末(純度99.5%、平均粒子径5μm)
55重量%に、はうけい酸ガラス微粉末(平均粒子径3
μm)45重量%を加え、さらにこれに対して有機バイ
ンダー、可塑剤2分散溶媒を適量加え、実施例1と同じ
方法で厚さ0.25Mのグリーンシートを得た。このグ
リーンシートの上にCuを主成分とする導体ペーストを
用いて、実施例1と同様の配線を施した。このように対
して作製したシートを15枚積層し、この積層体の上下
両面に無配線のグリーンシート(厚さ250μm)を各
−積層層し、950℃、4時間9弱酸化性窒素雰囲気中
で焼結した。
[Example 4] Alumina fine powder (purity 99.5%, average particle size 5 μm)
55% by weight, silicate glass fine powder (average particle size 3
A green sheet with a thickness of 0.25 M was obtained in the same manner as in Example 1 by adding an appropriate amount of an organic binder and a plasticizer 2 dispersion solvent to the green sheet. On this green sheet, wiring similar to that in Example 1 was provided using a conductive paste containing Cu as a main component. Fifteen sheets prepared in this way were stacked, and non-wired green sheets (thickness 250 μm) were layered on both the upper and lower surfaces of the stack, and the mixture was placed in a weakly oxidizing nitrogen atmosphere at 950°C for 4 hours. Sintered with

得られた基板の反りは、長さ10100a当り0.16
nunと小さく、これを実施例1と同様平滑研磨(研磨
置駒200μm厚さ)したところ、長さ100m当りの
反りが0.005μm という良い結果が得られた。
The warpage of the obtained substrate was 0.16 per 10100a of length.
When this was polished smooth (polishing piece 200 μm thick) in the same manner as in Example 1, good results were obtained with a warpage of 0.005 μm per 100 m length.

これに対して、積層体の上下面に無配線層を形成しない
従来法で作製した基板の反りは、長さ100mm当り、
0.35mm と非常に大きく、これを平滑研磨しても
基板表面部の導体層厚さに大きな不同を生ずるという問
題があった。
On the other hand, the warpage of a board manufactured by a conventional method that does not form a non-wiring layer on the upper and lower surfaces of the laminate is as follows per 100 mm in length.
The thickness was very large at 0.35 mm, and even if it was polished smooth, there was a problem in that there would be large variations in the thickness of the conductor layer on the surface of the substrate.

〔実施例5〕 実施例3と同様の方法でアルミナ系グリーンシートを用
いた40層配線の積層体を作り、その上下両面に、アル
ミナ系グリーンシート同じ組成のペーストをスクリーン
印刷法により厚さ80μmの無配線層を形成した。その
後、実施例3と同様の条件で焼結した。得られた基板の
反りは0.07mmで極めて小さかった。この焼結基板
をダイヤモンド砥石で厚さ80層m研磨した結果、基板
の10011111当りの反りは0 、0 O5nwo
であった。
[Example 5] A 40-layer wiring laminate using alumina green sheets was made in the same manner as in Example 3, and a paste of the same composition as the alumina green sheets was applied to the top and bottom surfaces of the laminate to a thickness of 80 μm by screen printing. A non-wiring layer was formed. Thereafter, sintering was carried out under the same conditions as in Example 3. The warpage of the obtained substrate was 0.07 mm, which was extremely small. As a result of polishing this sintered substrate to a thickness of 80 m with a diamond grindstone, the warpage per 10011111 of the substrate was 0,0 O5nwo.
Met.

一方、従来法によって作製した基板の反りは、長さ10
0mm当り、0.27mm と大きく、これを平滑研磨
しても、実用的な回路基板は得られなかった・ 〔実施例6〕 実施例4と同様の方法で、ガラスセラミックス系グリー
ンシートを用いた70層配線の積層体を作り、その上下
両面に、ガラスセラミックス系グリーンシート同じ組成
の絶縁ペーストをスクリーン印刷法により、厚さ15μ
mの無配線層を形成した。後、実施例4と同じ焼結条件
でこの積層体を焼結した。得られた基板の反りは、長さ
100百1当り、14μmであった。この基板の反りが
他の実施例のものより小さいのは積層数が多いためであ
る。
On the other hand, the warpage of the substrate produced by the conventional method is 10
It was large at 0.27 mm per 0 mm, and even if it was smoothed and polished, a practical circuit board could not be obtained. [Example 6] A glass-ceramic green sheet was used in the same manner as in Example 4. A 70-layer wiring laminate was made, and an insulating paste of the same composition as a glass-ceramic green sheet was printed on the top and bottom surfaces of the laminate to a thickness of 15μ by screen printing.
m non-wiring layers were formed. Thereafter, this laminate was sintered under the same sintering conditions as in Example 4. The warpage of the obtained substrate was 14 μm per 100 1/1 length. The reason why the warpage of this substrate is smaller than that of the other embodiments is because the number of laminated layers is large.

次に、焼結基板の上下両面をダイヤモンド砥石で研磨(
研磨置駒20μm厚さ)したところ、基板の長さ100
mm当りの反りは0.004μmであり、高密度配線に
好適な基板が得られた。
Next, the top and bottom surfaces of the sintered substrate are polished with a diamond grindstone (
When the polishing piece was 20 μm thick), the length of the substrate was 100 μm.
The warpage per mm was 0.004 μm, and a substrate suitable for high-density wiring was obtained.

一方、従来法によって、積層体の上下両面に無配線層を
設けないで作製した基板の反りは、長さ100nn当り
0.23mm と非常に大きく、実用性のある基板は得
られなかった。
On the other hand, the warpage of a substrate produced by the conventional method without providing a non-wiring layer on both the upper and lower surfaces of the laminate was as large as 0.23 mm per 100 nn of length, and a practical substrate could not be obtained.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、セラミックス系
回路基板の反りが非常に小さいために、電子計算機用と
して好適な高密度回路配線基板が可能となる。すなわち
、基板表面の配線導体の高さが均一であるため、能動素
子を搭載したときの接続不良や、基板周辺部の封止部の
気密不良などの問題がなくなり、信頼度の高い高密度配
線基板が得られる。
As explained above, according to the present invention, since the warpage of the ceramic circuit board is extremely small, a high-density circuit wiring board suitable for use in electronic computers is possible. In other words, since the height of the wiring conductor on the board surface is uniform, problems such as poor connection when mounting active elements and poor airtightness in the sealing area around the board are eliminated, allowing for highly reliable high-density wiring. A substrate is obtained.

さらに、焼結基板上面に、有機薄膜法などを用いて回路
パターンを形成する場合、薄膜層の段切れや、ふくれ等
の問題が無くなるという大きな効果もあり、超高密度配
線回路基板の性能向上と共に、基板製造上の歩留り向上
にも大きく寄与するものである。
Furthermore, when forming a circuit pattern on the top surface of a sintered substrate using an organic thin film method, etc., there is a significant effect of eliminating problems such as breakage and blistering of the thin film layer, improving the performance of ultra-high density wiring circuit boards. At the same time, it greatly contributes to improving the yield in manufacturing substrates.

【図面の簡単な説明】[Brief explanation of drawings]

第1図、第2図はいずれも本発明によるセラミック系回
路基板の断面模式図、第3図は従来法による回路基板の
断面模式図である。
1 and 2 are schematic cross-sectional views of a ceramic circuit board according to the present invention, and FIG. 3 is a schematic cross-sectional view of a circuit board according to a conventional method.

Claims (7)

【特許請求の範囲】[Claims] 1.複数枚のセラミックグリーンシートを積層,圧着し
、該積層体を焼結して多層セラミック配線基板を製造す
る方法において、上記積層体の上下両面に無配線の絶縁
層を形成し、焼結した後、該無配線層を研磨除去するこ
とを特徴とする多層セラミック配線基板の製法。
1. In a method of manufacturing a multilayer ceramic wiring board by laminating and pressing a plurality of ceramic green sheets and sintering the laminate, after forming a wiring-free insulating layer on both upper and lower surfaces of the laminate and sintering. . A method for producing a multilayer ceramic wiring board, characterized in that the non-wiring layer is removed by polishing.
2.請求項1記載の多層セラミック配線基板の製法にお
いて、上記研磨除去される無配線層の厚さが20〜25
0μmであることを特徴とする多層セラミック配線基板
の製法。
2. 2. The method for manufacturing a multilayer ceramic wiring board according to claim 1, wherein the thickness of the non-wiring layer to be removed by polishing is 20 to 25 mm.
A method for manufacturing a multilayer ceramic wiring board characterized by a thickness of 0 μm.
3.請求項1記載の多層セラミック配線基板の製法にお
いて、上記無配線の絶縁層として、セラミックグリーン
シートを用いることを特徴とする多層セラミック配線基
板の製法。
3. 2. The method of manufacturing a multilayer ceramic wiring board according to claim 1, wherein a ceramic green sheet is used as the non-wiring insulating layer.
4.請求項1記載の多層セラミック配線基板の製法にお
いて、絶縁体ペーストを用い、スクリーン印刷法によっ
て上記無配線絶縁層を形成することを特徴とする多層セ
ラミック配線基板の製法。
4. 2. The method of manufacturing a multilayer ceramic wiring board according to claim 1, wherein the wiring-free insulating layer is formed by a screen printing method using an insulating paste.
5.請求項3記載の多層セラミック配線基板の製法にお
いて、上記無配線の絶縁層として70〜300μm厚さ
のグリーンシートを用いることを特徴とする多層セラミ
ック配線基板の製法。
5. 4. The method of manufacturing a multilayer ceramic wiring board according to claim 3, wherein a green sheet having a thickness of 70 to 300 μm is used as the non-wiring insulating layer.
6.請求項4記載の多層セラミック配線基板の製法にお
いて、上記印刷厚さを15〜80μmとすることを特徴
とする多層セラミック配線基板の製法。
6. 5. The method for manufacturing a multilayer ceramic wiring board according to claim 4, wherein the printing thickness is 15 to 80 μm.
7.請求項1記載の多層セラミック配線基板の製法にお
いて、上記セラミックグリーンシートとして、アルミナ
系,ムライト系,ガラスセラミックス系の材料のいずれ
かを用いることを特徴とする多層セラミック配線基板の
製法。
7. 2. The method of manufacturing a multilayer ceramic wiring board according to claim 1, wherein the ceramic green sheet is made of an alumina-based, mullite-based, or glass-ceramic material.
JP11983290A 1990-05-11 1990-05-11 Manufacture of multilayer ceramic wiring board Pending JPH0417392A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11983290A JPH0417392A (en) 1990-05-11 1990-05-11 Manufacture of multilayer ceramic wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11983290A JPH0417392A (en) 1990-05-11 1990-05-11 Manufacture of multilayer ceramic wiring board

Publications (1)

Publication Number Publication Date
JPH0417392A true JPH0417392A (en) 1992-01-22

Family

ID=14771369

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11983290A Pending JPH0417392A (en) 1990-05-11 1990-05-11 Manufacture of multilayer ceramic wiring board

Country Status (1)

Country Link
JP (1) JPH0417392A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0591733A1 (en) * 1992-09-21 1994-04-13 Matsushita Electric Industrial Co., Ltd. Method for producing multilayered ceramic substrate
WO1999056510A1 (en) * 1998-04-24 1999-11-04 Matsushita Electric Industrial Co., Ltd. Method of producing ceramic multilayer substrate
JP2007053294A (en) * 2005-08-19 2007-03-01 Tdk Corp Process for manufacturing multilayer ceramic electronic component
JP2008066712A (en) * 2006-08-09 2008-03-21 Murata Mfg Co Ltd Multilayer capacitor, circuit substrate, circuit module, and manufacturing method for multilayer capacitor

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0591733A1 (en) * 1992-09-21 1994-04-13 Matsushita Electric Industrial Co., Ltd. Method for producing multilayered ceramic substrate
WO1999056510A1 (en) * 1998-04-24 1999-11-04 Matsushita Electric Industrial Co., Ltd. Method of producing ceramic multilayer substrate
KR100375486B1 (en) * 1998-04-24 2003-03-10 마쯔시다덴기산교 가부시키가이샤 Method of Producing Ceramic Multilayer Substrate
US6740183B1 (en) 1998-04-24 2004-05-25 Matsushita Electric Industrial Co., Ltd. Method of producing ceramic multi-layered substrate
JP2007053294A (en) * 2005-08-19 2007-03-01 Tdk Corp Process for manufacturing multilayer ceramic electronic component
JP2008066712A (en) * 2006-08-09 2008-03-21 Murata Mfg Co Ltd Multilayer capacitor, circuit substrate, circuit module, and manufacturing method for multilayer capacitor

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