JPH04125990A - Multilayered ceramic circuit board and manufacture thereof - Google Patents
Multilayered ceramic circuit board and manufacture thereofInfo
- Publication number
- JPH04125990A JPH04125990A JP24610990A JP24610990A JPH04125990A JP H04125990 A JPH04125990 A JP H04125990A JP 24610990 A JP24610990 A JP 24610990A JP 24610990 A JP24610990 A JP 24610990A JP H04125990 A JPH04125990 A JP H04125990A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- green sheets
- ceramic particles
- glass
- green sheet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 title claims abstract description 77
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000011159 matrix material Substances 0.000 claims abstract description 17
- 239000002245 particle Substances 0.000 claims description 63
- 239000011521 glass Substances 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 10
- 238000010304 firing Methods 0.000 claims description 9
- 239000011148 porous material Substances 0.000 claims description 6
- 238000010030 laminating Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 abstract description 6
- 238000000465 moulding Methods 0.000 abstract description 3
- 238000003475 lamination Methods 0.000 abstract 4
- 210000004907 gland Anatomy 0.000 abstract 2
- 230000002093 peripheral effect Effects 0.000 abstract 2
- KZHJGOXRZJKJNY-UHFFFAOYSA-N dioxosilane;oxo(oxoalumanyloxy)alumane Chemical compound O=[Si]=O.O=[Si]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O KZHJGOXRZJKJNY-UHFFFAOYSA-N 0.000 description 7
- 229910052863 mullite Inorganic materials 0.000 description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000010365 information processing Effects 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- 239000002002 slurry Substances 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 238000007606 doctor blade method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔概 要〕
多層セラミックス回路基板およびその製造方法に関し、
空孔を設けることにより誘電率を低下させながら機械的
強度を確保した多層セラミックス回路基板およびその製
造方法を提供することを目的とし、本発明の多層セラミ
ックス回路基板は、セラミックス粒子がガラスによって
結合されて成る絶縁性マトリクス中に配線が多層に配置
されている多層セラミックス回路基板において、配線周
囲領域のマトリクスはセラミックス粒子間に空孔が存在
することによって多孔質となっており、それ以外の領域
のマトリクスはセラミックス粒子間が実質的に全てガラ
スにより充填されていることによって緻密質となってい
るように構成し、
本発明の多層セラミックス回路基板の製造方法は、セラ
ミックスおよびガラスを主成分とするグリーンシートの
表面に配線層を形成し、該配線層を形成したグリーンシ
ートおよび形成しないグリーンシートを複数枚積層して
焼成することにより多層セラミックス回路基板を製造す
る方法において、表面に配線層を形成するグリーンシー
トおよび積層状態で配線層に直接接するグリーンシート
としてはセラミックス粒子の平均粒径が小さいグリーン
シートを用い、その他のグリーンシートとしてはセラミ
ックス粒子の平均粒径が大きいグリーンシートを用い、
これらのグリーンシートを所定順序に重ねたグリーンシ
ート積層体を、上記平均粒径の大きいセラミックス粒子
間をガラスが実質的に充填するのには十分で且つ上記平
均粒径の小さいセラミックス粒子間をガラスが充填する
のには不十分な温度で焼成するように構成する。[Detailed Description of the Invention] [Summary] Regarding a multilayer ceramic circuit board and a method for manufacturing the same, the present invention provides a multilayer ceramic circuit board and a method for manufacturing the same that ensure mechanical strength while lowering the dielectric constant by providing holes. A multilayer ceramic circuit board according to the present invention is a multilayer ceramic circuit board in which wiring is arranged in multiple layers in an insulating matrix made of ceramic particles bonded together by glass, in which the matrix in the area surrounding the wiring is made of ceramic particles. The matrix is porous due to the presence of pores between the ceramic particles, and the matrix in other regions is dense due to the fact that the spaces between the ceramic particles are substantially all filled with glass. The method for manufacturing a multilayer ceramic circuit board of the present invention involves forming a wiring layer on the surface of a green sheet whose main components are ceramics and glass, and laminating a plurality of green sheets with and without the wiring layer. In the method of manufacturing a multilayer ceramic circuit board by firing, a green sheet with a small average particle size of ceramic particles is used as a green sheet that forms a wiring layer on the surface and a green sheet that directly contacts the wiring layer in a laminated state, and other green sheets are used. As the green sheet, a green sheet with a large average particle size of ceramic particles is used,
A green sheet laminate in which these green sheets are stacked in a predetermined order is formed by forming a green sheet laminate in which glass is sufficient to substantially fill spaces between ceramic particles having a large average particle size, and glass is filling spaces between ceramic particles having a small average particle size. The structure is configured to fire at a temperature insufficient to cause the material to fill.
本発明は、多層セラミックス回路基板およびその製造方
法に関する。The present invention relates to a multilayer ceramic circuit board and a method for manufacturing the same.
多層セラミックス回路基板は、セラミックス粒子がガラ
スによって結合されて成るマトリクス中に配線が多層に
配置された回路基板であり、特にＬＳＩ素子搭載用に適
している。A multilayer ceramic circuit board is a circuit board in which wiring is arranged in multiple layers in a matrix formed by bonding ceramic particles with glass, and is particularly suitable for mounting LSI elements.
多層セラミックス回路基板の絶縁材料は誘電率が低いこ
とが特に必要である。従来、誘電率の低いガラスやセラ
ミックスを用いた基板が開発されてきたが、情報処理装
置の大型化と高速化に伴い、絶縁部分の誘電率を更に低
くすることが要請されている。It is particularly necessary that the insulating material of the multilayer ceramic circuit board has a low dielectric constant. Conventionally, substrates using glass or ceramics with low dielectric constants have been developed, but as information processing devices become larger and faster, there is a demand for lower dielectric constants of insulating parts.
この要請に対応するためには、ガラスやセラミックスの
誘電率を下げることだけでは不十分であり、基板内部に
空孔を設けることが必要である。In order to meet this demand, it is not enough to lower the dielectric constant of glass or ceramics; it is necessary to provide holes inside the substrate.
しかし、基板内部に空孔を設けると基板の機械的強度が
低下するという問題があった。However, there is a problem in that when holes are provided inside the substrate, the mechanical strength of the substrate is reduced.
本発明は、空孔を設けることにより誘電率を低下させな
がら機械的強度を確保した多層セラミックス回路基板お
よびその製造方法を提供することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a multilayer ceramic circuit board in which mechanical strength is ensured while reducing the dielectric constant by providing holes, and a method for manufacturing the same.
上記の目的を達成するために、本発明の多層セラミック
ス回路基板は、セラミックス粒子がガラスによって結合
されて成る絶縁性マトリクス中に配線が多層に配置され
ている多層セラミックス回路基板において、配線周囲領
域のマトリクスはセラミックス粒子間に空孔が存在する
ことによって多孔質となっており、それ以外の領域のマ
トリクスはセラミックス粒子間が実質的に全てガラスに
より充填されていることによって緻密質となっているこ
とを特徴とする。In order to achieve the above object, the multilayer ceramic circuit board of the present invention has a multilayer ceramic circuit board in which wiring is arranged in multiple layers in an insulating matrix formed by bonding ceramic particles with glass. The matrix is porous due to the presence of pores between the ceramic particles, and the matrix in other areas is dense because the spaces between the ceramic particles are substantially all filled with glass. It is characterized by
また、本発明の多層セラミックス回路基板の製造方法は
、セラミックスおよびガラスを主成分とするグリーンシ
ートの表面に配線層を形成し、該配線層を形成したグリ
ーンシートおよび形成しないグリーンシートを複数枚積
層して焼成することにより多層セラミックス回路基板を
製造する方法において、表面に配線層を形成するグリー
ンシートおよび積層状態で配線層に直接接するグリーン
シートとしてはセラミックス粒子の平均粒径が小さいグ
リーンシートを用い、その他のグリーンシートとしては
セラミックス粒子の平均粒径が大きいグリーンシートを
用い、これらのグリーンシートを所定順序に重ねたグリ
ーンシート積層体を、上記平均粒径の大きいセラミック
ス粒子間をガラスが実質的に充填するのには十分で且つ
上記平均粒径の小さいセラミックス粒子間をガラスが充
填するのには不十分な温度で焼成することを特徴とする
。Further, the method for manufacturing a multilayer ceramic circuit board of the present invention includes forming a wiring layer on the surface of a green sheet whose main components are ceramics and glass, and laminating a plurality of green sheets with and without the wiring layer. In the method of manufacturing a multilayer ceramic circuit board by heating and firing, a green sheet with a small average particle size of ceramic particles is used as the green sheet that forms the wiring layer on the surface and the green sheet that directly contacts the wiring layer in the laminated state. As the other green sheets, we used green sheets with ceramic particles having a large average particle size, and created a green sheet laminate in which these green sheets were stacked in a predetermined order, so that the glass was substantially between the ceramic particles with the large average particle size. The firing is performed at a temperature that is sufficient to fill the ceramic particles with glass, but insufficient to fill the spaces between the ceramic particles having the small average particle size.
本発明の多層セラミックス回路基板は、配線周囲領域の
マトリクスはセラミックス粒子間に空孔を存在させて多
孔質としたことにより誘電率を低下させ、同時に、それ
以外の領域のマドＩＪクスはセラミックス粒子間を実質
的に全てガラスにより充填して緻密質としたことにより
機械的強度を確保する。In the multilayer ceramic circuit board of the present invention, the matrix in the area surrounding the wiring is made porous by the presence of pores between the ceramic particles, thereby reducing the dielectric constant, and at the same time, the matrix in the other area is made of ceramic particles. Mechanical strength is ensured by filling substantially all of the gaps with glass to make it dense.
本発明の多層セラミックス回路基板の製造方法において
は、表面に配線層を形成するグリーンシートおよび積層
状態で配線層に直接接するグリーンシートとしてはセラ
ミックス粒子の平均粒径が小さいグリーンシートを用い
、その他のグリーンシートとしてはセラミックス粒子の
平均粒径が大きいグリーンシートを用いる。これらのグ
リーンシートを所定順序に重ねたグリーンシート積層体
を焼成すると、焼成温度でガラスが流動してセラミック
ス粒子間に入り込む。その際、セラミックス粒子が小さ
いほど、粒子間にガラスが入り込み難くなる。本発明で
はこの現象を利用して、平均粒径の大きいセラミックス
粒子間をガラスが実質的に充填するのには十分であるが
、平均粒径の小さいセラミックス粒子間をガラスが充填
するのには不十分な温度で焼成することにより、小さい
粒子間に空孔を残し、大きい粒子間はガラスで実質的に
充填する。これにより、セラミックス粒子の平均粒径が
小さい配線周囲の領域は多孔質となって実効誘電率が低
下し、セラミックス粒子の平均粒径が大きい上記以外の
領域は緻密質になって機械的強度が確保される。また、
配線周囲の空孔が基板内の亀裂伝播を分散させるため、
破壊強度が高まるという効果も得られる。In the method for manufacturing a multilayer ceramic circuit board of the present invention, green sheets with a small average particle size of ceramic particles are used as the green sheets forming the wiring layer on the surface and the green sheets directly in contact with the wiring layer in the laminated state, and other green sheets are used. As the green sheet, a green sheet having ceramic particles having a large average particle size is used. When a green sheet laminate in which these green sheets are stacked in a predetermined order is fired, the glass flows at the firing temperature and enters between the ceramic particles. At this time, the smaller the ceramic particles, the more difficult it is for glass to enter between the particles. In the present invention, by utilizing this phenomenon, it is sufficient for glass to substantially fill between ceramic particles with a large average particle size, but it is sufficient for glass to fill between ceramic particles with a small average particle size. Firing at an insufficient temperature leaves voids between the smaller particles and substantially fills the spaces between the larger particles with glass. As a result, the area around the wiring where the average particle size of ceramic particles is small becomes porous and the effective dielectric constant decreases, and the area other than the above where the average particle size of ceramic particles is large becomes dense and mechanical strength decreases. Secured. Also,
Since the pores around the wiring disperse crack propagation within the board,
The effect of increasing breaking strength can also be obtained.
以下に、添付図面を参照し、実施例によって本発明を更
に詳細に説明する。In the following, the invention will be explained in more detail by means of examples with reference to the accompanying drawings.
第１図および第２図を参照して、本発明に従って多層セ
ラミックス回路基板を製造した一例を説明する。An example of manufacturing a multilayer ceramic circuit board according to the present invention will be described with reference to FIGS. 1 and 2.
平均粒径１．０μｍと３．０μｍのムライト粉末を、そ
れぞれ別個にガラス粉末（平均粒径的３．０μｍ）、有
機バインダーおよび水とを混練し、２通りのスラリーを
作製した。本実施例ではセラミックスとしてムライトを
用いたが、もちろん従来からセラミックス回路基板用に
用いられているアルミナ等のセラミックスを用いてもよ
い。Mullite powders with average particle diameters of 1.0 μm and 3.0 μm were separately kneaded with glass powder (average particle diameter of 3.0 μm), an organic binder, and water to prepare two types of slurries. Although mullite is used as the ceramic in this embodiment, it is also possible to use ceramics such as alumina, which have been conventionally used for ceramic circuit boards.
これらのスラリーそれぞれから、ドクターブレード法に
より厚さ３００μｍのグリーンシートを成形した。これ
を１００四角に打ち抜き、ノくイアホールを形成した。Green sheets with a thickness of 300 μm were formed from each of these slurries by a doctor blade method. This was punched out into 100 squares to form ear holes.
ムライト平均粒径１．０μｍの打ち抜きグリーンシート
を１５枚、ムライト平均粒径３．０μｍの打ち抜きグリ
ーンシートを６枚、合計２１枚を用意した。A total of 21 sheets were prepared, including 15 punched green sheets with a mullite average particle size of 1.0 μm and 6 punched green sheets with a mullite average particle size of 3.0 μm.
先ず、ムライト平均粒径１．０μｍの打ち抜きグリーン
シート（第１図中の２）を３枚用い、１枚の片面にグラ
ンド層（同３）を印刷して積層製素人とし、他の２枚の
片面には配線（同１）をスクリーン印刷してそれぞれ積
層要素Ｂとした。First, three punched green sheets (2 in Figure 1) with a mullite average particle size of 1.0 μm were used, a ground layer (3 in Figure 1) was printed on one side to make a laminated product, and the other two sheets were A wiring (same as 1) was screen printed on one side of each to form a laminated element B.
また、ムライト平均粒径３，０μｍの打ち抜きグリーン
シート（同４）１枚の片面に上記と同様のグランド層（
同３）を印刷して積層要素Ｃ１とした。In addition, a ground layer similar to the above (
3) was printed to obtain a laminated element C1.
上８己４枚の積層要素を第１図に示した向きおよび順序
（上からＡ−Ｂ−Ｂ−Ｃになる順）で積層したものを１
組とし、これと同じものを上記と同様に合計５組分準備
した。これら５組を第１図と同じ向きにして順次積層し
てから最上部にムライト平均粒径３．０μｍの打ち抜き
グリーンシート（同４）を積層しくすなわち合計２１枚
の積層要素を積層し）、１５０℃、３０ＭＰａで加圧成
形し、グリーンシート積層体を得た。1 is made by laminating 4 laminated elements in the direction and order shown in Figure 1 (A-B-B-C from the top).
A total of 5 sets of the same material were prepared in the same manner as above. These five sets were laminated one after another in the same direction as in Figure 1, and then a punched green sheet (4) with a mullite average grain size of 3.0 μm was laminated on top (that is, a total of 21 laminated elements were laminated). Pressure molding was performed at 150° C. and 30 MPa to obtain a green sheet laminate.
この積層体を窒素中、１０３０℃で焼成し、第２図に示
すように配線１の周囲領域のマトリクスが多孔質領域２
′であり、その他のマ） ＩＪクスは緻密質領域４°と
なっている多層セラミックス回路基板を得た。This laminate is fired at 1030°C in nitrogen, and as shown in FIG.
', and other ma) A multilayer ceramic circuit board was obtained in which IJx had a dense region of 4°.
実施例で作製したムライト平均粒径３．０μｍの打ち抜
きグリーンシート４のみを２１枚準備した。Twenty-one punched green sheets 4 having an average mullite particle diameter of 3.0 μm prepared in the example were prepared.
実施例１と同様にして、但し打ち抜きグリーンシート２
の代わりに打ち抜きグリーンシート４を用いて、積層要
素４枚を積層したものを１組とし、これを５組積層して
から最上部に最後の１枚を積層した。Same as Example 1, except that punched green sheet 2
Instead, a punched green sheet 4 was used, and four laminated elements were laminated to form one set, and five sets of these were laminated, and then the last one was laminated on top.
以下、実施例と同様な手順および条件で加圧成形および
焼成を行い多層セラミックス回路基板とした。得られた
基板は全領域が空孔の無い緻密質であった。Thereafter, pressure molding and firing were performed using the same procedures and conditions as in the examples to obtain a multilayer ceramic circuit board. The obtained substrate was dense with no pores in the entire region.
実施例および従来例で得られた多層セラミックス回路基
板について、誘電率および曲げ強さを測定した結果を第
１表に示す。Table 1 shows the results of measuring the dielectric constant and bending strength of the multilayer ceramic circuit boards obtained in Examples and Conventional Examples.
第１表
第１表の結果から、本発明の多層セラミックス回路基板
は、従来よりも誘電率が低下しており、従来と同等の曲
げ強さを有することが分かる。From the results shown in Table 1, it can be seen that the multilayer ceramic circuit board of the present invention has a dielectric constant lower than that of the conventional circuit board, and has a bending strength equivalent to that of the conventional circuit board.
以上説明したように、本発明の多層セラミックス回路基
板は、配線周囲を多孔質として誘電率を低下させながら
、その他の部分を緻密質として機械的強度を確保したの
で、情報処理装置の高速化を進める上で極めて有用であ
る。As explained above, the multilayer ceramic circuit board of the present invention makes the area around the wiring porous to lower the dielectric constant, while making the other parts dense to ensure mechanical strength, thereby increasing the speed of information processing equipment. This is extremely useful as you move forward.
第１図は、本発明に従ってグリーンシートを積層する配
列状態の一部を示す断面図、および第２図は、第１図の
配列を５回繰り返して積層し、最上部に更にもう１層積
層した積層体を焼成して得られた本発明の多層セラミッ
クス回路基板を示す断面図である。
１・・・配線層、
２・・・セラミックス平均粒径の小さいグリーンシート
、
２° ・・・セラミックス平均粒径の小さい多孔質領域
、
３・・・グランド層、
４・・・セラミックス平均粒径の大きいグリーンシート
、
４° ・・・セラミックス平均粒径の大きい緻密質領域
。FIG. 1 is a cross-sectional view showing a part of the arrangement state in which green sheets are laminated according to the present invention, and FIG. 2 is a cross-sectional view showing a part of the arrangement state in which green sheets are laminated according to the present invention, and FIG. 2 shows the arrangement shown in FIG. FIG. 2 is a cross-sectional view showing a multilayer ceramic circuit board of the present invention obtained by firing the laminate. 1... Wiring layer, 2... Green sheet with small average ceramic particle size, 2°... Porous region with small average ceramic particle size, 3... Ground layer, 4... Average ceramic particle size Large green sheet, 4°...Dense region with large ceramic average grain size.
Claims (2)
絶縁性マトリクス中に配線が多層に配置されている多層
セラミックス回路基板において、配線周囲領域のマトリ
クスはセラミックス粒子間に空孔が存在することによっ
て多孔質となっており、それ以外の領域のマトリクスは
セラミックス粒子間が実質的に全てガラスにより充填さ
れていることによって緻密質となっていることを特徴と
する多層セラミックス回路基板。1. In a multilayer ceramic circuit board in which wiring is arranged in multiple layers in an insulating matrix made of ceramic particles bonded together by glass, the matrix in the area surrounding the wiring becomes porous due to the presence of pores between the ceramic particles. A multilayer ceramic circuit board characterized in that the matrix in other regions is dense because substantially all of the gaps between the ceramic particles are filled with glass.
シートの表面に配線層を形成し、該配線層を形成したグ
リーンシートおよび形成しないグリーンシートを複数枚
積層して焼成することにより多層セラミックス回路基板
を製造する方法において、表面に配線層を形成するグリ
ーンシートおよび積層状態で配線層に直接接するグリー
ンシートとしてはセラミックス粒子の平均粒径が小さい
グリーンシートを用い、その他のグリーンシートとして
はセラミックス粒子の平均粒径が大きいグリーンシート
を用い、これらのグリーンシートを所定順序に重ねたグ
リーンシート積層体を、上記平均粒径の大きいセラミッ
クス粒子間をガラスが実質的に充填するのには十分で且
つ上記平均粒径の小さいセラミックス粒子間をガラスが
充填するのには不十分な温度で焼成することを特徴とす
る多層セラミックス回路基板の製造方法。2. A method of manufacturing a multilayer ceramic circuit board by forming a wiring layer on the surface of a green sheet whose main components are ceramics and glass, and laminating and firing a plurality of green sheets with and without the wiring layer formed thereon. In this method, green sheets with a small average particle size of ceramic particles are used as green sheets that form a wiring layer on the surface and green sheets that are in direct contact with the wiring layer in a laminated state, and green sheets with a small average particle size of ceramic particles are used as other green sheets. A green sheet laminate in which large green sheets are used and these green sheets are stacked in a predetermined order is prepared by using a material having a size that is sufficient for glass to substantially fill the space between the ceramic particles having the above-mentioned large average particle diameter and A method for manufacturing a multilayer ceramic circuit board, characterized by firing at a temperature insufficient for glass to fill between small ceramic particles.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24610990A JPH04125990A (en) | 1990-09-18 | 1990-09-18 | Multilayered ceramic circuit board and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24610990A JPH04125990A (en) | 1990-09-18 | 1990-09-18 | Multilayered ceramic circuit board and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04125990A true JPH04125990A (en) | 1992-04-27 |
Family
ID=17143619
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24610990A Pending JPH04125990A (en) | 1990-09-18 | 1990-09-18 | Multilayered ceramic circuit board and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04125990A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6800360B2 (en) | 2001-02-08 | 2004-10-05 | Sumitomo Electric Industries, Ltd. | Porous ceramics and method of preparing the same as well as microstrip substrate |
| JP2007281115A (en) * | 2006-04-05 | 2007-10-25 | Murata Mfg Co Ltd | Multilayer circuit board and its manufacturing method |
| JP2011114175A (en) * | 2009-11-27 | 2011-06-09 | Kyocera Corp | Method of manufacturing multilayer wiring board, and multilayer wiring board |
| JP2011134843A (en) * | 2009-12-24 | 2011-07-07 | Kyocera Corp | Method of manufacturing wiring board, and wiring board |
| CN103094694A (en) * | 2011-10-31 | 2013-05-08 | 深圳光启高等理工研究院 | Metamaterial dielectric substrate and processing method thereof |
-
1990
- 1990-09-18 JP JP24610990A patent/JPH04125990A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6800360B2 (en) | 2001-02-08 | 2004-10-05 | Sumitomo Electric Industries, Ltd. | Porous ceramics and method of preparing the same as well as microstrip substrate |
| JP2007281115A (en) * | 2006-04-05 | 2007-10-25 | Murata Mfg Co Ltd | Multilayer circuit board and its manufacturing method |
| JP2011114175A (en) * | 2009-11-27 | 2011-06-09 | Kyocera Corp | Method of manufacturing multilayer wiring board, and multilayer wiring board |
| JP2011134843A (en) * | 2009-12-24 | 2011-07-07 | Kyocera Corp | Method of manufacturing wiring board, and wiring board |
| CN103094694A (en) * | 2011-10-31 | 2013-05-08 | 深圳光启高等理工研究院 | Metamaterial dielectric substrate and processing method thereof |
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