JPH03272245A - Bipolar violation detection circuit - Google Patents

Abstract

PURPOSE:To reduce number of FFs and to simplify the circuit by setting a different output signal logic when a mark of a positive unipolar signal is inputted from when a mark of a negative unipolar signal is inputted. CONSTITUTION:An output signal logic set by a latch circuit 1 when a mark of a positive unipolar signal is inputted is inverted from that when a mark of a negative unipolar signal is inputted. A 1st gate circuit 2 latches an output of the latch circuit 1 when both the positive and negative bipolar signals represent non-mark and uses a unipolar signal representing a mark for an input signal to the latch circuit 1 when any of the positive and negative bipolar signals represents a mark. A 2nd gate circuit s compares an output of the latch circuit 1 with the positive and negative bipolar signal input to output a bipolar violation detection signal.

Description

[Detailed Description of the Invention] [Summary] Regarding a bipolar violation detection circuit for detecting bipolar law violations in bipolar codes such as AMI signals, the present invention aims to reduce the number of FFs and simplify the circuit. In a circuit that detects bipolar violations by converting a bipolar signal into positive and negative unipolar signals, there is a difference between when a positive unipolar signal mark is input and when a negative unipolar signal mark is input. A holding circuit that inverts the output signal logic, and when both the positive and negative unipolar signals indicate a non-mark, maintains the output of the holding circuit, and when either the positive or negative unipolar signals indicate a mark, A first gate circuit that controls the unipolar signal indicating the mark as an input signal to the holding circuit, and detects bipolar violation by comparing the output of the holding circuit with the positive and negative unipolar signal inputs. The second gate circuit is configured to include a second gate circuit and a second gate circuit.

[Industrial Application Field] The present invention relates to a bipolar violation detection circuit for detecting bipolar law violations in bipolar codes such as AMI signals.

As shown in FIG. 3(a), the bipolar signal is
Each time 1" occurs, the polarity is reversed and alternately +1
．． -1 is sent. If the data is ``0'', it is at the 0 level. However, if the data "'bi" corresponds to +1.-1 of the bipolar signal, the data "o"
Whether "" corresponds to +11 of the bipolar signal is arbitrary depending on the system design specifications, etc., so hereinafter, the portion corresponding to +1°1 of the bipolar signal will be referred to as a mark.

As is clear from Figure 1, such a bipolar signal has no DC component, making it easy to extract the clock component on the receiving side and making code amount interference less likely to occur. It is widely used as a transmission line code for 15DN and 15DN subscriber lines.

For bipolar signals, data “1” or data “
Code conversion is performed based on a bipolar rule in which the polarity is reversed every time an ``OPA'' occurs, but as shown in FIG. 3, a code that disturbs this bipolar rule may be used. This is called a bipolar violation, and it causes transmission of frame bits and information such as failure notification. Then, on the receiving side, by detecting this bipolar violation,
Detects frame bits, etc.

[Conventional technology]

As shown in FIG. 3(b), bipolar violation converts the bipolar signal into a positive unipolar signal (N
RZ signal, etc.) and a unipolar signal on the negative side, and detection is performed by monitoring the unipolar signal. In other words, the third
As shown in Figure (b), bipolar violation is detected by detecting that marks occur consecutively in unipolar signals of the same polarity. (In FIG. 3(b), bipolar violation is detected in the positive unipolar signal.) As a circuit configuration for detecting the continuous occurrence of marks in the positive or negative unipolar signal, FIG. What is shown in a) is publicly known. FIG. 6(b) is an operation time chart. In the following description, a case where the mark of the bipolar signal indicates data "1" will be explained as an example.

The positive unipolar signal is input to the set terminal of the set/reset FF 51 and the AND gate 53, and the negative unipolar signal is input to the reset terminal of the set/reset FF 51 and the AND gate 54. When the mark of the positive unipolar signal is input to the FF 51, the FF 51 sets its output to logic "'1". Conversely, when the mark of the negative polarity side unipolar signal is input to the FF 51, the FF 51 is reset and its output becomes logic "'0". moreover,
The output of FF51 is input to D-FF52. D-F
F52 operates in synchronization with a clock signal extracted from a bipolar signal.

Therefore, as shown in the fifth (g)) time chart,
The mark of the positive polarity unipolar signal and the mark of the negative polarity unipolar signal are DI, D2. When the signals occur alternately as in D3, the FF 51 inverts the output logic according to the mark input. Also, D3. When marks occur consecutively in unipolar signals of the same polarity as in D4 (bipolar violation in this case), the FF 51 continues to output the same logic.

Since FF52 operates in synchronization with the clock signal extracted from the bipolar signal, the output of FF52 is
This is the output of F51 delayed by one clock. That is, when the output Q of the FF 52 is logic 1, it indicates that the previously input mark is a positive unipolar signal,
When it is logic O, it indicates that it is a negative polarity unipolar signal.

Di, D2. When marks occur alternately in positive and negative unipolar signals as in D3, the mark input this time and the mark input last time are generated in unipolar signals of different polarities. , the output Q of the FF 52 and the positive unipolar signal never become logic 1. Similarly, the output Q of the FF 52 and the negative unipolar signal never become logic 1. Therefore, the output logic of AND gates 53 and 54 is O, and no bipolar violation detection signal is output from OR gate 55.

Next, D3. In an example where marks of the same polarity are continuously generated as in D4 (see FIGS. 5 and 5), marks are continuously generated on the positive polarity side. ) The output Q of the FF 52 and the positive unipolar signal or the output Q of the FF 52 and the negative unipolar signal both become logic 1. Therefore, a logic 1 is output from either AND gate 53 or 54,
A bipolar violation detection signal is output from the OR gate 55. In the example of FIG. 5(b), since a violation is detected on the positive polarity unipolar signal side, the output of the AND gate 53 becomes logic 1.

(Problems to be Solved by the Invention) As shown in FIG. 4(a), in the conventional bipolar violation detection circuit, the set/reset FF 51 detects whether or not marks of the same polarity occur consecutively, and the previous D indicating which polarity the input mark is of
- Required at least two FFs of FF52.

The present invention aims to reduce the number of FFs and simplify the circuit.

[Means for solving problems] The principle configuration diagram of the present invention is shown in FIG. 1(a).

The present invention replaces the part conventionally composed of set/reset FFs with a simple first gate circuit.

In FIG. 1(a), the received bipolar signal is converted into unipolar signals on the positive side and the negative side, and inputted together with the clock signal to the bipolar violation detection circuit 8.

The holding circuit 1 inverts the output signal logic when the mark of the positive unipolar signal is input and when the mark of the negative unipolar signal is input.

The first gate circuit 2 maintains the output of the holding circuit when both the positive and negative unipolar signals indicate a non-mark, and outputs a mark when either the positive or negative unipolar signals indicate a mark. The unipolar signal shown in FIG. 1 is controlled to be input to the holding circuit.

The second gate circuit compares the output of the holding circuit with the positive and negative unipolar signal inputs and outputs a bipolar violation detection signal.

[Effect]

Considering the operation of a conventional set/reset FF, its logical output f is: The presence or absence of this is determined by a combination of the above three logics.

The relationship between these logic combinations and the logic output f is shown in the table below.

In the above table, for X, 1 indicates that there is a mark on positive polarity, 0 indicates that there is a mark on negative polarity, for YZ, 1 indicates that there is a mark, 0 indicates that there is no mark, and r indicates the output logic. . Note that since it is impossible for both positive polarity and negative polarity to have marks, they are indicated by "-°" in the above table.

The above table will be explained.

0 a) This is a case where the previous mark exists in negative polarity (X) and the current input has no mark in both positive and negative polarity. In this case, f is the state of X that is preserved as is.

b) The previous mark exists in positive polarity (X), and the current input has no mark in both positive and negative polarity. In this case, f is the state of X that is preserved as is.

C) The previous mark exists in negative polarity (X), and the current input has a mark in positive polarity. In this case, f is the inverted state of X.

d) The previous mark exists at negative polarity (X), and the current input is a case where there is a mark at negative polarity. In this case, f will preserve the state of X. (Bipolar pie oscillation) e) The previous mark exists at positive polarity (X), and the current input is a case where there is a mark at positive polarity. In this case, f will preserve the state of X. (Bipolar violation) g) The previous mark exists in positive polarity (X), and the current input has a mark in negative polarity. In this case, f is the inverted state of X.

From the above table, f can be expressed as a logical function as follows.

r=x10y+z・・・・・・■ = (x10y) ・Z・・・・・・■ =x−y−z・・・・・・■ Therefore, the conventional set/reset) FF The output logic can be configured by a logic circuit (first gate circuit 2) that satisfies the above logical formula (■■■), and the circuit configuration is simplified.

To explain it more functionally, when both the positive and negative unipolar signals indicate non-mark, the second gate circuit 2 maintains the output of the holding circuit 1 and outputs either the positive or negative unipolar signal. When indicates a mark, a unipolar signal indicating the mark is input to the holding circuit 1, and the logic circuit 12 may be configured to obtain an output from the holding circuit 1 according to the polarity of the mark.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

Figure 1(a) shows two NORs that satisfy the above-mentioned equation 0.
FIG. 3 is a diagram showing an example in which a first gate circuit is configured by a circuit.

The first N0R21 has a positive polarity unipolar signal and a D-F
The Q output of F52 is input. Also, the second (7)
The NOR21 (7) output and the negative unipolar signal are input to the NOR22. N.

The output of R22 becomes the input of D-FF52.

The time chart of the circuit shown in Fig. 1(a) above is shown in Fig. 1(b).
). Regarding bipolar signals, positive polarity unipolar signals, negative polarity unipolar signals, and clock signals, the fifth
This is similar to the time chart shown in FIG. As is clear from this time chart, the output of the second ONOR 22 indicates logic 1 when a positive polarity mark is input;
It can be seen that when a mark of negative polarity is input, it indicates logic 0. Also, if no mark is input, the previous logic is saved. That is, it is similar to the output of the set/reset FF51 in FIG.
can be simplified to two NOR circuits. The other configurations are the same as the conventional circuit configuration shown in FIG. 5(a).

FIG. 2(a) shows a case where the first gate circuit is configured with one OR circuit and one AND circuit that satisfy the above-mentioned equation 0.

The OR circuit 31 has a positive polarity unipolar signal and D-FF5.
2 Q output is input to the AND circuit 32,
The output of the OR circuit 31 and a negative unipolar signal via an inverter are input.

The output of the AND circuit 32 becomes the input of the D-FF 52.

The other configurations are the same as in FIG. 1(a).

An operation time chart of the circuit of FIG. 2(a) is shown in FIG. 2(b). Regarding bipolar signals, positive polarity unipolar signals, negative polarity unipolar signals, and clock signals, the fifth
This is similar to the time chart in Figure (c). As is clear from this time chart, the output of the AND circuit 32 is
It can be seen that when a mark of positive polarity is input, a logic 1 is indicated, and when a mark of negative polarity is input, a logic O is indicated. Also, if no mark is input, the previous logic is saved. That is, the set/reset F of Fig. 5 et al.
It is the same as the output of F51, and the set/reset FF is
It can be simplified to an OR circuit and an AND circuit. The other configurations are the same as the conventional circuit configuration shown in FIG. 5(a).

FIG. 3 shows a case where the second gate circuit is configured with a NAND AND circuit D circuit that satisfies the above-mentioned equation 0.

The NAND circuit 33 receives the Q output of the D-FF 52 and a positive unipolar signal via an inverter. The output of the NAND circuit 33 and a negative unipolar signal via an inverter are input to the AND circuit 34 . The output of the AND circuit 34 becomes the input of the DFF 52. The other configurations are the same as in FIG. 1(a).

This operation time chart in FIG. 3 is the same as that in FIG. 2(b).

〔Effect of the invention〕

As described above, according to the present invention, the number of flip-flops can be reduced and the circuit configuration can be simplified.

[Brief explanation of drawings]

FIG. 1(a) is a diagram showing the principle configuration of the present invention and the circuit configuration of the first embodiment. FIG. 1(b) is a time chart showing the operation of FIG. 1(a). a) shows the circuit configuration of the second embodiment.
Fig. 2) is a time chart showing the operation of Fig. 2(a);

Claims (1)

[Claims] In a circuit that detects bipolar violation by converting a bipolar signal into positive and negative unipolar signals, when a mark for a positive unipolar signal is input and a mark for a negative unipolar signal is input. A holding circuit that inverts the output signal logic when it is input, and when both the positive and negative unipolar signals indicate non-mark, maintains the output of the holding circuit and outputs either the positive or negative unipolar signal. A first gate circuit controls the unipolar signal indicating the mark to be input to the holding circuit when the mark is displayed, and compares the output of the holding circuit with the positive and negative unipolar signal inputs. and a second gate circuit for detecting bipolar violation.