JPH03270431A - Interprocessor communication system - Google Patents

Abstract

PURPOSE:To improve the throughput of communication between processors as an entire multiprocessor system by preventing a data communication bus from being occupied unnecessarily. CONSTITUTION:An end talker number storing and transmitting means 9 stores tentatively a received end announce signal as a talker number, which executes data communication in advance, and sends it to respective IPC (Inter- multiprocessor Communication Devices) (2-1)-(2-n). End announce receiving means 10 in talker parts (2-T)-(2-T-n) of the respective IPC (2-1)-(2-n) receives the talker numbers to be sent by using polling lines and decide the coincidence/ noncoincidence with polling line information held in advance. When the talker numbers are coincident, it is judged to finish the data transmission form the talker part 2-T-1 equipped with the talker number to a processor n1-n, and the end announce receiving means 10 executes the processings to complete the data transmission executed in advance. Thus, the efficiency of using the data communication bus can be improved.

Description

[Detailed Description of the Invention] [Summary] Regarding an inter-processor communication method that improves the usage efficiency of a data communication bus between processors, the present invention relates to an inter-processor communication method that improves the usage efficiency of a data communication bus between processors. The system consists of multiple processors, a data communication bus, a talker section with a data transmission function, and a listener section with a data reception function, and each processor is connected to the data communication bus. Data received by the talker unit of the inter-processor communication device from the transmitting processor during the inter-processor communication by the inter-processor communication device for connecting to the data communication bus, and the inter-processor bus control device that controls the dominance of the data communication bus by polling control. When all of the data has been transmitted to the listener section of the interprocessor communication device on the receiving side via the data communication bus, the final answer sent from the listener section to the talker section indicating the end of reception is detected, and the data is final answer detection data communication bus disconnection means for canceling exclusive use of the communication bus;
When the listener unit of the inter-processor communication device on the receiving side finishes transferring the data received from the talker unit of the inter-processor communication device on the transmitting side to processor n via the data communication bus, the listener unit transfers the data to processor n. a termination notification line specifying means for specifying a transmission line for a termination notification to be sent to and transmitting the specified termination notification line number to the listener section and the talker section; a termination notification means for transmitting the termination notification to the inter-processor bus control device; a termination answer receiving section for receiving the termination notification transmitted by the termination notification means; and upon receiving the termination notification received by the termination notification receiving section, transmitting the termination notification. end talker number storage and transmission means for storing the number (end talker number) of an interprocessor communication device having a talker unit that has previously executed data transmission, and transmitting the end talker number to the talker unit as an end notification; , when the termination notification sent by the termination talker number storage and transmission means is received, and the termination notification line designation number transmitted and held by the termination notification line designation means is compared with the termination talker number, and they match; The apparatus is configured to have a completion notification receiving means for notifying the transmission side processor of the completion of data communication and completing the data communication process.

[Industrial application field]

The present invention relates to an inter-processor communication method in a multiprocessor system such as a digital exchange or a data processing system, and more particularly to an inter-processor communication method that improves the efficiency of using a data communication bus between processors.

[Conventional technology]

When there are multiple processors and communication is to be performed between these processors, there is a method of providing -1 communication buses and temporarily dedicating these communication buses between the sending processor and the receiving processor for data communication. be.

FIG. 9 is a system configuration diagram of such an inter-processor communication system. Now, suppose that data is to be transmitted from processor 0 (90-0) to processor 1 (90-1). The sending side is called a talker, and the receiving side is called a listener.

Each processor 90 has an interprocessor communication device IPC (In
ter-Mult iprocessorCommun
cation Device) 91, each IP
C91 is connected to a data communication bus 94. Also,
Each IPC 91 includes a talker section 92 and a listener section 93.

The talker unit 92-0 of the IPC 91-0 receives and receives data from the processor 90-0 on the sending side, and the talker unit 92-O sends the data to the data communication bus 94, and sends this data to the listener of the IPC 91-1 on the receiving side. The receiver section 93-1 receives the data and sends the received data to the processor 90-1. This completes data transmission from processor 90-0 to processor 90-1.

In addition, in order to execute inter-processor communication, an inter-processor bus control device IBC (Inter-Multiprocessor) that controls control of the data communication bus 94, etc.
ssor Bus Controller) 95 and various signal lines.

The IBC 95 scans each IPC 91 by polling, receives a request for exclusive use of the data communication bus 94 from the IPC 91, and grants exclusive rights if possible.

The signal lines include a data order content transmission line 96 that is attached to the data communication bus 94 and that transmits an order indicating the meaning of transmitted and received data, a polling number transmission line 97 that transmits a polling number, and a polling number transmission line 97 that transmits a polling number. A polling number synchronization signal transmission line 98 that sends a synchronization signal for transmission, a communication bus usage right request transmission line 99 that transmits a usage right request for the data communication bus 94, and a communication bus usage permission signal in response to the usage right request. There is a communication bus use permission transmission line 100 that transmits the data.

The interprocessor bus control device IBC95 performs polling and
It consists of a number generation section 101 and a communication bus use permission section 102. The polling number generation unit sequentially generates a number for each IPC in order to scan each interprocessor communication device IPC 91 by polling. Furthermore, in response to a request for permission to use the communication bus sent from the talker section 92 of the IPC 91, the communication bus use permission section 102 returns a signal indicating permission to use the bus if it is available.

On the other hand, the talker unit 92 in the IPC 91 communicates with the communication bus use request transmitting unit 103 via the data communication bus 94.
-IPC-IP that controls data communication between IPCs
The 0 communication bus use request transmitting unit 103 having the C-to-C data communication control unit 104 receives the polling number sent by the IBC 95 via the polling number transmission line 97, and transmits its own number (the number for each IPC 91). When matching is achieved, a communication request signal is sent to the IBC 95 via the communication bus use request transmission line 99.

The IPC-IPC data communication control unit 104
After receiving permission to use the data communication bus 94 from processor O (90-0), the processor O (90-0) reads data to be transmitted.
The data is sent to the data communication bus 94. At this time, the order contents indicating the meaning of the data to be transmitted are sent to the data order contents transmission line 96.

The listener section 93 in the IPC 91 has an IPC-IPC data communication control section 105 that receives data and transmits the received data to the processor 1 (90-1).

Next, the operation of this system will be explained.

First, the interprocessor bus control device IBC95 sequentially polls and
A number is generated, the generated polling number is sent to a polling number transmission line 97, and a synchronization signal for polling number transmission is sent to a polling number synchronization signal transmission line 98.
Output to. The talker unit 92 of each PC 91 receives and receives the polling numbers sent in sequence, and the communication bus use request transmitting unit 103 determines whether the polling number is the number of its own IPC, If it is your own PC number and there is a data transmission request, the number is IB.
Sends a communication bus use request to C95.

Assume that there is a data transmission request to the IPCO (91-0) and a communication request 106 is manually input to the communication bus use request transmitter 103. Every time a polling number is sent from the polling number transmission wA 97, the communication bus use request sending unit 103 compares the received polling number with its own number. If they do not match, wait for the next polling number to be input; if they match, then it is determined whether or not the communication request signal 106 is input to the communication bus use request transmitter 103. . If the communication bus use request signal 106 has not been input, the communication bus use request sending process is ended and the next polling number is manually input. On the other hand, if the communication request signal 106 has been input, the data communication bus 94 In order to obtain usage permission, a communication bus use request signal is output to the communication bus use request transmission line 99.

The communication bus use permission section 102 of the IBC 95 receives the communication bus use request signal outputted to the communication bus use request transmission line 99 . If the data communication bus 94 is free at that time,
The communication bus use permission unit 102 sends a use permission signal to the communication bus use permission transmission line 100.

The talker unit 92-O of the IPCO (91-0) receives this communication bus use permission signal. Upon receiving this permission signal, the IPC-IPC data communication control unit 104 first selects the destination (
listener).

The IPC number of the listener is output to the data communication bus 94. IPC91 (currently IPC9) corresponding to the IPC number
1-1 as a listener) sends a signal indicating that reception is possible to the talker IPC 91-0 via the data communication bus 94. Upon receiving this signal, IPC9
1-0 sends data to IPC 9 via data communication bus 94.
Send to 1-1. At this time, the data to be transmitted is stored in the buffer memory in the IPC-IPC data communication control section 104 in advance from the processor 0 (90-0).

The data sent to the IPC91-1 is sent to the listener section 93.
-1's IPC-IPC data communication control unit 105 takes the call. The receiver sends the received data to processor 1 (90
-1), data communication is completed. Data communication bus 94 used between talker listeners after data communication is completed
to open.

FIG. 10 shows the operational flow of this system.

The horizontal axis shows the position of each device in the system, and the vertical axis is a time axis that progresses downward.

On the left side there is a transmitting side, ie, a talker 110 device, on the right side there is a receiving side, ie, a listener 112 device, and there is a communication bus 111 between them.

There is an IPCO (91-0) in the part of the talker 110 closest to the communication bus 111, and a processor O (91-0) is located in the part of the talker 110 that is closest to the communication bus 111.
0-0) are connected, and the main storage device 113-0 is further connected. Similarly, on the listener 112 side, IPCI
(91-1), a processor 1 (90-1), and a main storage device 113■. The communication bus 111 section has rBc.
95 is located.

The operation of transmitting data stored in the main storage device 113-0 of the example talker 110 to the listener 112 via the communication bus will be described.

First, the processor O (90-0) on the talker 110 side performs DMA (direct) communication with the summer PCO (91-0).
A DMAC (DMA control) data setting signal S1, which is data for memory access) transfer control, is sent. This signal includes, for example, the memory address where the data is stored, the destination memory address,
These include the amount of data, commands (write commands, etc.), etc. The processor 0 (90-0) further sends a listener number setting signal S2 and a transmission order signal S3, which is a transmission command, to the IPCO in order to set the number of the listener 112, which is the transmission destination, in the IPCO (91-0). Send to (91-0). I
PCO (91-0) is activated upon receiving transmission order signal S3.

Next, processor 0 (90-0) transfers the transmission data from main memory 113-0 to the buffer of IPCO (91-0).
DMA transfer to memory.

On the other hand, on the listener 112 side, processor 1 (90-1)
sends the DMAC data setting signal S5 to IPCI (91-IN,:) when it becomes receivable.The DMAC data setting signal S5 is sent to the memory address of the main storage device 1131 where the data is stored, as in 31 above. , commands, etc. Next, processor 1 (90-1) uses IPCI
(91-1), sends the reception order signal S6, and sends the IPCI
(91-1) is started. Processing related to activation of these listener IPCs is performed at the time when the listener-side device becomes capable of receiving data.

On the talker 110 side, the talker 110 waits until the same polling number as its own number is sent to the IPCO (91-0) on the polling line by the polling scan of the IBC 95. When the same polling number as its own number arrives, IPCO (91-O) issues a communication bus use request S7 to IBC95. Upon receiving S7, the IBC 95 issues a use permission signal S8 if the communication bus is in a usable state.
is returned to IPCO (91-0). Once this usage permission is granted, exclusive use of the communication bus 111 by the talker 110 begins.

The IPCO (91-0) then outputs the listener designation number S9, which has already been set in the IPCO, to the data communication bus 111. All IPC91s that are ready to receive are 39
and determines whether the designated number matches its own number. If they do not match, no processing is performed; on the other hand, if they match, a reception ready 0KSIO signal indicating that reception is possible is sent to the Ill via the data communication bus Ill.
Send to PCO (91-1). In this case, it is assumed that the listener 112 with the number designated as the listener is in a receiving state, and is not in a receiving state and the processor 9O-IP
If 35 and S6 data are not being transmitted between C91, reception preparation is OK even if S9 listener designation signal is sent.
Signal SIO does not return. When the SIO is not returned, the listener side considers that reception is not possible and stops data transmission.

When the reception preparation OK signal SlO is returned from IPCI (91-1) to IPCO (91-0), IP
The CO reads the transmission data from the buffer memory and sends it to the JPCI in burst mode via the communication bus 111 (Sll), and the sent data is stored in the buffer memory in the IPCI.

When all data transmission from IPCO to IPCI is completed, the data stored in the buffer memory in IPCI is transferred to the main memory 113 of processor 1 (90-1).
DMA transfer to -1 (S12).

The receiving side IPCI (91-1) is the main storage device 113-
When data transfer to IPCO (91-0) is completed, an end answer signal S13 indicating that all data transfer has been completed is sent to IPCO (91-0) using communication bus 111. I.P.C.
Upon receiving S13, O confirms the end of data communication and releases the exclusive use of the communication bus 111. and I PC
O sends a notification S14 of data communication completion to processor 0, and I
The PCI sends a completion notification S15 to the processor 1, and all data communication processing ends.

According to this method, the talker monopolizes the data communication bus 94 after the talker IPC 91-0 receives the communication bus use permission signal S8 transmitted by the IBC 95, and then the data communication bus 94 is transferred from the listener IPC to the main storage device 113-1. The talker IPC (91
-0) is received during the period T1.

[Problem to be solved by the invention]

However, the conventional method has the problem of monopolizing the data communication bus for an unnecessarily long time, reducing the throughput of interprocessor communication for the multiprocessor system as a whole. That is, the data communication bus 94 is actually used after the IPCO (91-0) receives the communication bus use permission S8 from the IBC 95.
This is the period (T2) until data transfer between IPCI (91-1) and IPCI (91-1) is completed.
) to the main storage device 113-1 after the data transfer period (
The communication bus is not used during the unused period T3). During the communication bus unused period T3, there is no need for the talker and listener to exclusively use the communication bus.

SUMMARY OF THE INVENTION An object of the present invention is to improve the throughput of inter-processor communication in a multiprocessor system as a whole by preventing unnecessarily exclusive use of a data communication bus in inter-processor communication.

[Means to solve the problem]

FIG. 1 is a block diagram of the present invention. The present invention provides a plurality of processors (l-1, I-2, . . . 1-n) and -
an inter-processor communication device IPC (2-1, 2-2, . . . 2-n) that connects each processor 1 to the data communication bus 3 and executes inter-processor communication;
Interprocessor bus control device IBc4 that controls the data communication bus 3 by scanning for dominance by polling.
Assuming that. In addition, each IPC (2-1, 2-2,...
, 2-n) is a talker unit (
2-T-1, 2-T-2, . . . , 2-T-n), and a listener unit (2-L-1, 2-T-n) that executes data reception processing.
-L-2,...2-L-n). Further, it is assumed that data from processor 1 (l-1) is transmitted to processor n (1-n).

First, the talker section (2-T-1, 2-T-2, . . . 2-T-n) of each IPC (2-1, 2-2, . . . 2n) is a final answer detection data communication bus disconnection means. 5. The means 5 communicates with the sending side IPC (2-
After the data communication from 1) to the receiving PC (2-n) is completed, the receiving IPC (2-n) detects the answer signal sent to the transmitting PC (2-1), and after detection, it is used. The exclusive use of the data communication bus 3 that has been completed is released. An answer signal from IPC (2-n) to IPC (2-1) is transmitted every time one unit of data is received.

The means 5 extracts the last answer signal from among the answer signals, determines that the transfer of transmission data via the data communication bus 3 is completed, and releases the data communication bus 3.

The released data communication bus 3 becomes available for new inter-processor communication.

As soon as the data communication between IPC (2-1) and IPC (2-n) is completed, exclusive use of data communication bus 3 is released, so data transfer from IPC (2-n) to processor n is completed normally. A means for notification of completion is required to notify the talker side whether or not the process has been executed. In the present invention, the polling line normally used for controlling the data communication bus 3 is used to notify the termination.

First, the IBC4 specifies how to use the multiple polling lines for notification of completion, and the receiving side IPC
2-n and the sending side IPC 2-1.

The information on the polling line specified by the means 6 is received by the termination notification means 7 included in the listener section 2-L-n of the IPC 2-n on the receiving side. The means 7 stores information on the polling line to be used, and after the data transfer between the IPC (2-n) and the processor n is completed, sends a completion notification to the I BO 2 using the polling line. .

The termination notification sent by the termination notification means 7 is received by the termination answer receiving means 8 included in the IBC 4. The termination answer receiving means 8 transmits the received information to the termination talker that the IBC 4 has.
The receipt is passed to the number storage and transmission means 9.

The end talker number storing and transmitting means 9 stores the end notification information from the end answer receiving means 8 as the number of the transmitting side, that is, the talker (talker number), and uses the polling line to send the end notification information from the end answer receiving means 8 to each IPC (2 -1, 2-2,..., 2
-n).

Termination notification receiving means included in the talker section ((2-T-1, 2-T-2, . . . , 2-T-n) of each IPC (2-1, 2-2, . . . , 2-n) 10 receives and holds the information of the polling line specified by the end notification line designation means 6. Then, it receives the end talker number transmitted from the end talker number storage and transmission means 9, and Compare with the previously held polling line information. If they match, it is determined that the data sent by the talker unit (2-T-1) was correctly sent to the receiving processor (1-n). death,
A process is executed to complete the data communication process of the talker unit. If they do not match, no processing is performed.

[For production]

Processor 1 (1-1) to processor n (1-n)
When transmitting data to the processor 1, first, the interprocessor bus controller (IBC) 4 scans each interprocessor communication device (IPC) 2 by polling, and
1-1) notifies IBO2 that there is a communication request. In response to this communication request, the IBO 2 grants permission to use the data communication bus 3 to the talker unit (2-T-1) of the IPCI (2-1).

The talker section (2-T-1> specifies the receiving side IPCn (2-n) using the data communication bus 3 for which use is permitted. The listener section (2-L- n
) returns a signal indicating completion of reception preparation to the talker unit (2-T-1> and IBO2 of IPCI (2-1) via the data communication bus 3. -T-1) receives this, sends the transmission data to the data communication bus 3, and sends it to IPCn (2-n).

The IBC 4 receives a reception preparation completion signal from the listener unit (2-L-n), and when the listener unit (2-L-n) completes all data reception processing (i.e., the processor of the received data The listener section (2-L-n)
and notifies the talker section (2-T-1). This process is executed by the end notification line specifying means 6 in the IBC 4. A polling line is used to send the termination notification signal, and the termination notification line designating means 6 determines which polling line the signal should be sent to.
Specify whether to set it to ``'' or ``0.'' The specified information is transmitted to the end notification means 7 in the listener section (2-L-n) of the listener IPC (2-n) and the talker of the talker IPC (2-1). It is sent to the completion notification receiving means 10 in the section (2-T-1), and is held by the completion notification means 7 and the completion notification receiving means 10.

As mentioned above, from the talker section (2-T-1> to the listener section (2-T-1)
In data transmission via the data communication bus 3 to the listener section (2-L-n), each time one unit of data is sent, the listener section (2-L-n
) returns to the talker section (2-T-1), indicating whether the data has been received normally.

The final answer detection data communication bus disconnection means 5 in the talker section (2-T-1) first receives this answer signal and disconnects the final answer data from the listener section (2-L-n).
Detects the answer signal sent from. When the final answer signal is detected, the data communication bus 3, which has been exclusively used between the transmitting side IPCI (2-1) and the receiving side IPCn (2-n), is released. Specifically, data communication bus 3
A signal to release the IBC 4 is sent to the IBC 4. In response to this, the IBC 4 starts scanning each IPC by polling and searches for an IPC that has a communication request. As a result, when data transmission between IPCI C2-1)-1FCn (2-n) is completed, it becomes possible to move on to the next different communication request process.

At this point, the transmitted data is stored in the buffer memory in the listener section (2-L-n) of the IPC (2-n) on the receiving side. The listener unit (2-L-n) then executes a process of transmitting this data to processor n (1-n).

The completion notification means 7 in the listener section (2-L-n) sends a completion notification to the IBC 4 when data transmission to the processor n (2-n) is completed. This termination notification is polling line information previously held in the termination notification means 7, and is sent using the polling line.

This termination notification is received by the termination answer receiving means 8 in the IBCd and passed to the termination talker number storage and transmission means 9 in the IBCJ.

The end talker number storage/transmission means 9 stores the received end notification signal as the number (
2-1, 2-2, . . . , 2-n) using a polling line.
send to Talker section of each IPC (2-T-1, 2-T-2
,...2-T-n) receives the talker number sent using the polling line, and determines whether it matches/mismatches the previously held polling line information. Determine. If they match, the talker unit (2-T-1) having the talker number sends the processor n(
1-n) is determined to have been completed. Finally, the completion notification receiving means 10 executes the completion process of the data transmission previously performed.

〔Example〕

Hereinafter, embodiments will be described with reference to FIGS. 2 to 8.

FIG. 2 shows the countries in which the system is configured according to an embodiment of the present invention.

This embodiment concerns interprocessor communication in a multiprocessor system using a digital exchange as an example.

First, the management processor MPR (management processor) manages the entire digital switching system.
t processor).

and a call processing processor CPR (c
all processors) 22 (22-
1, 22-2,... 22-n). By installing multiple CPRs 22, the load is distributed. MPR 21 and multiple CPRs 22 are all connected to data communication bus 3. This data communication bus 3
between MPR21-CPR22, different CPR2
Performs data communication between the two. In addition, there is an interprocessor bus control device IBC4 that controls which processor controls the data communication bus 3 by polling.

The internal configurations of MPR21 and CPR22 are similar.

Processor bus Pbus2, which is a bus within the processor
5 exists, and it has a central control unit CC (central
controller) 23 and main memory MM (
main memory) 24, inter-processor communication device IPC (inter-multiprocess
ssor communicaLion devi
ce) 2 are connected. Each IPC 2 is also connected to a data communication bus 3, and executes data communication processing for each processor.

The operation of this system will be explained using an example in which data is transmitted from the CPRO (22-0) to the CPRI (22-1). The data to be transmitted is initially transmitted by CPRO (22-0
) The central control unit CC23-0 of the CPRO stored in the main memory MM24-0 in ) sends a data transmission request to the interprocessor communication unit IPCI (2-1),
In response to this, IPCI (2-1) sends a request for permission to use the data communication bus 3 to the interprocessor bus control device IBC4. IBC4 received this usage permission request,
If the data communication bus 3 is free at that time, permission to use it is given to IPCI (2-1).

IPCO (2-1) is the destination CPR from CC23-0.
Take the number I (22-1) and connect to data communication bus 3.
Specify the recipient via .

IPC2 (2-2) in CPRI (22-1) receives and accepts this designated signal, and if CPRI (22-1) is ready for reception, transmits the reception ready signal to IPCI (2-2).
Return to 1).

IPCI (2-1) receives this reception ready signal and starts actual data transmission. First, the main memory 24
-0 to IPC transmission data via Pbus25-0
The data is stored in a buffer memory within I, and the stored data is sent to the data communication bus 3. IPC2 (2-2) in CPRI (22-1) receives and receives this communication data, and
While accumulating data in the buffer memory within the PC 2, it returns an answer signal to IPCI (2-1) each time it receives one unit of data, indicating whether or not it has been received normally.

IPCI (2-1) sends the last data and IPC
2 (2-2) receives the data and returns an answer signal, and when IPCI (2-1) receives it, the data communication ends and IPCI (2-1) transfers data communication bus 3.
Withdraw permission to use. When permission to use the data communication bus 3 is withdrawn, the IBC 4 starts scanning each IPC 2 by polling in order to receive the next communication request.

The IPC2 (2-2) that received the data then transfers the received data accumulated in the internal buffer memory to the Pbus25.
-1 to the main storage device 24-1. In reality, when this transfer process ends normally, CPRO
Data communication from CPR1 to CPR1 is completed. IPC2(2
-2) sends a completion notification to the IBC 4 when the data transfer to the main memory bag 224-1 is completed. The IBC 4 then passes this completion notification to the source IPCI (2-1).

In response to this, IPCI (2-1) acknowledges the completion of data communication via W1, executes communication completion processing, and prepares for the next data communication.

Figure 3 shows each IPC in the countries that make up the system in Figure 2.
2 is an explanatory diagram of the internal configurations of IBC 2 and IBC 4, and the configurations of communication lines such as a data communication bus 3 and polling lines.

The IBC 4 includes a polling number generation circuit 32 that generates polling numbers and a talker section 30 of the IPCO.
Communication bus use permission circuit 33 that grants the right to use the communication bus to
, a termination notification line designation circuit 34 that specifies a communication line for transmitting the termination notification from the IPCI listener unit 31, and an termination talker number that stores the termination notification transmitted from the IPCI listener unit 31 as the number of the talker whose communication has terminated. Memory circuit 3
5. A termination answer receiving circuit 36 that receives the termination notification sent from the IPCI listener section 31, a polling number sending gate circuit 37 that outputs the polling number to the communication line, and a line that receives the termination talker number. End talker number sending gate circuit 38 for output, IP
It consists of a termination answer reception gate circuit 39 for receiving termination notifications transmitted from the listener section 31 of the CI.

Among these, the new circuits of the present invention include an end notification line designation circuit 34, an end talker number storage circuit 35, an end answer receiving circuit 36, and three gate circuits 37, 38, and 3.
It is 9.

On the other hand, each IPC includes a talker section 30 and a listener section 31. In this figure, due to space constraints, IPCO is used for transmission, and IPCl is used for reception, with only the talker unit 30 shown for IPCO and only the listener unit 31 for IPCI shown. I PCO has processor O (1-0)
However, processor 1 (1-1) is connected to IPCI.

The talker unit 30 includes a data transmission circuit 40 that sends data to the data communication bus 3, and a data answerer that decodes an answer signal sent from the listener unit 31, which is the data transmission destination, every time one unit of data is received. a decoding circuit 41; a final answer detection circuit 42 for detecting the final answer from among the answers decoded by the data/answer decoding circuit 41;
The communication bus use request circuit 43 receives and receives the polling number from the BC4, determines whether it matches/disagrees with its own number, and sends a bus use request to the IBC4 if they match, and the listener section 31 to the IBC4 receives the polling number. The termination talker number sent via the BC4 is received, and the termination notification line information specified by the termination notification line designation circuit 34 of the IBC4 is matched/
It is determined whether there is a mismatch, and if there is a match, processor 0 (1
It consists of a completion notification receiving circuit 44 that generates a completion interrupt at -0).

Among these, the new circuits of the present invention are the final answer detection circuit 42 and the completion notification receiving circuit 44.

On the other hand, the listener section 31 receives and receives an order content signal indicating the content of data sent from the data receiving circuit 45 that receives data and the talker section 30 via the data communication bus 3, and a data order signal that decodes the order content signal. Content decoding circuit 46: When the order content decoding circuit 46 decodes the data content as a listener designation, it determines whether the data matches/mismatches its own number, and if they match, it identifies itself as a listener. When the data is decoded as the final data by the listener designation circuit 48 and the order content decoding circuit 46, a data transfer request is issued to the processor 1 (1-1), and the order content decoding circuit 46 issues a data transfer request to the processor 1 (1-1). IP that controls communication
C-processor communication control circuit 47, a completion notification circuit that receives a notification of completion of data transmission to the processor 1 from the IPC-processor 1 volume communication control circuit 47 and sends a completion answer to the communication line determined by the IBC designation. Consists of 49. Among these, the new circuit of the present invention is the termination notification circuit 49.

Next, types of communication lines will be explained. First, in order to transmit data from the talker section 30 to the listener section 31, there is a data communication bus 3 (Ll) connected to each IPC. For example, it can be configured with an 8-bit wide bus. In addition to the data communication bus L1, there is a data order content notification line L2 connected to each IPC in order to notify the listener unit 31 from the talker unit 30 of the order content of data on the data communication bus L1.

The communication lines used for controlling the data communication bus L1 include a polling number line L3 that sends a polling number from the IBC 4 to each IPC, and a polling number line L3 that sends an end talker number from the IBC 4 onto the polling number line L3. , or to send a signal 330 for selecting whether to send a polling number or whether the IBC 4 should receive an end answer from the listener section 31.
Polling number line use mode control line L4 connects IBC4 and each IPC to send a pulse synchronized with the polling number output by IBC4 and each IPC.
Polling number synchronization line L5, I BC4 connecting
An ending talker connects the IBC4 and each IPC in order to send out a pulse synchronized with the final talker number output by the IBC4.
In order for the number synchronization, IaL6, and the talker unit 30 of each IPC to send a request signal for the right to use the data communication bus 3 to the IBC4, a communication bus use request line L7, which connects each IPC and IBC4, is sent from the IBC4 to the talker unit 30. Communication bus use permission line L8.1 connects the BC4 and each IPC to send permission to use the communication bus. End connects the IBC4 and each IPC to specify a notification line for notifying the end answer to the listener unit 31 from the Bc4. The notification line designation line L9 and each IPC and IB are used to notify the IBC 4 that the listener unit 31 that has received the listener designation from the talker unit 30 has been designated as a listener.
There is a listener designated reception line LIO that connects C4.

Next, the operation of this system will be explained along the operation flow shown in FIG.

Assume that there is a data transmission request from processor O (1-0) to processor 1 (11).

First, the I PC to which processor O(1-0) is connected
The transmission data is sent to the talker unit 30 of O.
The data settings (DMAC data settings 541) for DMA transfer are sent to the buffer memory in the DMA transfer unit. Data settings include data amount, read memory address, data type, etc.

Further, the processor O (1-0) transmits a listener number designation S42 to the IPCO in order to notify the IPCO of the transmission destination, that is, the number of the listener.

Thereafter, the processor O(1-0) transmits a transmission order S43 to the IPCO, and starts the talker section 30 of the rpco. Next, the main storage device 24- attached to processor 0
The transmission data is extracted from 0 and transferred by DMA to the buffer memory of the talker section 30 (344).

The IBC4 generates a polling number signal (345) in the polling number generation circuit 32, and generates a polling number signal (345).
It is sent to number line L3. At this time, at the same time, a polling number line use mode S30 and a polling number synchronization signal S31 are sent to the polling number line use mode control line L4 and polling number synchronization line L5, respectively. In this case, the mode of S31 is a polling number sending mode.

The communication bus use request circuit 43 in the talker unit 30 of each TPC receives the polling number signal (S45) sent to the polling number line L3, and checks whether the number matches its own number or not. If they match, a data communication bus use request signal, that is, a polling prohibition request S46 that prohibits subsequent polling, is sent.
It is output to the communication bus use request line L7.

The IBC 4 receives this polling prohibition request S46, and if the data communication bus L1 is free, transfers the use permission S47 of the data communication bus L1 to the communication bus use permission line L8.
It is transmitted to the talker section 30 via.

The data transmission circuit 40 of the talker unit 30 receives the use permission signal S47 of the data communication bus L1, and transmits the data communication bus L1.
Use to specify the listener. At this time, the signal S32 output from the data transmission circuit 40 to the data communication bus L1 is the listener number data 348, and the data
The signal S33 output to the order content notification line L2 is S32
This data indicates that the data is listener specified data.

A data order content decoding circuit 46 in the listener section 31 of each PC decodes the data content of 333. Since the listener is designated, the listener designation circuit 48 is activated.

The listener designation circuit 48 receives the listener designation number from S32 and determines whether it matches/mismatches its own number. If the listener designation circuit 48 that has determined that there is a match is ready to receive data, it sends out two reception preparation OK double signals S49.550) via the data reception circuit 45.

The reception preparation OK double signal 49 is sent to the output signal line S34 from the data reception circuit 45, and is passed to the data/answer decoding circuit 41 of the talker section 30 via the data communication bus L1. determines that data transmission to the listener unit 31 is possible. On the other hand, preparation for reception O
The K times signal 50 is sent from the data receiving circuit 45 to the listener designated receiving line LIO, and is passed to the end notification line designating circuit 34 of the TBC 4.

The talker unit 30 that received the reception preparation OK double signal 49,
The transmission data S52 accumulated in the buffer memory in the talker section 30 is sent to the data communication bus L1 via the output line S32 of the data transmission circuit 40. At this time, the data order content notification line L2 has the following information via the output line S33:
A signal indicating that the content of the data is transmission data is sent out.

The data order content decoding circuit 46 of the listener section 31
2 is decoded and in this case, it is found that it is transmission data, so the transmission data S5 is transmitted from the data communication bus L1.
2 is received by the data receiving circuit 45 and stored in the buffer memory within the listener section 31.

Every time data reception circuit 45 receives one unit of transmission data, it outputs answer signal S53 from output line S34 to data communication bus L1. This answer signal S53 is received by the data/answer decoding circuit 41 of the talker section 30, and if it is received normally, data transmission continues.

On the other hand, the reception rate IOK signal S50 to IBC4 is IBO
The completion notification line designation circuit 34 in 2 receives the notification.

Then, when the data communication to the processor 1 (1-1) is completely completed, the polling number line L3 consisting of a plurality of lines is used to specify the communication line to which the listener unit 31 sends out the completion notification signal. specify how to use it),
The designation result is sent to the end notification line designation line L9 as the end notification line designation signal S51. The end notification line designation signal S51 is
The termination notification circuit 49 of the listener section 31 and the termination notification receiving circuit 44 of the talker section 30 receive the message and hold it therein.

The last transmission signal is sent from the data transmission circuit 40 of the talker section 30 to the data communication bus Ll, and the data reception circuit 41 of the listener section 31 receives this and also sends an answer signal S5.
3 to the data communication bus L1. The data/answer decoding circuit 41 of the talker section 30 receives this answer signal 353 and passes it to the final answer detection circuit 42. When the final answer detection circuit 42 detects that this answer signal S53 is the final answer signal, it cancels the communication bus use request signal S46 via the communication bus use request circuit 43. The communication bus use permission circuit 33 in the IBCJ detects a change in the signal on the communication bus use request line L7, and resumes polling that was prohibited by the polling prohibition request S46. This allows the data communication bus Ll to be used for data communication between other processors.

On the other hand, the listener section 31 sends the final answer signal to the talker section 30.
After transmitting the data to processor 1 (1-1), the data is transferred to processor 1 (1-1). That is, the IPC-processor communication control circuit 47 in the listener section 31 transfers the received data stored in the buffer memory to the processor 1 by DMA (S54).

All received data is stored in the main memory 24 of the processor 1.
1, the completion notification circuit 49 in the listener section 31 sends a completion notification to the polling number line L3 based on the completion notification line data held in the completion notification circuit 49. (S55), the end notification circuit 49
After sending 5, it sends a completion notification interrupt signal 35B indicating that all data communication has been completed to processor 1 (1-1) connected to IPCI (2-1).

The end answer signal S55 is the end answer reception diagram in IBC4! 36 receives the completed answer via the reception gate circuit 39. That is, by this gate circuit 39, when the polling number line use mode control line L4 is at a low level,
The end answer signal S55 is input to the end answer receiving circuit 36.

The end talker number storage circuit 35 in the I BCJ stores the end answer signal received by the end answer receiving circuit 36 as an end talker number. And end talker
The number storage circuit 35 receives the end talker number synchronization signal 3.
56 and the end talker number S57.
The number is sent out via the number sending gate circuit 38. S57 is sent to polling number line L3, and 356 is sent to end talker number synchronization, IL6.

The end talker number signal 357 sent to the polling number line L3 is received by the end notification receiving circuit 44 in the talker section 30 of each IPC.

The termination receiving circuit 44 determines whether the number in S57 and the termination notification line information previously stored within the receiver match or do not match, and if they match, it determines that the executed data communication has been completely completed. A completion notification interrupt signal S59 is sent to processor O (1-1) which has recognized and connected to IPCO (2-0).
Send. This allows processor 0 (1-0)
- Data communication between processor 1 (1-1) is completed.

FIG. 5 is an explanatory diagram of the main new circuits among the circuits of the interface control section 50 in the IBC 4 and IPC.

First, there is an interface control section 50 between the IBC 4 and each IPC (IPCi). There is a polling number line L3 between them. The polling number line L3 consists of four communication lines PNO-3.

Polling number generation circuit in IBC4 (Fig. 32
) has a 4-bit polling counter 51 that stores the generated polling number. Polling counter 51 is connected to polling number line PNO-3 via polling number output gate 37. One input signal of the polling number output gate 37 is the output value of the polling counter 51, the other input S60 is the output of the AND element 52, and the two input signals of the AND element 52 are the polling number This is a negative logic input of the line use mode control signal SEL (communication line L4) and the communication bus use permission signal TOK (communication line L8).

That is, the polling number read from the polling counter 51 is sent from the polling number output gate 37 to the polling number line PN when 5EL=1 and TOK=0 (permission to use the communication bus is not granted).
Output to O~3.

On the other hand, the termination notification line designation circuit 34 in the IBCJ includes a termination notification line management circuit 53 that manages information on the polling number line used by the listener section 31 for termination notification, a termination notification line designation encoder 54, and a termination answer line designation output. gate 55
, AND element 56. The information of the polling number line used for the termination notification stored in the termination notification line management circuit 53 is read into the termination notification line designation encoder 54.

The output of the encoder 54 becomes one input of the output answer line designation output gate 55, and the other input is connected to the output S61 of the AND element 56.

The output of gate 55 is connected to polling number line PNO-3. The inputs to the AND element 56 are the polling number line use mode control signal 5EL (communication line L4) and the communication bus use permission signal TOK (communication line L8).

That is, the end notification line designation information read from the end notification line management circuit 53 by the end notification line designation encoder 54 specifies the output answer line when 5EL=1 and TOK=1 (permission to use the communication bus has been granted). Output gate 55
is output from the output terminal to polling numbers 1PNO to 3.

Further, the end answer receiving circuit 36 in the IBCJ is composed of a 4-bit shift register 57 and a delay element 58.

The input signal of the delay element 58 is the polling number line use mode control signal SEL (communication line L4), and the output is the counter pulse CP.

The contents of the shift register 57 are shifted using this counter pulse CP. The input of the shift register 57 is
This is the output of the end answer input gate 39, and the human power of the gate 39 is connected to the polling number line PNO~3. The output of the silt register 57 is connected to the completion notification line management circuit 34.

Next, the circuit configuration of the IPC interface control section 50 will be explained.

First, the communication bus use request circuit 43 in the talker section 30 of the IPC includes a polling number verification circuit 59 and a polling latch flip-flop 60.3 manual NA.
It consists of an ND element 61. Polling number verification @Route 5
The input of 9 is connected to PNO through the PNO~3 receiving gate 62.
~3 is connected. Polling number verification circuit 5
9 compares the polling number input via the PNO~3 receiving gate 62 with its own number. When the polling number and the self-number match, the output S62 of the polling number matching circuit 59 becomes a "high level".

S62 is polling latch flip flop 6o
is input to the D input terminal of.

Polling latch flip flop 6° is D-F
, F, (delay type flip-flop), and the counter pulse input terminal CP has a three-power NAND
Output S63 of element 61 is input. The inputs of the NAND element 61 are the bus request signal 564 from the talker control unit, the polling number synchronization signal PSYNC (communication line L5), and the negative logic input of the communication bus use permission signal TOK (communication line L8). , S64 is at a "high level" because a data communication request is issued to the talker section. PSYNC is a synchronization signal and periodically changes to a "high level" and a "low level."

is repeated, and TOK is at a "low level" because permission to use the communication bus has not been granted.The output S65 of the polling latch flip-flop 60 becomes a "high level" after S62 goes to a "high level". At the point where the level changes from level to low level, it rises to a high level and becomes a communication bus use request signal to be sent to the IBC4.

-4. Termination notification circuit 4 in the listener section 31 in each IPC
9 is a listener termination answer gland specification register 63 and a delay type flip-flop 65.3 human-powered NAND element 64, A
ND element 66 and polling number line PNO~3
It consists of a transmission gate 67 to.

The end answer line specification register 63 for listener is a 4-bit register, and its input is polling number line PNO~3.
This data is input via the PNO~3 reception gate 62. Counter pulse input terminal C of register 63
The output S66 of the three-power NAND element 64 is input to P. The input of the 3-person NAND element 64 is polling.
These are a number line synchronization signal PSYNC (communication line L5), a communication bus use permission signal TOK (communication line L8), and a reception OK status signal 367 from the risk control unit. T
OK is "high level", S67 is also "high level",
At the point where PSYNC changes from "low level" to "high level," a counter pulse is input, and end answer line designation data is input to register 63. Output S71 of register 63 is a transmission gate to PNO~3. 67 will be a one-man force.

On the other hand, the delay type flip-flop 65 uses the polling number line use mode control signal SEL (communication mL4) as a counter pulse, and inputs the end answer condition signal S6B from the risk control section to the D input terminal. 368 goes to a high level when the end answer can be sent.

Therefore, the output S69 of the flip-flop 65 is SE
The L signal changes to "high level" at the point when it changes from "high level" to "low level." S69 sends it to the risk control unit as a signal to reset the end answer condition.

S69 becomes the AND element 66 by one person. The other input is a negative logic input of the SEL signal. That is, AND
Element 66 outputs a "high level" output S70 when the SEL signal is at a low level.

S70 becomes the other input of the PNO~3 transmission gate 67 (the other is the output signal 571 of the end answer line designation register 63), so that when 370 is at high level, the end answer signal S71 is sent to the polling number line. PNO~
Output to 3.

Finally, the circuit configuration of the termination notification receiving circuit 44 in the talker section 30 of the IPC will be explained.

The end notification receiving circuit 44 includes a talker end answer line designation register 68, a three-man NAND element, a end answer collation circuit 70, and an end answer latch flip-flop 71.
, a delay element 72.

The data on the polling number line PNO-3 passed through the PNO-3 reception gate 62 is input data to the talker termination answer line designation register 68.

Register 68 is a 4-bit register whose counter
The output S72 of the three-man power NAND element 69 is input to the pulse terminal. The input of the NAND element 69 is polled.
These are a number synchronization signal PSYNC and a reception OK signal TANS. As a result, the end notification line designation data output from the end notification line designation circuit 34 of the IBC 4 is stored in the register 68.

The end answer collation circuit 70 uses the output of the register 68 as one input, and the other input as the PNO~3 receiving gate 6.
Polling number line P NO inputted via 2
~3 data. That is, the end talker number storage circuit 35 of the IBC 4 outputs the talker number to PNo.
It's number. These two numbers are compared, and if they match, a "high level" output 373 is output. This output S73 enters the D input terminal of the termination answer latch flip-flop 71. The SEL signal is input to the counter pulse input terminal of the flip-flop 71 via the delay element 72 . The output S74 of the flip-flop 71 is a termination answer signal and is sent to the talker control section.

Figure 6 shows IBO2 and each IPC (IPCo, IPCI
, ..., I PCn).

The communication line connecting IBO2 and each IPC includes a polling number line use mode control signal 5EL (communication line L4).
, polling number line PNO~3 (L3), polling number synchronization line PSYNC (L5), communication bus use request signal PINH (L7), communication bus use permission signal T
OK (L8) and listener designated reception OK signal TANS
It is O11 (LIO). SEL and PSYNC, TOK
is the direction from IBC4 to each IPC, PINH is the direction from each IPC
direction from to IBC4, other PNO~3 and TA
NSOll is a bidirectional communication line.

FIG. 7 shows a case where there is no communication request from the talker unit 30.
3 is a data sequence diagram of a polling number line use mode control signal SEL, polling number line signals PNO to 3, and a polling number line synchronization signal PSYNC. FIG.

When there is no communication request, there is a mode (polling mode) in which a new communication request is searched by scanning using a polling number, and a mode in which data transmission from the talker unit 30 to the listener unit 31 is completed and the data communication bus L1 is released. A mode in which the end answer signal from the listener unit 31 is waited for later (
There is a completion answer standby mode). Here, if the SEL signal is "high level", the mode is set to polling mode, and if the SEL signal is "low level", the mode is set to end answer standby mode.

When the SEL signal is at "high level", the data sent to the polling number lines PNO~3 is the polling number, and the communication bus use request circuit 43 of the talker section 30 responds to the rising edge of the polling number line synchronization signal PSYNC. The polling number is received at the appropriate timing and checked against the own number.

When the SEL signal is at a low level, the data sent to the polling number lines PNO~3 is an end answer signal, and the end notification receiving circuit 44 of the talker section 30 receives the PSYNC signal.
This end answer signal is received when is at a high level.

FIG. 8 is a data sequence diagram when the talker section 30 makes a communication request.

The polling number line use mode control signal SEL periodically repeats high level and low level, and as explained in FIG. 7, basically, when it is at high level,
The signal of polling number line PNO~3 is polling
It is a number, and if it is low level, it is an end answer signal.

There is now a communication request to the talker section 30. At this time, 5EL=
At “high level,” the polling number line synchronization signal PS
At the timing tl of the rise of YNC, the communication bus use request circuit 43 of the talker section 30 receives the signals of PNO to 3 as polling numbers, and performs comparison with its own number. If they match, the communication bus use request signal PINH is set to a low level (t2). The PINH signal is a low level active signal. The communication bus use permission circuit 33 of the IBC 4 receives the PINH signal, and the IBC 4 becomes usable. If so, set the communication bus use permission signal TOK to a high level (t3
). TOK is a high level active signal.

The data transmission circuit 40 of the talker unit 30 detects that the communication bus use permission signal TOK has become a "high level", and specifies the listener as the transmission destination via the data communication buses DATAO~8,
This is done using the data communication synchronization signal TSYNC and data order content signals TOD0 and TOD1. In other words, send the listener designation number to DATAO~8, and send the DA to TODOll.
A signal indicating that the signal from TAO to 8 is a listener designated number is sent. TSYNC periodically repeats "high level/low level".

The listener designation circuit 48 in the listener section 31 has DATAO~8.
It takes in the listener designated number at the rising timing (t4) of TSYNC, compares it with its own number, and if they match and is in a state where it can receive, it sends reception OK as a listener designated reception OK signal TANSO11.

When the reception OK signal is returned from the listener unit 31 to the IBC 4, the completion notification line designation circuit 34 of the IBO 2 specifies the sending communication line for the completion notification signal that the listener unit 31 outputs when the data communication between the processors is completed. . The end notification line is specified when 5EL = “high level” (polling number mode), communication TOK = “high level°” (data communication bus is in use), and TANSO1
1=Perform at reception OK timing (L5).

At this time, the data sent to PNO~3 is end answer line designation data, and the end notification receiving circuit 44 of the talker section 30 and the end notification circuit 49 of the listener section 31 transmit this data to the timing t5 when PSYNC rises. I will take the uke. The termination notification receiving circuit 44 of the talker unit 30 stores the received termination answer line designation data in the register 68, and later checks the data when the termination talker number is sent from the IBC 4. If they match, the process to complete the data communication that was being performed up to that point is executed. On the other hand, the end notification circuit 49 of the listener section 31 stores the received end answer line designation data in the register 63, and when the received data transfer to the processor is completed, the end answer line designation data is transferred to PCO~3. Execute the process of outputting to.

Finally, the sequence when the last data is transmitted using DATAO~8 will be explained.

The last data sent to DATAO~8 is TSYN
The signal is received by the data receiving circuit 45 of the listener section 31 at the rising timing of C (L6). As the data order content signal TODO1■, a signal indicating that it is the last data is transmitted. This data order content is decoded by a data order content decoding circuit 46, and when it is determined that the data is the last data, an answer signal to that effect is transmitted to the talker unit 30. The talker unit 30 detects that it is the final answer using the final answer detection circuit 42, returns the communication bus use request signal PINH to the "high level" (t7), and cancels the use request.The communication bus use permission circuit of the TBC4 33 detects that PINH has become a high level, and returns the communication bus use permission signal TOK to a low level.

As described above, the data communication bus can be released when data transmission using the data communication bus is completed.

Along with this, it is now possible to send a completion notification output from the listener section when the data transfer from the listener IPC to the processor is completed using the polling number line (instead of using the data communication bus in the conventional method). A circuit was added for the transmission (transmitting).

〔Effect of the invention〕

According to the present invention, in inter-processor communication, the data communication bus can be released at the time when data transfer between the inter-processor communication devices IPC is completed. As a result, the data communication bus can be opened earlier by the time required for data transfer from the IPC to the processor than in the conventional method, and it is possible to improve the usage efficiency of the data communication bus. As a result, the overall throughput of interprocessor communications in a multiprocessor system is improved.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the present invention, Fig. 2 is a system configuration diagram (1) of one embodiment, Fig. 3 is a system configuration diagram (2) of one embodiment, and Fig. 4 is an operation flowchart of one embodiment. , Figure 5 is a circuit diagram of IBC and fPc, Figure 6 is a connection diagram between IBC and IPC, Figure 7 is a polling sequence diagram (when there is no talker communication request), Figure 8 is a polling sequence diagram. (When there is a talker communication request), FIG. 9 is a system configuration diagram of the conventional system, and FIG. 10 is an operation flowchart of the conventional system. 1.1-2, . . . 1-n) Processor, 1.2-2, . . . , 2-n) Inter-processor communication device IPC1 (2-T-1, --2-T-n) Talker section, 1 (1-2(2-T (2-L-1, . . . 2-L-n) listener section, data communication bus, interprocessor bus control device IBC1, final answer detection data communication bus disconnection means, end notification line specification means, termination notification means, termination answer reception means, termination talker number storage transmission means, termination notification reception means. 3 ・ ・ ・ 4 ・ ・ ・ 5 ・ ・ ・

Claims (1)

[Claims] 1) A plurality of processors (1((1-1),...,(1-
n))), a data communication bus (3), a talker section (2-T) with a data transmission function and a listener section (2-L) with a data reception function, and each processor (1) is connected to the data communication bus (3). (3), an inter-processor communication device (2 ((2-1), . . . , (2-n))) for connecting to the data communication bus (3), and an inter-processor communication device that controls the control of the data communication bus (3) by polling control. In the inter-processor communication by the bus control device (4), the talker section (2-T-1) of the inter-processor communication device (1 (2-1)) receives from the sending processor (1 (1-1)). The data is transmitted via the data communication bus (3) to the listener unit (2
-L-n), the listener section (2
-L-n) to the talker unit (-T-1), detects the final answer indicating the end of reception, and detects the final answer transmitted from the data communication bus (-L-n) to the talker unit (-T-1)
The last answer detection data communication bus disconnection means (5) for canceling the exclusive use of the data communication bus (3) and the listener section (2-L-n) of the inter-processor communication device (n(2-n)) on the receiving side connect to the data communication bus (3). ), when the data received from the talker section (2-T-1) of the inter-processor communication device (1 (2-1)) on the sending side has been transferred to the processor n, the listener section a termination notification line designating means (6) for specifying a transmission line for the termination notification sent to the control device and transmitting the specified termination notification line number to the listener section (2-L-n) and the talker section; a termination notification means (7) for transmitting a termination notification to the inter-processor bus control device (4) using the transmission line specified by the specification means (6); and receiving the termination notification transmitted by the termination notification means (7). Upon receiving the termination notification received by the termination answer receiving unit (9) and the termination notification receiving unit (8), the termination notification is sent to the number of the inter-processor communication device having the talker unit that previously executed the data transmission (termination talker). an end talker number storage and transmission means (9) that stores the end talker number as a termination notice (number) and sends the end talker number to the talker unit as a termination notification; and an end talker number storage and transmission means (9) that transmits the end talker number. is received, the termination notification line designation number sent from the termination notification line designation means (6) and held is compared with the termination talker number, and if they match, the transmission side processor (1 (1- 1) Notify the completion of data communication to
An inter-processor communication system characterized by comprising: completion notification receiving means (10) for completing data communication processing. 2) The final answer detection data communication bus disconnection means (5)
is an inter-processor communication device (2-1, 2-2,..., 2
-n) talker section (2-T-1) 2-T-2,...
2-T-n), and by canceling the exclusive use of the data communication bus (3), it is possible for other processors to occupy the data communication bus (3) thereafter. . 3) The end notification line designating means (6) is included in the inter-processor bus control device (4).
) specifies which line the termination notification means (7) should use to send the termination notification among the polling lines used for granting control of the data communication bus (3), and the termination notification means (7) ) and the completion notification receiving means (10). 4) The termination notification means (7) is an inter-processor communication device (
2-1, 2-2, ..., 2-n) listener section (2-L
-1, 2-L-2, . 2. The inter-processor communication system according to claim 1, wherein, when the transmission of the received data to the receiving processor (1) is completed, the polling line is used to send a completion notification to notify the completion. 5) The end answer receiving means (8) and the end talker.
The number storage transmitting means (9) is included in the inter-processor bus control device (4), and stores the termination notification received by the termination answer receiving means (8) from the termination notification means (7) in the termination talker number memory. The transmitting side inter-processor communication device (2-1, 2-2, . . . , 2-
2. The inter-processor communication method according to claim 1, wherein the inter-processor communication method is transmitted to the processor. 6) The end talker number storage/transmission means (9) transmits the stored end talker number to the interprocessor communication device (2-1, 2-2, . . . , 2-) using a polling line.
n) talker section (2-T-1, 2-T-2,..., 2
-T-n). 7) The termination notification receiving means (10) retains the termination notification line designation number (polling line number) transmitted by the termination notification line designation means (6), and transmits the termination notification line designation number (polling line number) to the talker number storage transmission means (9). When you receive the end talker number from
2. The inter-processor communication system according to claim 1, wherein the numbers are compared, and if they match, the inter-processor communication process that has been executed is completed.