JPS63128834A - Data transmission system - Google Patents

Abstract

PURPOSE:To improve the utilizing efficiency of a common bus by applying inquiry of communication request of each terminal equipment via a line independent of a bus during the transmission of a packet on the bus. CONSTITUTION:A central controller 101 supplies an address and a clock for the inquiry of communication request to two-phase clock lines 106, 107 while checking a reply signal from a reply line 105. In receiving an inquiry signal of communication request, a terminal equipment 112-i having a transmission packet returns a reply signal to the inquiry to the controller 101 through the reply line 105. Then a common bus 102 is supervised and after a packet during transmission is finished or the idle state of a transmission medium is detected, the packet is sent to the bus 102. The communication request inquiry is applied by the control station 101 during the packet transmission in this way and the terminal equipment sends a packet at bus use enable state, then the bus is used almost without intermission.

Description

[Detailed description of the invention] [Industrial application field] More particularly, the present invention relates to a data transmission system.

In a transmission system in which multiple terminals communicate by sending and receiving information packets via a common line (bus), a central control unit gives permission to send packets, especially to prevent packets from colliding on the bus. It relates to a data transmission system using a polling method.

[Conventional technology]

In a transmission system in which data is transmitted by sharing a transmission medium (bus) between multiple terminal devices, LAN (Local Area
l'Jetwork) access method is well known. For example, in the COMA/CD access method, each device detects an unused state of the bus and sends out a packet. If a packet collision is detected, transmission is stopped, and the packet is retransmitted after a waiting time calculated according to a predetermined algorithm has elapsed. Furthermore, the talk/bus access method and the token ring access method control the right to send packets to the bus by circulating access rights to the bus called tokens. Regarding the above three types of access methods, IE, Draft Standards 802.3, 802.4, 80
2.5 (IEEEpraft 5 standard
802.3, 802.4, 802.5).

Another example of a bus access method is a polling method in which a control station is provided to control bus access rights, and the control station sequentially scans communication requests from each device and grants bus access rights to a device that has made one communication request. Are known. An example of a polling method is I80' Information Processing - Basic Mote Control Glossiers Fordata Communication Systems l5.
O1745-1975(E) (ISO''' engineering
ation process jng-basic m
ode control procedures for
rdata Communication System
ems 'i3Q 1745-1975 (E)).

[Problem that the invention seeks to solve]

The above-mentioned conventional technology has a problem in that it is not possible to increase the bus usage efficiency. That is, in the C8MA/CD access method, bus usage efficiency is low due to packet collisions. Also,
In the token bus access method and the token ring access method, after the packet is sent, the token is sent using the same bus, and data packets cannot be sent during that time, so it is not possible to increase the bus usage efficiency beyond a certain level.

Similarly, in the polling method, a control station sends a boring signal using a bus, so there is a problem in terms of the efficiency of use of the transmission medium.

An object of the present invention is to develop an access rights control method that enables highly efficient use of buses.

A line for sending inquiry signals for making requests is provided independently from the bus for transmitting packets, and while packets are being sent to the bus, communication request inquiries are made from the central control unit, and each terminal device receives communication requests. When an inquiry is received and there is a packet to be transmitted, a response signal in response to the communication request inquiry is transmitted on the independently installed circular line, and at the same time the bus status is monitored and the packet being transmitted is terminated. Alternatively, a packet is output when the idle state of the transmission medium is detected, and when the central control device receives a response signal to the communication request inquiry, it temporarily suspends the communication request inquiry to the next device and outputs a new packet to the transmission medium. This is achieved by configuring the transmission system to confirm that the communication request has been output and then restart the communication request inquiry to the next device.

[Effect]

When a terminal device having a packet to be transmitted receives an inquiry signal for a communication request, it returns a response signal to one inquiry;
By monitoring the bus and transmitting the packet after detecting the end of the packet being transmitted or the idle state of the transmission medium, bus usage efficiency can be increased. This is because even while a packet is being transmitted, the control station is inquiring for a communication request via an independent line.Especially when the load on the transmission system is heavy (that is, when there are many terminals making one communication request), the control station There is a very high probability that the next terminal to send the packet has been determined during transmission, so the terminal that should send the packet first detects the end of the packet being transmitted by another terminal or the idle state of the bus. This is because if the packets are output in a very short time from the end of one packet to the start of the next packet, the bus can be used almost seamlessly.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of an embodiment of a data transmission system according to the present invention. A plurality of terminals 112-1 to 112-N communicate with each other using the common bus 102 via interface devices 110-1 to 110-N, respectively. 111
-1 to 111-N are transmission lines connecting the terminal and the interface device. 103 is an address line for specifying each interface device in order to sequentially inquire about communication requests from each terminal device from the system control device; 104 is a line for sending an address enable signal indicating that the signal on the address line is valid;
105 is a transmission line for a response signal to a communication request inquiry. The system control device 101 checks the response signal from the response 105.

Address for communication request inquiry (address serves as inquiry signal for communication request inquiry) and clock 106.10
Supply 7. Common bus 102 physically consists of ten parallel transmission lines, and each interface device is connected to common bus 102 by a bidirectional tristate buffer circuit.

FIG. 2 shows the configuration of parallel signals transmitted on the common bus 102. There are 10 bits in total, and the pitches are bO to b7.
is the 8-bit data part, pits b8 to b9 are the second
As shown as ab in the figure, 2 bits indicate the data (packet) transmission state and indicate four states of the common bus 102: idle state, packet transmission start, packet transmission in progress, and packet transmission end.

Figure 3 shows a two-phase clock (lines 106° and 107 in Figure 1).
),! The relationship between the signals on the four-way bus 102 is shown. At the rising edge of clock CKI, data (
bO-b7) and a control signal (bits b8 to b9) are output and taken into the destination interface device at clock CLK2.

Therefore, for example, if a 4MHz clock is used, the common bus capacity is 4MHz x 8 pits = 32Mbps.
becomes.

FIG. 4 shows an example of the structure of a packet output from each interface device to the common bus. One packet is divided into 8 bits and output. The start and end of packets and the idle state of the common bus are controlled by 2 pins) (b8.b9
).

FIG. 5 shows an example of the configuration of the interface device 110-iO-. The terminal interface unit 206 controls bidirectional transmission with the terminal 112-i and sends the contents of the receive buffer 205 to the terminal 112-i, and! Ta.

Data from terminal 112-i is written to transmission buffer 204. The transmission/reception control unit 203 is the bus interface unit 2
01 from the common bus 102.

If the destination address of the packet matches the local address, the packet is written to the reception buffer 206. Also,
The transmission buffer 204 is monitored, and if there is a packet to be sent, the transmission right control unit 20 is sent via the communication request line 207.
A communication request is output to 2. The transmission right control unit 202 responds to the communication request inquiry, monitors the bus, and outputs an exaggeration permission signal 208 when it becomes possible to send a packet.

FIG. 6 shows a more detailed embodiment of the transmission right control section 2020. 102 to 105.207 in Figure 6
208 correspond to the numbers in FIGS. 1 and 5. Further, FIG. 7 is a timing chart for explaining the operation of FIG. 6. The contents of the address line 103 are captured by the address latch 306 at the falling edge of the address enable signal received on the address enable line 104.

The output of the address latch is compared with the local address.

If both match and there is a transmission request (207) from the transmission/reception control unit (203 in FIG. 5), the AND gate 30
5. A response signal is output via the tri-state buffer 308. The response line 1o5 connects the outputs of each interface device using wired logic, and one response line can collect response signals from all interface devices. 301 uses common bus pins b8 to b9 to detect idleness of the common bus or the end of a packet.

Since the output of the AND gate 304 may output a packet, the output of the AND gate 304 sets the R, S flip-flop 303, and the output of the S flip-flop 70 controls the transmission and reception of the communication enable signal via the line 208. The information is sent to section 203. The S7 lip-flop 303 is reset by the output of an AND gate 302 which detects that a packet is being transmitted on the common bus.

FIG. 7 is a diagram showing the operation timing of FIG. 6. The address signal (103 in FIG. 6) for communication request inquiry is updated at the rising edge of clock CK2, and the address enable signal is output in synchronization with clock CKI.

Since no response signal (response line 105 becomes @L") is returned from the interface device of the address output at time t2, it is determined that there is no communication request, and the address is updated at the rising edge of the primary clock CK2 (t4). Since the interface device responds to the next address, the address is not updated at time t6.

The transmission right control unit monitors the state of the common bus and determines the end of the packet at time 1. Detected by , and outputs send permission.

As a result, a packet is output with +'9, and the transmission request is @
The control device (101 in Figure 1) changes the response line to the "H#H#" level, updates the address with tlo, and inquires about the next interface device's communication request. .

FIG. 8 shows the configuration of the boring control section of the control device 101 shown in FIG. 1. N by the N-ary counter 402
The 7 traces of the terminals are output in sequence. The signal on the polling response line 105 is latched by the D-type flip-flop 405 at the falling edge of LCKI, and if there is no response signal (signal from 105: "H#"), the counter is counted up and output to the address enable l1151104. A signal is output. Also, if there is a response (10
5-line signal: @L''), counter count-up and address enable output are prohibited.

〔Effect of the invention〕

According to the present invention, it is possible to inquire about a communication request from the prefectural control unit even while a packet is being sent from a certain terminal.

゛ In addition, devices on other terminals that have the ability to transmit after the packet being transmitted can monitor the status of the common bus and output packets without interrupting the bus idle status. The efficiency of use can be increased.

[Brief explanation of the drawing]

101...Control device, 102...Common bus, 103
...Address, s! % 104...Address enable, 105...Response L 106,107...2
Phase clock, 110-1 to 110-N...Interface device, 111-1 to 111-N...Transmission line, 11
2-1 to 112-N...terminal, 201...bus interface, 202 transmission right control unit, 203...transmission/reception control unit, 204...transmission buffer, 205...
Receive buffer, 206...terminal interface, 30
1...Common bus idle state, packet end detector,
302, 304° 305...AND gate, 303.
... aS flip-flop, 306... address latch, 307... comparator.

Claims (1)

[Claims] 1. A common bus, and a plurality of terminals each connected to the bus via an interface device and communicating with each other;
In a data transmission system that includes a central control device that manages the use of the bus by the plurality of terminals, between the central control device and each of the interface devices, there is a connection between the central control device and the plurality of terminals in addition to the bus. a line for sending an inquiry signal for inquiring about communication requests;
A line for transmitting a response signal in response to the inquiry signal from the terminal to the central control device is installed, and after receiving the inquiry signal to each of the interface devices, the response signal is transmitted when there is a packet to be communicated. At the same time, means is provided for monitoring the transmission status of packets of other terminals on the bus, and transmitting its own packet when detecting a state in which there are no more packets of the other terminals, and receiving the response signal to the central control device. When this occurs, means is provided to interrupt the transmission of the inquiry signal to the next terminal, and after confirming that the own packet has been sent to the bus, to resend the inquiry signal to the next terminal. A data transmission system comprising: