EP0345334A1 - Managing interlocking - Google Patents

Managing interlocking

Info

Publication number
EP0345334A1
EP0345334A1 EP19890901009 EP89901009A EP0345334A1 EP 0345334 A1 EP0345334 A1 EP 0345334A1 EP 19890901009 EP19890901009 EP 19890901009 EP 89901009 A EP89901009 A EP 89901009A EP 0345334 A1 EP0345334 A1 EP 0345334A1
Authority
EP
European Patent Office
Prior art keywords
transaction
type
lock state
discriminant
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19890901009
Other languages
German (de)
French (fr)
Inventor
Michael J. K. Nielsen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of EP0345334A1 publication Critical patent/EP0345334A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system

Definitions

  • This invention relates to management of interlocking in computer systems with parallel processors using a common memory space.
  • An intercommunication bus provides a facility for transfer of information, packaged as transactions, between processors and between any processor and a common memory.
  • some means is provided for controlling access to the bus, receiving requests for and granting use of the bus.
  • a need for interlocking arises in such systems to forestall the use of data from some interrelated group of addresses (giving for example, the coordinates of a point) by one processor while this data is in the midst of being updated by another processor.
  • the present invention manages interlocking of addresses in a system with parallel processors using a common memory space by maintaining for each processor a record of the lock state of the system.
  • a processor seeks to initiate a transaction the transaction is analyzed against the lock state record, and the processor's request for access to the bus is transmitted only when the lock state of the system is in condition to process the transaction.
  • the lock state record is maintained up to date.
  • Figure 1 shows in block diagram form a computer system with parallel processors managing interlocking according to the invention.
  • Figure 2 shows in greater detail elements associated with an individual processor of Fig. 1.
  • computer system 10 includes as components processors 11 each connected to intercommunication bus 12 through interlock managing circuitry 13 and access controllers 14, which may be as described in copending application SN 123,958. Access controllers 14 in the aggregate control access of the processors to the bus. Memory store 15 is also connected to bus 12 and stores memory space used jointly by all the processors.
  • each processor 11 has an associated out-buffer 16 having a transaction characterization store 17 and a data store 18.
  • Characterization store 17 includes type discriminant store 36 and address store 37.
  • Each processor 11 also has an associated in-buffer 19 with a data store 21 and characterization store 20.
  • Characterization store 20 includes type discriminant store 34 and address store 35.
  • Out-buffer 16 is connected to bus 12 through channel 22 and to access controller 14 through channel 24; in-buffer 19 is connected to bus 12 through channel 23.
  • Update manager 25 is connected to intercommunication bus 12 through channel 26 and to access controller 14 through channel 52.
  • Out-analyzer 27 is connected to out-buffer 16 through channel 28, to processor 11 through channel 29 and to access controller 14 through channel 30.
  • Update manager 25 and out- analyzer 27 include conventional circuitry which will be further discussed in connection with the operations of the system.
  • Lock state record 31 is connected to update manager 25 through channels 32 and 51, and to out-analyzer 27 through channel 33.
  • Lock state record 31 has a capacity for storing two addresses and includes first locked address store 38, second locked address store 39, and F-discriminant store 40.
  • F-discriminant store holds signals indicating whether the address stores hold valid addresses. When an address store holds a valid address it will be interpreted as full, and when all the. locked address stores hold valid addresses the lock state record will be interpreted as FULL.
  • a processor when a processor needs to move information to or from the common memory 15 or some other system component, it defines a bus transaction which specifies the activity to take place on the bus to accomplish the desired exchange of information and loads the specification into out-buffer 16 for transmission over the bus.
  • the defined specification includes a locking characterization characterizing the effect of the transaction on the lock state of the system.
  • the locking characterization includes a type discriminant which identifies the type of locking operations called for by the transaction and an address in the common memory space which will be affected by the transaction.
  • the types of transaction include type LOCK, indicating that the address of the transaction is to be locked, type UNLOCK, indicating that the address of the transaction is to be unlocked, type NOLOCK, indicating that the address of the - transaction admits of being locked but in the transaction is not to be locked, and NONLOCKING, indicating that the address of the transaction is outside the interlocking scheme and does not admit of being locked.
  • type LOCK indicating that the address of the transaction is to be locked
  • type UNLOCK indicating that the address of the transaction is to be unlocked
  • type NOLOCK indicating that the address of the - transaction admits of being locked but in the transaction is not to be locked
  • NONLOCKING indicating that the address of the transaction is outside the interlocking scheme and does not admit of being locked.
  • Particular system designs may use less than all of these types.
  • the type discriminant and the transaction address are lodged in the processor's out-buffer in corresponding stores which may be conventional registers. Transmit locking characterization signals indicating the information in the characterization store of the out- buffer are transmitted from out-buffer 16 to out- analyzer 27 on channel 28. After the out-buffer has been thus loaded, the processor sends a ready-to-send signal on channel 29 to out-analyzer 27, indicating that the processor seeks to initiate a transaction on the bus and that its out-buffer is ready to feed the transaction. At this point the out-buffer does nothing further until it receives a bus grant signal from access controller 14 through channel 24.
  • the out-analyzer 27 receives lock state signals from the lock state record and, as mentioned before, transmits locking characterization signals from the out-buffer and ready to send signals from the processor. It analyzes these input signals using conventional logic circuitry to generate criteria for sending an access request signal on channel 30 to the access controller 14. In particular, when a ready- to-send signal indicates the processor seeks to initiate a transaction and the transmit locking characterization signal indicates the prospective transaction is of type UNLOCK or of type NONLOCKING, the out-analyzer emits an access request signal.
  • the transmit locking characterization signal indicates the prospective transaction is of type NOLOCK
  • the lock state signal indicates that none of the valid locked addresses matches the address of the locking characterization
  • the out-analyzer emits an access request signal.
  • the transmit locking characterization signal indicates the prospective transaction is of type LOCK
  • the lock state signal indicates that none of the valid locked addresses matches the address of the locking characterization and that the lock state record is NOTFULL, the out-analyzer emits an access request signal.
  • the type discriminant and address of all transactions passed on the bus 12, whether originating with the local processor or another, are presented to update manager 25 through channel 26.
  • the update manager receives a timing signal from the access controller 14 on channel 52 indicating that a valid locking characterization is being presented, it makes a logical analysis of the locking characterization in conjunction with lock state signals from the lock state record and latches the result. Then it effects a revision of the lock state record in accordance with the analysis.
  • the update manager sets the address value of the address-1 store to the address of the locking characterization signal and the F-discriminant of the address-1 store to FULL; when the received locking characterization is of type LOCK and address-1 store of the lock state record is FULL, the update manager sets the address value of the address-2 store to the address of the locking characterization signal and the F-discriminant of the address-2 store to FULL.
  • the update manager sets the F-discriminant of the address-1 store to NOT FULL; when the received locking characterization is of type UNLOCK and the transaction address matches the address of the address-2 store of the lock state record and the
  • the update manager sets the F-discriminant of the address-2 store to NOT FULL.
  • the update analyzer uses conventional logic circuitry to effect the stated functions for which there is no need of detailed description.
  • each processing station keeps its own record of locked addresses, all the records being identical. Every change in the locked addresses is made through a transaction that propagates over the bus and is available to every processing station irrespective of whether the station is involved in the data movement of the transaction.
  • Each processing station also refers to its lock state record to delay requesting use of the bus when the address it seeks to access is locked, this procedure avoids burdening the bus including the bus access control with transactions which would only be rejected if locking were done at the site of the memory.
  • each processor comply with certain restraints as to the temporal ordering of the transactions which it initiates.
  • no LOCK type or UNLOCK type transactions must be initiated by a processor except in pairs one of each type and relating to a single address, with the LOCK type preceding the UNLOCK type. This pairing is of course what is usually done with interlocking systems, but it is necessary to preclude exceptions.
  • the system specifically described above has a capacity to concurrently lock two addresses corresponding to the two-address store of the lock state record.
  • Alternative systems with capacities to handle more locked addresses can readily be implemented by providing the lock state record with more address registers and by straightforwardly augmenting the logic of out-analyzer and the up-date manager to test and manage the additional address stores.
  • An alternative system with a one-address locking capacity can also be implemented, and for this case some particular economies are possible.
  • the address registers of the lock state store may be eliminated and the
  • F-discriminant reduced to a single bit of storage indicating whether some address is currently locked (i.e. , NOTFULL) .
  • Transactions of the LOCK or NOLOCK types would be deferred while the F-discriminant was FULL. Receipt of a LOCK type transaction would result in setting the F-discriminant to FULL, and receipt of an UNLOCK type transaction in setting the F-discriminant to NOTFULL.

Abstract

Interlocking of addresses in a system with par­ allel processors using a common memory space (15) is managed by maintaining for each processor a re­ cord of the lock state of the system. When a processor seeks to initiate a transaction, the transaction is ana­ lyzed against the lock state record (31), and the pro­ cessor's request for access to an intercommunication bus is transmitted only when the lock state of the sys­ tem is in condition to process the transaction. By monitoring and analyzing bus transactions, the lock state record (31) of each processor is maintained up to date. By thus blocking a transaction involving a locked address before the bus is requested, the tying up of the bus in futile activity is avoided.

Description

MANAGING INTERLOCKING
BRIEF SUMMARY OF THE INVENTION
This invention relates to management of interlocking in computer systems with parallel processors using a common memory space.
Certain computer systems are designed to have several processors which process instructions quasi- independently in parallel but use a common memory space. An intercommunication bus provides a facility for transfer of information, packaged as transactions, between processors and between any processor and a common memory. In order to assure that the bus is used by the several processors in an orderly way, some means is provided for controlling access to the bus, receiving requests for and granting use of the bus. A need for interlocking arises in such systems to forestall the use of data from some interrelated group of addresses (giving for example, the coordinates of a point) by one processor while this data is in the midst of being updated by another processor.
The present invention manages interlocking of addresses in a system with parallel processors using a common memory space by maintaining for each processor a record of the lock state of the system. When a processor seeks to initiate a transaction, the transaction is analyzed against the lock state record, and the processor's request for access to the bus is transmitted only when the lock state of the system is in condition to process the transaction. By monitoring and analyzing bus transactions, the lock state record is maintained up to date. By thus blocking a transaction involving a locked address before the bus is requested, the tying up of the bus in futile activity is avoided.
BRIEF DESCRIPTION OF THE DRAWING
Figure 1 shows in block diagram form a computer system with parallel processors managing interlocking according to the invention.
Figure 2 shows in greater detail elements associated with an individual processor of Fig. 1.
DETAILED DESCRIPTION
Referring to the Figures, computer system 10 includes as components processors 11 each connected to intercommunication bus 12 through interlock managing circuitry 13 and access controllers 14, which may be as described in copending application SN 123,958. Access controllers 14 in the aggregate control access of the processors to the bus. Memory store 15 is also connected to bus 12 and stores memory space used jointly by all the processors.
As shown more particularly in Fig. 2, each processor 11 has an associated out-buffer 16 having a transaction characterization store 17 and a data store 18. Characterization store 17 includes type discriminant store 36 and address store 37. Each processor 11 also has an associated in-buffer 19 with a data store 21 and characterization store 20. Characterization store 20 includes type discriminant store 34 and address store 35. Out-buffer 16 is connected to bus 12 through channel 22 and to access controller 14 through channel 24; in-buffer 19 is connected to bus 12 through channel 23. Update manager 25 is connected to intercommunication bus 12 through channel 26 and to access controller 14 through channel 52. Out-analyzer 27 is connected to out-buffer 16 through channel 28, to processor 11 through channel 29 and to access controller 14 through channel 30. Update manager 25 and out- analyzer 27 include conventional circuitry which will be further discussed in connection with the operations of the system. Lock state record 31 is connected to update manager 25 through channels 32 and 51, and to out-analyzer 27 through channel 33. Lock state record 31 has a capacity for storing two addresses and includes first locked address store 38, second locked address store 39, and F-discriminant store 40. F-discriminant store holds signals indicating whether the address stores hold valid addresses. When an address store holds a valid address it will be interpreted as full, and when all the. locked address stores hold valid addresses the lock state record will be interpreted as FULL.
Turning now to the operation of the system, when a processor needs to move information to or from the common memory 15 or some other system component, it defines a bus transaction which specifies the activity to take place on the bus to accomplish the desired exchange of information and loads the specification into out-buffer 16 for transmission over the bus. The defined specification includes a locking characterization characterizing the effect of the transaction on the lock state of the system. The locking characterization includes a type discriminant which identifies the type of locking operations called for by the transaction and an address in the common memory space which will be affected by the transaction. The types of transaction include type LOCK, indicating that the address of the transaction is to be locked, type UNLOCK, indicating that the address of the transaction is to be unlocked, type NOLOCK, indicating that the address of the - transaction admits of being locked but in the transaction is not to be locked, and NONLOCKING, indicating that the address of the transaction is outside the interlocking scheme and does not admit of being locked. Particular system designs may use less than all of these types.
The type discriminant and the transaction address are lodged in the processor's out-buffer in corresponding stores which may be conventional registers. Transmit locking characterization signals indicating the information in the characterization store of the out- buffer are transmitted from out-buffer 16 to out- analyzer 27 on channel 28. After the out-buffer has been thus loaded, the processor sends a ready-to-send signal on channel 29 to out-analyzer 27, indicating that the processor seeks to initiate a transaction on the bus and that its out-buffer is ready to feed the transaction. At this point the out-buffer does nothing further until it receives a bus grant signal from access controller 14 through channel 24.
The out-analyzer 27 receives lock state signals from the lock state record and, as mentioned before, transmits locking characterization signals from the out-buffer and ready to send signals from the processor. It analyzes these input signals using conventional logic circuitry to generate criteria for sending an access request signal on channel 30 to the access controller 14. In particular, when a ready- to-send signal indicates the processor seeks to initiate a transaction and the transmit locking characterization signal indicates the prospective transaction is of type UNLOCK or of type NONLOCKING, the out-analyzer emits an access request signal.
When a ready-to-send signal indicates the processor seeks to initiate a transaction, the transmit locking characterization signal indicates the prospective transaction is of type NOLOCK, and the lock state signal indicates that none of the valid locked addresses matches the address of the locking characterization, the out-analyzer emits an access request signal. When a ready-to-send signal indicates the processor seeks to initiate a transaction, the transmit locking characterization signal indicates the prospective transaction is of type LOCK, and the lock state signal indicates that none of the valid locked addresses matches the address of the locking characterization and that the lock state record is NOTFULL, the out-analyzer emits an access request signal. For all conditions other than those enumerated an access request signal is not sent to the access controller, with the result that the request to use the bus for a transaction is deferred until the lock state record is revised to a state compatible with one of the enumerated conditions enabling transmitting the access request signal.
On the incoming side, the type discriminant and address of all transactions passed on the bus 12, whether originating with the local processor or another, are presented to update manager 25 through channel 26. When the update manager receives a timing signal from the access controller 14 on channel 52 indicating that a valid locking characterization is being presented, it makes a logical analysis of the locking characterization in conjunction with lock state signals from the lock state record and latches the result. Then it effects a revision of the lock state record in accordance with the analysis. More particularly, when the received locking characterization is of type LOCK and address-1 store of the lock state record is NOTFULL, the update manager sets the address value of the address-1 store to the address of the locking characterization signal and the F-discriminant of the address-1 store to FULL; when the received locking characterization is of type LOCK and address-1 store of the lock state record is FULL, the update manager sets the address value of the address-2 store to the address of the locking characterization signal and the F-discriminant of the address-2 store to FULL. When the received locking characterization is of type UNLOCK and the transaction address matches the address of the address 1 store of the lock state record and the F-discriminant of the address-l store is FULL, the update manager sets the F-discriminant of the address-1 store to NOT FULL; when the received locking characterization is of type UNLOCK and the transaction address matches the address of the address-2 store of the lock state record and the
F-discriminant of the address-2 store is FULL, the update manager sets the F-discriminant of the address-2 store to NOT FULL.
The update analyzer uses conventional logic circuitry to effect the stated functions for which there is no need of detailed description.
From a global or system point of view, it can be seen that the responsibility for managing the interlocking is distributed among the several processing stations although data is stored in a central memory facility. Each processing station keeps its own record of locked addresses, all the records being identical. Every change in the locked addresses is made through a transaction that propagates over the bus and is available to every processing station irrespective of whether the station is involved in the data movement of the transaction. Each processing station also refers to its lock state record to delay requesting use of the bus when the address it seeks to access is locked, this procedure avoids burdening the bus including the bus access control with transactions which would only be rejected if locking were done at the site of the memory.
Another global aspect of the operation of the system is that each processor comply with certain restraints as to the temporal ordering of the transactions which it initiates. In particular, no LOCK type or UNLOCK type transactions must be initiated by a processor except in pairs one of each type and relating to a single address, with the LOCK type preceding the UNLOCK type. This pairing is of course what is usually done with interlocking systems, but it is necessary to preclude exceptions.
The system specifically described above has a capacity to concurrently lock two addresses corresponding to the two-address store of the lock state record. Alternative systems with capacities to handle more locked addresses can readily be implemented by providing the lock state record with more address registers and by straightforwardly augmenting the logic of out-analyzer and the up-date manager to test and manage the additional address stores. An alternative system with a one-address locking capacity can also be implemented, and for this case some particular economies are possible. For a system with a one-address capacity, the address registers of the lock state store may be eliminated and the
F-discriminant reduced to a single bit of storage indicating whether some address is currently locked (i.e. , NOTFULL) . Transactions of the LOCK or NOLOCK types would be deferred while the F-discriminant was FULL. Receipt of a LOCK type transaction would result in setting the F-discriminant to FULL, and receipt of an UNLOCK type transaction in setting the F-discriminant to NOTFULL.

Claims

WHAT IS CLAIMED IS:
1. A method of managing interlocking in a computer system having parallel processors using a common memory space, an intercommunication bus for transferring information from one system component to another, and means for controlling access of the processors to said bus for initiating information transfer transactions thereon comprising the steps maintain for each processor an associated lock state record of the lock state of the system, said lock state record being of predetermined capacity, define for every transaction a locking characterization characterizing the effect of the transaction on the lock state of the system, make, prior to requesting by any of said processors access to said bus for initiating a transaction, a transmission analysis of the locking characterization of the transaction in conjunction with the associated lock state record, defer, contingent on the results of said transmission analysis, a bus access request to said ~ means for controlling access, make, on receiving by any processor of a transaction, a receiving analysis with reference to the locking characterization of the received transaction and revise, in accordance with said receiving analysis, the lock state record.
2. A method as claimed in Claim 1, wherein said lock state record includes an F-discriminant indicating whether the capacity of the lock state record is FULL or NOT FULL, wherein said locking characterization includes a type discriminant indicating which of a plurality of transaction types the transaction belongs to, one of said transaction types being type LOCK, indicating that the transaction is to be conditionally deferred and involves an address to be locked when received, and one of said transaction types being type UNLOCK, indicating that the transaction is never to be deferred and involves an address to be unlocked when received, wherein when said transaction is of type LOCK, a bus access request to transmit the transaction is deferred while said F-discriminant is FULL, wherein when said transaction is of type UNLOCK, a bus access request to transmit the transaction is not deferred, wherein when a transaction is of type UNLOCK is received by a processor, the F-discriminant of its associated lock state record is set to NOT FULL.
3. A method as claimed in Claim 2, one of said transaction types being type NOLOCK, wherein when a transaction to be initiated is of type NOLOCK, a bus access request to transmit the transaction is deferred while said F-discriminant is FULL, wherein when a transaction of type NOLOCK is received by a processor, the F-discriminant of its associated lock state record is not changed.
4. A method as claimed in Claim 2, wherein the locking characterization of transactions includes an address, and wherein said lock state record has a capacity to list a plurality of concurrently locked out addresses, wherein when a transaction is of type LOCK, a bus access request to transmit the transaction is deferred while its address is listed in said associated lock state record and wherein when a transaction of type LOCK is received by a processor, the address thereof is listed in said associated lock state record.
5. A method as claimed in Claim 4, wherein when said transaction is of type UNLOCK, a bus access request to transmit the transaction is not deferred and wherein when said transaction is of type UNLOCK is received by a processor, the address thereof is delisted in said associated lock state record.
6. A method as claimed in Claim 5, one of said transaction types being type NOLOCK, wherein when a transaction is of type NOLOCK, a bus access request to transmit the transaction is deferred while its address is listed in said associated lock state record and wherein when a transaction of type NOLOCK is received by a processor, its associated lock state record is not changed.
7. A method as claimed in Claim 2, including the step initiate all LOCK type and UNLOCK type transactions in pairs one of each type and relating to a single address, with the LOCK type preceding the UNLOCK type.
8. Apparatus for managing interlocking in a computer system having parallel processors using a common memory space, an intercommunication bus for transferring information in transactions from one system component to another, and access control means for controlling access of the processors to said bus for initiating information transfer transactions thereon comprising in association with each processor: an out-buffer connected to said processor and to said bus for storing information to be transferred on said bus, said out-buffer including a characterization store for storing a locking characterization for a transaction ready to be transmitted, a lock state record for storing the lock state of the system, said lock state record being of predetermined capacity, said lock state record including an F-discriminant indicating whether the locking capacity of the system is FULL or NOTFULL, an update manager connected to receive received locking characterization signals from said intercommunications bus and to deliver update signals to said lock state record, and an out-analyzer connected to receive transmit locking.characterization signals from said out- buffer, to receive ready-to-send signals from said processor, to receive lock-state signals from said lock state record, and to transmit access request signals to said access control means, wherein said locking characterization includes a type discriminant indicating which of a plurality of transaction types a transaction belongs to, one of said transaction types being type LOCK, and one of said transaction types being type UNLOCK, said out-analyzer responding to receiving a transmit locking characterization signal with a type discriminant of type LOCK and a ready-to-send signal by deferring sending an access request signal while receiving a lock state signal indicating said
F-discriminant is FULL, said out-analyzer responding to receiving a transmit locking characterization signal with a type discriminant of type UNLOCK, and a ready-to-send signal by transmitting a bus access request signal, said update manager responding to receiving a received locking characterization signal with a type discriminant of type UNLOCK by transmitting an update signal setting said F-discriminant to NOTFULL.
9. Apparatus as claimed in Claim 8, one of said transaction types being type NOLOCK, said out-analyzer responding to receiving a transmit locking characterization signal with a type discriminant of type NOLOCK and a ready-to-send signal by deferring sending an access request signal while receiving a lock state signal indicating said F-discriminant is FULL, said update manager responding to receiving a received locking characterization signal with a type discriminant of type NOLOCK by not transmitting an update signal changing said F-discriminant.
10. Apparatus as claimed in Claim 8, wherein said lock state record has list means for listing a plurality of concurrently locked out addresses, and wherein the locking characterization of transactions includes an address, said out-analyzer responding to receiving a transmit locking characterization signal with a type discriminant of type LOCK and a transaction address and a ready-to-send signal by deferring sending an access request signal while receiving a lock state signal indicating that the transaction address is listed as a locked out address, said update manager responding to receiving a received locking characterization signal with a type discriminant of type LOCK and designating a received transaction address by transmitting an update signal causing said received transaction to be listed in said associated lock state record.
11. Apparatus as claimed in Claim 10, said out-analyzer responding to receiving a transmit locking characterization signal with a type discriminant of type UNLOCK and a transaction address and a ready-to-send signal by transmitting an access request signal, and said update manager responding to receiving a received locking characterization signal with a type discriminant of type UNLOCK and designating a received transaction address by transmitting an update signal causing said received transaction to be delisted in said associated lock state record.
12. Apparatus as claimed in Claim 11, one of said transaction types being type NOLOCK, said out-analyzer responding to receiving a transmit locking characterization signal with a type discriminant of type NOLOCK and a transaction address and a ready-to-send signal by deferring sending an access request signal while receiving a lock state signal indicating that the transaction address is listed as a locked out address, and said update manager responding to receiving a received locking characterization signal with a type discriminant of type NOLOCK and designating a received transaction address by not transmitting an update signal causing said associated lock state record to be changed.
EP19890901009 1987-12-18 1988-12-14 Managing interlocking Withdrawn EP0345334A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13477187A 1987-12-18 1987-12-18
US134771 1998-08-12

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EP0433095B1 (en) * 1989-12-15 1997-08-27 Fujitsu Limited Exclusive memory region control system
US5721870A (en) * 1994-05-25 1998-02-24 Nec Corporation Lock control for a shared main storage data processing system
JP2776759B2 (en) * 1995-04-14 1998-07-16 甲府日本電気株式会社 Lock request control device
DE102007044803A1 (en) * 2007-09-20 2009-04-09 Robert Bosch Gmbh Circuit arrangement for signal reception and generation and method for operating this circuit arrangement

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JPS58214957A (en) * 1982-06-09 1983-12-14 Mitsubishi Electric Corp Computer system

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JPH02501780A (en) 1990-06-14

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