EP0345334A1 - Gestion de l'enchevetrement d'adresses - Google Patents

Gestion de l'enchevetrement d'adresses

Info

Publication number
EP0345334A1
EP0345334A1 EP19890901009 EP89901009A EP0345334A1 EP 0345334 A1 EP0345334 A1 EP 0345334A1 EP 19890901009 EP19890901009 EP 19890901009 EP 89901009 A EP89901009 A EP 89901009A EP 0345334 A1 EP0345334 A1 EP 0345334A1
Authority
EP
European Patent Office
Prior art keywords
transaction
type
lock state
discriminant
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19890901009
Other languages
German (de)
English (en)
Inventor
Michael J. K. Nielsen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of EP0345334A1 publication Critical patent/EP0345334A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system

Definitions

  • This invention relates to management of interlocking in computer systems with parallel processors using a common memory space.
  • An intercommunication bus provides a facility for transfer of information, packaged as transactions, between processors and between any processor and a common memory.
  • some means is provided for controlling access to the bus, receiving requests for and granting use of the bus.
  • a need for interlocking arises in such systems to forestall the use of data from some interrelated group of addresses (giving for example, the coordinates of a point) by one processor while this data is in the midst of being updated by another processor.
  • the present invention manages interlocking of addresses in a system with parallel processors using a common memory space by maintaining for each processor a record of the lock state of the system.
  • a processor seeks to initiate a transaction the transaction is analyzed against the lock state record, and the processor's request for access to the bus is transmitted only when the lock state of the system is in condition to process the transaction.
  • the lock state record is maintained up to date.
  • Figure 1 shows in block diagram form a computer system with parallel processors managing interlocking according to the invention.
  • Figure 2 shows in greater detail elements associated with an individual processor of Fig. 1.
  • computer system 10 includes as components processors 11 each connected to intercommunication bus 12 through interlock managing circuitry 13 and access controllers 14, which may be as described in copending application SN 123,958. Access controllers 14 in the aggregate control access of the processors to the bus. Memory store 15 is also connected to bus 12 and stores memory space used jointly by all the processors.
  • each processor 11 has an associated out-buffer 16 having a transaction characterization store 17 and a data store 18.
  • Characterization store 17 includes type discriminant store 36 and address store 37.
  • Each processor 11 also has an associated in-buffer 19 with a data store 21 and characterization store 20.
  • Characterization store 20 includes type discriminant store 34 and address store 35.
  • Out-buffer 16 is connected to bus 12 through channel 22 and to access controller 14 through channel 24; in-buffer 19 is connected to bus 12 through channel 23.
  • Update manager 25 is connected to intercommunication bus 12 through channel 26 and to access controller 14 through channel 52.
  • Out-analyzer 27 is connected to out-buffer 16 through channel 28, to processor 11 through channel 29 and to access controller 14 through channel 30.
  • Update manager 25 and out- analyzer 27 include conventional circuitry which will be further discussed in connection with the operations of the system.
  • Lock state record 31 is connected to update manager 25 through channels 32 and 51, and to out-analyzer 27 through channel 33.
  • Lock state record 31 has a capacity for storing two addresses and includes first locked address store 38, second locked address store 39, and F-discriminant store 40.
  • F-discriminant store holds signals indicating whether the address stores hold valid addresses. When an address store holds a valid address it will be interpreted as full, and when all the. locked address stores hold valid addresses the lock state record will be interpreted as FULL.
  • a processor when a processor needs to move information to or from the common memory 15 or some other system component, it defines a bus transaction which specifies the activity to take place on the bus to accomplish the desired exchange of information and loads the specification into out-buffer 16 for transmission over the bus.
  • the defined specification includes a locking characterization characterizing the effect of the transaction on the lock state of the system.
  • the locking characterization includes a type discriminant which identifies the type of locking operations called for by the transaction and an address in the common memory space which will be affected by the transaction.
  • the types of transaction include type LOCK, indicating that the address of the transaction is to be locked, type UNLOCK, indicating that the address of the transaction is to be unlocked, type NOLOCK, indicating that the address of the - transaction admits of being locked but in the transaction is not to be locked, and NONLOCKING, indicating that the address of the transaction is outside the interlocking scheme and does not admit of being locked.
  • type LOCK indicating that the address of the transaction is to be locked
  • type UNLOCK indicating that the address of the transaction is to be unlocked
  • type NOLOCK indicating that the address of the - transaction admits of being locked but in the transaction is not to be locked
  • NONLOCKING indicating that the address of the transaction is outside the interlocking scheme and does not admit of being locked.
  • Particular system designs may use less than all of these types.
  • the type discriminant and the transaction address are lodged in the processor's out-buffer in corresponding stores which may be conventional registers. Transmit locking characterization signals indicating the information in the characterization store of the out- buffer are transmitted from out-buffer 16 to out- analyzer 27 on channel 28. After the out-buffer has been thus loaded, the processor sends a ready-to-send signal on channel 29 to out-analyzer 27, indicating that the processor seeks to initiate a transaction on the bus and that its out-buffer is ready to feed the transaction. At this point the out-buffer does nothing further until it receives a bus grant signal from access controller 14 through channel 24.
  • the out-analyzer 27 receives lock state signals from the lock state record and, as mentioned before, transmits locking characterization signals from the out-buffer and ready to send signals from the processor. It analyzes these input signals using conventional logic circuitry to generate criteria for sending an access request signal on channel 30 to the access controller 14. In particular, when a ready- to-send signal indicates the processor seeks to initiate a transaction and the transmit locking characterization signal indicates the prospective transaction is of type UNLOCK or of type NONLOCKING, the out-analyzer emits an access request signal.
  • the transmit locking characterization signal indicates the prospective transaction is of type NOLOCK
  • the lock state signal indicates that none of the valid locked addresses matches the address of the locking characterization
  • the out-analyzer emits an access request signal.
  • the transmit locking characterization signal indicates the prospective transaction is of type LOCK
  • the lock state signal indicates that none of the valid locked addresses matches the address of the locking characterization and that the lock state record is NOTFULL, the out-analyzer emits an access request signal.
  • the type discriminant and address of all transactions passed on the bus 12, whether originating with the local processor or another, are presented to update manager 25 through channel 26.
  • the update manager receives a timing signal from the access controller 14 on channel 52 indicating that a valid locking characterization is being presented, it makes a logical analysis of the locking characterization in conjunction with lock state signals from the lock state record and latches the result. Then it effects a revision of the lock state record in accordance with the analysis.
  • the update manager sets the address value of the address-1 store to the address of the locking characterization signal and the F-discriminant of the address-1 store to FULL; when the received locking characterization is of type LOCK and address-1 store of the lock state record is FULL, the update manager sets the address value of the address-2 store to the address of the locking characterization signal and the F-discriminant of the address-2 store to FULL.
  • the update manager sets the F-discriminant of the address-1 store to NOT FULL; when the received locking characterization is of type UNLOCK and the transaction address matches the address of the address-2 store of the lock state record and the
  • the update manager sets the F-discriminant of the address-2 store to NOT FULL.
  • the update analyzer uses conventional logic circuitry to effect the stated functions for which there is no need of detailed description.
  • each processing station keeps its own record of locked addresses, all the records being identical. Every change in the locked addresses is made through a transaction that propagates over the bus and is available to every processing station irrespective of whether the station is involved in the data movement of the transaction.
  • Each processing station also refers to its lock state record to delay requesting use of the bus when the address it seeks to access is locked, this procedure avoids burdening the bus including the bus access control with transactions which would only be rejected if locking were done at the site of the memory.
  • each processor comply with certain restraints as to the temporal ordering of the transactions which it initiates.
  • no LOCK type or UNLOCK type transactions must be initiated by a processor except in pairs one of each type and relating to a single address, with the LOCK type preceding the UNLOCK type. This pairing is of course what is usually done with interlocking systems, but it is necessary to preclude exceptions.
  • the system specifically described above has a capacity to concurrently lock two addresses corresponding to the two-address store of the lock state record.
  • Alternative systems with capacities to handle more locked addresses can readily be implemented by providing the lock state record with more address registers and by straightforwardly augmenting the logic of out-analyzer and the up-date manager to test and manage the additional address stores.
  • An alternative system with a one-address locking capacity can also be implemented, and for this case some particular economies are possible.
  • the address registers of the lock state store may be eliminated and the
  • F-discriminant reduced to a single bit of storage indicating whether some address is currently locked (i.e. , NOTFULL) .
  • Transactions of the LOCK or NOLOCK types would be deferred while the F-discriminant was FULL. Receipt of a LOCK type transaction would result in setting the F-discriminant to FULL, and receipt of an UNLOCK type transaction in setting the F-discriminant to NOTFULL.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

L'enchevêtrement d'adresses dans un système à processeurs parallèles utilisant un espace mémoire commun (15) est géré par l'établissement pour chaque processeur d'un tableau de l'état de blocage du système. Lorsqu'un processeur cherche à initier une transaction, cette transaction est analysée par comparaison avec le tableau de l'état de blocage (31), et la demande d'accès du processeur à un bus d'intercommunication n'est transmise que lorsque l'état de blocage du système permet de traiter la transaction. Le contrôle et l'analyse des transactions du bus permettent de maintenir à jour le tableau de l'état de blocage (31) de chaque processeur. Ainsi, grâce au blocage d'une transaction mettant en jeu une adresse verrouillée avant que le bus n'ait fait l'objet d'une demande d'accès, on évite la mobilisation du bus pour des activités futiles.
EP19890901009 1987-12-18 1988-12-14 Gestion de l'enchevetrement d'adresses Withdrawn EP0345334A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13477187A 1987-12-18 1987-12-18
US134771 1987-12-18

Publications (1)

Publication Number Publication Date
EP0345334A1 true EP0345334A1 (fr) 1989-12-13

Family

ID=22464918

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19890901009 Withdrawn EP0345334A1 (fr) 1987-12-18 1988-12-14 Gestion de l'enchevetrement d'adresses

Country Status (3)

Country Link
EP (1) EP0345334A1 (fr)
JP (1) JPH02501780A (fr)
WO (1) WO1989006011A1 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE68924992T2 (de) * 1988-02-23 1996-07-25 Digital Equipment Corp Symmetrische Steuerungsanordnung für Multiverarbeitung.
US5050072A (en) * 1988-06-17 1991-09-17 Modular Computer Systems, Inc. Semaphore memory to reduce common bus contention to global memory with localized semaphores in a multiprocessor system
DE69031333T2 (de) * 1989-12-15 1998-01-02 Fujitsu Ltd Steuerungssystem für einen exklusiven Speicherbereich
US5721870A (en) * 1994-05-25 1998-02-24 Nec Corporation Lock control for a shared main storage data processing system
JP2776759B2 (ja) * 1995-04-14 1998-07-16 甲府日本電気株式会社 ロックリクエスト制御装置
DE102007044803A1 (de) * 2007-09-20 2009-04-09 Robert Bosch Gmbh Schaltungsanordnung zur Signalaufnahme und -erzeugung sowie Verfahren zum Betreiben dieser Schaltungsanordnung

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58214957A (ja) * 1982-06-09 1983-12-14 Mitsubishi Electric Corp 計算機システム

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO8906011A1 *

Also Published As

Publication number Publication date
JPH02501780A (ja) 1990-06-14
WO1989006011A1 (fr) 1989-06-29

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