AU640754B2 - Interprocessor communication system - Google Patents

Description

COMMONW

PAT

COMPLE

S F Ref: 158777 FORM EALTH OF AUSTRALIA ENTS ACT 1952 ETE SPECIFICATION

(ORIGINAL)

FOR OFFICE USE: Class Int Class a. a.

*e a 0@ a a.

a **aa 00 *e 0 a Complete Specification Lodged: Accepted: Published: Priority: Related Art: Name and Address of Applicant: a 0* Oa a -ujitsu Limited 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi Kanagawa 211

JAPAN

Spruson Ferguson, Patent Attorneys Level 33 St Martins Tower, 31 Market Street Sydney, New South Wales, 2000, Australia Address for Service: a *a.

a Complete Specification for the invention entitled: Interprocessor Communication System The following statement is a full description of this invention, including the best method of performing it known to me/us 5845/3

ABSTRACT

When the data receiving side of an interprocessor communication control unit receives final data from the transmission side of anothe'r inter-processor communication control unit, the receiving unit transmits to the transmitting unit information indicating that all data have been 0 0 received. Thus, the transmitting unit transmits to a bus control unit information of a withdrawal of a use *e* 10 of a data communication bus. Then, after the receiving unit transfers to processors connected thereto all reception data accumulated therein, it transmits through the bus control unit or directly to the transmitting unit information indicating that o 0 15 data communication to the processor is finished.

*2* 0 0

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INTERPROCESSOR COMMUNICATION SYSTEM Background of the Invention Field of the Invention The present invention relates to an interprocessor communication system in a digital switching device or a multiprocessor system such as a data processing system.

Description of the Prior Art Recently, in digital switching devices and 10 data processing apparatuses such as computers, multiprocessor systems have been employed. In these sstems, a plurality of processors are interconnected by a shared bus or an input output channel to commonly use an input output unit or to simultaneously operate 15 the plurality of processors, thereby improving processing efficiency, reliability, system expandability and cost performance. These systems are used because, in digital switching devices, "improvement of processing efficiency and data transfer capability has become increasingly important as ISDNs (Integrated Service Digital Networks) have been more widely used.

In this multiprocessor system, as one method in which a communication is carried out among a plurality of processors, such communication method is 2 known, in which one communication bus is provided and a communication is performed among processors via one communication bus.

In this communication method, there is known such a method in which a processor at the transmitting side and a processor at the receiving side temporarily occupy the communication bus to perform data *communication between them.

Figure 1 is a schematic block diagram showing an arrangement of a multiprocessor system in which data communication is performed among processors 6 according to this method.

An inter-processor communication method utilizing this multiprocessor system is described o a 15 below.

Each processor 90 includes an IPC (inter- *a multiprocessor communication device) 91 and interconneced to a data communication bus 94. Each IPC 91 is composed of a talker unit 92 '-nd a listener 20 unit 93. Now, assume that data is transmitted from a processor 130-0 to a processor 90-1. The transmitting side processor is called a talker and the receiving side processor is called a listener.

The talker unit 92-0 of the IPC 91-0 receives transmission data from the processor 90-0 which is the 3 talker and transmits that transmission data to the data communication bus 94.

Then, a listener 93-I of an IPC 91-1 interconnected to the processor 90-1 receives this data and transmits it to the processor 90-1 which is the listener. The data transmission from the processor 90-0 to the processor 90-1 is thus completed. In this inter-processor communication, an IBC (Inter-Multiprocessor Bus Controller) 95 and sees 10 various kinds of signal lines are utilized. The iBC 95 performs the polling to each of the IPCs 91 so that it receives an occupation request of the data communication bus 94 from each IPC 91 and if possible gives an occupation right to the IPC 91. The signal 15 line may be a data order content transmission line 96 00ev interconnected to the data communication bus 94 to transmit an order which indicating the meaning of transmission and reception data, a polling number goal transmission line 97 through which a polling number is 0**b transmitted, a polling number synchronizing signal transmitting line 98 for transmitting a synchronizing signal containing the polling number, a communication bus using right transmission line 99 for transmitting a using right request of the data communication bus 94, and a communication bus use permission -4transmission line 100 for transmitting a communication bus use permission signal in response to the use right request through a communication bus using permission signal for the using right request is transmitted.

The inter-processor bus control unit IBC 95 is composed of a polling number generating unit 101 and a communication bus use permission unit 102. The polling number generating unit 101 sequentially too* 10 generates the numbers of respective IPCs to scan

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respective inter-processor communication unit IPCs 91 *by the polling, and the communication bus use permission unit 102 returns a signal indicating permission of use to the communication bus use 15 permission request sent from the talker unit 92 of the o. IPC 91 if the communication bus can be used.

The talker unit 92 within the IPC 91 is composed of a communication bus use request transmitting unit 103 and an IPC-IPC data communication control unit 104 0 20 which controls data communication between IPCs via the data communication bus 94. When the communication bus use request transmitting unit 103 receives the polling number transmitted from the IBC 95 via the polling number transmission line 97 and determines that this number is equal to the polling number of its own IPC, 5 it transmits the communication request signal to the IBC 95 via the communication bus use request transmission line 99. When the IPC-IPC data communication control unit 104 receives the use permission of the data communication bus 94 from the IBC 95, the IPC-IPC data communication control unit 104 inputs data transmitted from the processor 90-0 and transmits it to the data communication bus 94.

*Then, an order content indicating the kind of data transmitted is also transmitted to the data order *000 00 content transmission line 96.

0 The listener unit 93 within the IPC 91 see includes an IPC-IPC data communication control unit 105 which receives data from the data communication 5 bus 94 and which transmits it to the processor 15 Operation of this system is described next.

In the inter-processor bus control unit IBC the polling number generating unit 101 sequentially generates the polling numbers and 4 B transmits them to the polling number transmission line 20 97 and the polling number transmission synchronizing signal to the polling number synchronizing signal transmission line 98. The talker unit 92 in each IPC 91 receives the polling numbers sequentially transmitted through the polling number transmission 6 line 97 and the communication bus use request transmitting unit 103 determines whether or not the polling number is equal to the number of its own IPC.

If it is, and if there is a data transmission request, the communication bus use request is transmitted through the communication bus use request transmission line 99 to the IBC Now, assume that the IPC 91-0 has the data transmission request and that a communication request 106 is input to the communication bus use request :..*.transmission unit 103. Then, each time the polling number is transmitted to the communication bus use request transmitting unit 103 from the polling number transmission line 97, the communication bus use 15 request transmitting unit 103 compares the received 0,*9 polling number with the number of its own IPC. If they do not coincide, the communication bus use

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request transmitting unit 103 awaits the input of the next polling number. If they do coincide, the S20 communication bus use request transmitting unit 103 e• determines whether or not the communication request signal 106 is input. If it is not input to the communication bus use request transmitting unit 103, the communication bus use request transmitting unit 103 ends the transmission processing and awaits the 7 input of the next polling number. In that case, since the communication request signal 106 is input to the communication bus use request transmitting unit 103, this unit transmits the communication bus use request signal to the communication bus use request transmission line 99 to obtain the permission of the use of the data communication bus 94.

The communication bus use request signal a. a• *e output to the communication bus use request

SO*

transmission line 99 is received by the communication *s bus use permission unit 102 of the IBC 95 and, if the data communication bus 94 is vacant upon reception, the communication bus use permission unit 102 transmits the use permission signal to the 15 communication bus use permission transmission line *e v 100.

SS 0 *Subsequently, when the IPC-IPC data communication control unit 104 of the talker unit 92-0 in the IPC 91-0 receives the communication bus use ac Oo* 20 permission signal, the IPC-IPC data communication control unit 104 outputs the IPC number corresponding to the IPC 91-1, which becomes a listener, to the data communication bus 94 in order to designate a transmission destination listener). The IPC 91- 1 or the listener corresponding to the IPC number 8 transmits a signal indicating the receivable condition through the data communication bus 94 to a talker IPC91-0 if the talker IPC 91-1 is in a receivable condition. When receiving this signal, the IPC 91-0 transmits the transmission data to the IPC 91-1 via the data communication bus 94. Incidentally, transmission data is written beforehand in a buffer memory (not shown) within the IPC-IPC data communication control unit 104 by the processor 90-0.

'The data transmitted to the IPC 91-1 is received by the IPC-IPC data communication control unit 105 in listner unit 93-1 and transmitted to the processor 90-1. With this processing, the data communication from the processor 90-0 to the processor 15 90-1 is finished, and at the completion of the data 15 Scommunication, the data communication bus 94 utilized between the talker and the listener is released.

0* 05 Figure 2 is a diagram used to explain the operation of the above data communication. In Figure 2, the abscissa represents the position of each unit S" of the system, and the ordinate represents a time axis in which time is passed in the lower direction. The transmitting side, i.e. unit of a talker 110, is located on the left, the receiving side, i.e. unit of a listener 112, is located on the right and a 9 communication bus 111 is iocated between the talker 110 and the listener 112.

Incidentally, the communication bus 111 is an inclusive expression of the data communication bus 94, the data order content transmission line 96, the polling number transmission line 97, the polling number synchronizing signal transmission line 98, the communication bus use request transmission line 99 and *0 *e the communication bus use permission transmission line 100. Further, in the talker unit 100, the IPC 91-0 is connected to the communication bus 111 and the e* o processor 90-0 is connected to the IPC 91-0. Then,

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the processor 90-0 includes a memory 113-0.

Similarly, the IPC 91-1, the processor 90-1 and a main lot.: 15 memory unit 113-1 are provided on the listener unit 112 side. For convenience, the IBC 95 is provided within the communication bus 111.

Operation in which data stored in the main memory unit 113-0 of the processor 90-0 at the talker 20 110 side is transmitted through the communication bus 0 S" 111 to the listener unit 112.

The processor 90-0 on the talker unit 110 side transmits a DMAC (Direct Memory Access Control) data setting signal S1 for DMA transfer control data to the IPC 91-0. This signal comprises the address of the 10 main memory unit 113-0 in which transmission data is stored, the data storage address of the main memory unit 113-1 of the processor 90-1 on the listener 112 side, transmission data amount and command (write command and so on) or the like.

The processor 90-0 transmits the listener number setting signal S2 and a transmission order signal S3 which is the transmission command to the IPC 91-0 in order to set the number (IPC number) of the 10 listener 112 which transmits the signal to the IPC 91- 0. The IPC 91-0 then receives transmission order 0 signal S3 and is actuated.

The processor 90-0 transfers the transmission data from the main memory unit 113-0 to the buffer 15 memory within the IPC 91-0 in a DMA fashion.

When the processor 90-1 is set in the receivable condition, the listener 112 side transmits the DMAC data setting signal S5 to the IPC 91-1. As for the data setting signal S1, this DMAC data setting 20 signal S5 is composed of a memory address of the main memory unit 113-1 which stores reception data and a command. Subsequently, the processor 90-1 transmits the reception order signal S6 to the IPC 91-1 to actuate it. The processing associated with the 9g actuation of the IPC 91-1 of the listener 112 side is -11 carried out at the timing point in which the unit of the listener 112 is placed in the receivable condition.

In the talker unit 110 side, the IBC 95 is set in the standby mode until the same polling number as its own polling number is transmitted to the polling number transmission line. When this polling number is transmitted, the IPC 91-0 transmits the communication SO .0 bus use request S7 to the IBC 95. When receiving the communication bus use request S7, the IBC 95 returns the use permission signal S8 to the IPC 91-0 if the 04 communication bus 111 is set in the receivable Ok condition at that time. When the use permission is obtained, the occupation of the data communication bus 94 by the talker unit 110 is started.

Then, the IPC 91-0 outputs the listener designating number S9 set within the IPC 91-0 to the Be or data communication bus 94. The IPCs 91, which are all in the receivable condition, receive the listener toes Q20 designating number S9 and determine whether it S 20 coincides with their own designating numbers. If they do not, no processing is carried out. If they do, a reception preparation OK signal S10 indicating the receivable condition is transmitted through the data communication bus 94 to the IPC 91-1. Thus, when the 12 listener 112 of the listener designating number is not placed in the receivable condition, or when the abovementioned signals S5 and S6 are not transmitted from the processor 90-1 to the IPC 91-1, even if the listener designating signal S9 is transmitted, the reception preparation OK signal S10 is not returned from the IPC 91-1. When the signal S10 is not returned, the talker 110 determines that the listener 6 120 is not in the receivable condition, and stops the 10 data transmission.

On the other hand, when the reception preparation OK signal S10 is returned from the IPC 91- 1 on the listener 112 side to the IPC 91-0 on the talker side, the IPC 91-0 reads out transmission data from the buffer memory and transmits it through the data communication bus 94 to the IPC 91-1 (S11) in the burst mode. Then, the transmission data is temporarily stored in the buffer memory (not shown) within the IPC 91-1. When the transmission of data 20 from the IPC 91-0 at the talker 110 side to the IPC91- 1 of the listener 112 side is completed, the IPC 91-1 transfers the data stored in the inside buffer memory to the main memory unit 113-1 in a DMA fashion (S12).

When the data transfer to the main memory unit 113-1 is finished, the listner 112 side IPC 91-1 13 transmits an end answer signal S13 indicating that the data transfer is finished via the data communication bus 94 to the IPC 91-0 of the talker 110 side. When receiving the end answer signal S13, the IPC 91-0 confirms the end of the data communication and releases the data communication bus 94 from being occupied via the IBC 95. Then, the IPC 91-0 transmits data communication completion information S14 to the processor 90-0 and the IPC 90-1 transmits data communication completion information S15 to the *1 processor 90-1 thereby finishing the data

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communication processing.

In accordance with this system, the talker unit 110 occupies the data communication bus 94 during 15 the period T1 in which the IPC 91-0 on the talker 110 4 side receives the communication bus use permission a signal S8 transmitted from the IBC 95 and the IPC 91-0 on the talker 110 side receives the answer S13 indicating that the data transfer from the IPC 91-1 at the listener 112 side to the main memory unit 113-1 3 has ended.

In the conventional system, however, one processor occupies the data communication bus 94 for a longer period longer than necessary and there is then the substantial problem that throughput in the inter- 14 processor communication in the entire multiprocessor system is reduced. That is, as shown in Figure 2, the data communication bus 94 is utilized while the IPC 91-0 of the talker unit 110 side receives the communication bus use permission S8 from the IBC and the data transfer between the TPC 91-0 and the IPC *91-1 is finished (period T2). Therefore, while the data is being transferred from the IPC 91-1 at the listener 112 side to the main memory unit 113-1 of the S 10 processor 91-1 (period T3), the data communication bus i« 94 is not utilized. That is, for a period T3 in 00 *0 *c which the data communication bus is not yet utilized,

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the talker unit 110 and the listener unit 112 need not occupy the data communication bus 94.

Summary of the Invention "Accordingly, it is an object of the present a invention to provide an improved inter-processor communication system in which the aforenoted shortcomings and disadvantages of the prior art can be subitantially eliminated.

More specifically, it is an object of the present invention to provide an inter-processor communication system of a multiprocessor system in which a data communication bus is prevented from being occupied for a period longer than necessary to increase throughput of the inter-processor communication in the entire multiprocessor system.

That is, the present invention is based on an inter-processor communication system in a multiprocessor system comprising a plurality of processors, a data communication bus interconnected among the plurality of processors, a bus control unit Sg for controlling the using right of the data

S..

communication bus by the polling for transmitting the 10 polling number to a polling number line and an inter- 10 processor communication control unit connected to each :Dg of the plurality of processors and for controlling transmission and reception of data among the processors via the data communication bus.

04006: ni~~v~~it o(N\ jn oe aepgc_ i SThe 1 firt relates to the following inter-processor communication system. That is, when S.0.• S• receiving final data from the inter-processor communication control unit on the transmission side, ego S oan inter-processor communication control unit on the S 20 receiving side transmits an answer indicating the reception of the final data to the transmission side inter-processor communication control unit. When receiving the answer, the transmission side interprocessor communication control apparatus transmits the information for withdrawing the use of the data 16 communication bus to the bus control apparatus, and the bus control apparatus again starts polling in response to this information.

Further, after transferring all the received data stored in the inside to the processors interconnected thereto, the reception side inter-processor communication control unit transmits a completion answer indicating the completion of the data transfer to the bus control unit. Hhen receiving the completion answer, the bus control unit transmits completion information indicating the completion of the data communication among the processors to the transmission side inter-processor communication control unit.

As described above, in the inter-processor data communication system, when the inter-processor control unit on the receiving side receives all the data in its own buffer memory or the like, this reception side inter-processor control unit transmits the completion answer indicating the reception of all data to the transmission side inter-processor communication control unit. In response to this :information, the transmission side inter-processor communication control unit immediately transmits the information indicating the withdrawal of the use of the data communication bus to the bus control unit so that, when data transfer among the inter-processor 4 )/266K 17 communication control units is completed, the data communication bus is immediately released to another processor. Accordingly, compared with the prior art, the occupation time of the data communication bus in the inter-processor data communication can be reduced. Further, after transferring all received data to the processors interconnected thereto, the reception side inter-processor communication control unit transmits the completion answer to the bus control unit and the bus control unit transmits the completion information indicating the completion of the data transfer to the processors. Thus, the transmission side processor can know the completion of the data transfer via the inter-processor communication control unit connected thereto.

The invention, in a second aspect, relates to the following inter-processor communication system. When receiving final data from the transmission side inter-processor control unit, the reception .ide inter-processor communication control unit transmits an answer indicating of the reception of the final data to the transmission side 1 inter-processor communication control unit. When receiving the answer, Sa:the transmission side inter-processor communication control unit 20 transmits information of the withdrawal of the use of the data communication bus to the bus h control unit. In response, the bus control unit again starts polling.

Further, after transferring all received data stored inside to the processors interconnected thereto, the reception side inter-processor communication control apparatus transmits the completion answer indicating the completion of the data transfer to the bus control unit and to the transmission side inter-processor communication control unit.

As described above when data transfer between the inter-processor communication control unit is finished, the data transmission sidq inter-processor control unit transmits the information of the withdrawal of the use request of the data communication bus to the bus control unit so that the occupation time of the data communication bus in the inter-processor data communication can be reduced. Further, since the reception side inter-processor communication control unit directly transmits the completion answer to the transmission side inter-processor communication control unit and not via the bus control unit, the completion of the inter-processor data communication can be *known earlier.

Brief Description of the Drawings a R1 $~FD/266K 0 *m~e *ft e 'aDaG -19- A better understanding of other objects, features and advantages of the present invention will be gained from the following illustrative embodiments thereof to be read in conjunction with the accompanying drawings, in which: Figure 1 is a block diagram showing an arrangement of a conventional multiprocessor system; 0* *S Figure 2 is a schematic diagram used to explain the operation of an inter-processor data oo 10 communication of the conventional multiprocessor *system; Figure 3 is a block diagram showing the system arrangement of a digital switchboard having a multiprocessor configuration according to the first 9 t 15 embodiment of the present invention; Figure 4 is a block diagram showing more fully 0 a talker unit and a listener unit in an IBC and an IPC according to the first embodiment of the present .099 invention; 0S Figure 5 is a diagram for explaining the operation of the call processing inter-processor data communication of the first embodiment; Figure 6 is a schematic diagram showing the main portion of a digital switchboard system according to the second embodiment of the present invention; 20 Figure 7 is a circuit block diagram showing in more detail the main portions of the IBC and IPC according to the second embodiment of the present invention; Figure 8 is a diagram for explaining the polling sequence when no communication request is issued from the talker unit of the IPC in the second S embodiment of the present invention; Figure 9 is a schematic diagram for 10 explaining the inter-processor data communication operation of the second embodiment of the present invention; and Figure 10 is a diagram for explaining the operation flow of the call processing inter-procesor data communication in the second embodiment of the present invention.

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Detailed Description of the Preferred Embodiments The preferred embodiments of the present 3 invention are described with reference to the accompanying drawings.

Figure 3 shows the system arrangement of the first embodiment of the present invention. This embodiment relates to an inter-processor communication of a multiprocessor system arrangement in a digital oe switchboard.

21 The digital switchboard in this embodiment is composed of a management processor MPR 21 for managing the entire system of the digital switchboard and a plurality of call processors CPR 22-i (i 0, 1, 2, n) for processing respective calls. That is, the plurality of CPRs 22-i are provided to decentralize function and load.

The MPR 21 and the plurality of CPRs 22-i are all connected through inter-multiprocessor 10. communications (IPCs) 2-i to a data communication bus 3. Each of the CPRs 22-i performs data communication a between other CPRs and MPRs via the IPCs 2-i. Further, an inter-processor bus control unit IBC4 is provided to control or determine by performing the polling which of processors MPR 21 and CPRs 22-i occupy the 15 data communication bus 3. The inside arrangements of S' the MPR 21 and the CPRs 22-i are similar.

As shown in Figure 3, the MPR 21 and the CPRs *00* 22-i comprise a processor bus Pbus 25 (25-i or e S' 20 which is the inside bus of the processor, a central controller CC 23 (23-i or 23-M) connected to the processor bus Pbus 25 and a main memory MM 24 (24-i or 24-M). Further, the inter-processor communication control unit IPC 25 is connected to the processor bus Pbus 22 Each inter-processor communication control unit IPC 2 is connected to the data communication bus 3, and used as an interface for executing the interprocessor data communication via the data communication bus 3. IPC numbers necessary for the IBC 4 to perform the polling are allocated to the respective IPCs 2, and these IPC numbers are utilized S* as the polling numbers, described later.

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Next, operation of the inter-processor data a o 10 communication in the first embodiment of this a ft arrangement is described with reference to the case that data is transmitted from CPR 22-0 to CPR 22-1.

The following description is based on the assumption that transmission data is stored beforehand in a main 15 memory unit (hereinafter simply referred to as MM) 24- 0 within the CPR 22-0.

Initially, the control CC 23-0 of the CPR 22-0 transmits a data transmission request to the interprocessor communication control unit IPC 2-0 and, in S" 20 response to this request, the IPC 2-0 transmits the use permission request of the data communication bus 3 to the inter-processor bus control unit IBC 4.

When receiving this use permission request, if the data communication bus 3 is vacant at that time, or if it is not in use, the IBC 4 transmits the use 23 permission to its IPC When supplied with the use permission of the data communication bus 3 from the IBC 4, the IPC receives from the CC 23-0 the IPC number of the IPC 2 of the transmission destination CPR 22-1 and transmits it to the data communication bus 3 to thereby designate the reception destination. The IPC 2 (2-1) within the CPR 22-1 which is the reception destination receives the designation signal from the data 10 communication bus 3, and if the CPR 22-1 is in the receivable condition, the IPC 2 returns a reception preparation completion signal to the IPC via the data communication bus 3. The IPC receives this reception preparation completion signal c. 15 and starts the transmission of data.

Next, the data transmission operation is S• described.

IPC 2-0 reads out transmission data from the main memory 24-0 of the CPR 22-0 via the PBbus 25-0, temporarily stores the read-out transmission data in its buffer memory and transmits this data to the data communication bus 3. IPC 2-1 connected to the CPR 22- 1 which is on the data receiving side receives the communication data via the data communication bus 3, sequentially stores it in its buffer memory and 24 determines whether or not the transmission data is correct each time it receives one predetermined unit of concrete data. Then, IPC 2-1 transmits to IPC via the data communication bus 3 an answer signal of the judged result indicating whether or not the transmission data is received correctly.

After IPC 2-0 transmits the final data to the data communication bus 3, and IPC 2-1 receives the 55 transmission data via the data communication bus 3, 4*

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10 IPC 2-I transmits the answer to IPC 2-0 via the data 10 communication bus 3. When IPC 2-0 receives this answer, the data communication from CPR 22-0 to CPR 22-1 is finished. Then, IPC 2-0 transmits the IBC 4 a signal indicating that the use permission of the data 15 communication bus 3 is abandoned. When detecting that ICP 2-0 has abandoned the use right of the data communication bus 3, the IBC 4 starts again the polling in order to transmit the use right of the data communication bus 3 to another processor which transmits the use permission request of the data communication bus 3. That is, when the data transfer from CPR 22-0 to CPR 22-1 is completed, the data communication bus 3 is released.

IPC 2-1, which receives the data as described above, transfers the reception data stored in the 25 inside buffer memory to the main memory unit ?4-1 of CPR 22-1 via the Pbus 25-1 in a DMA transfer fashion.

When this transfer is ended normally, the data communication from CPR 22-0 to CPR 22-1 is substantially completed. When the data transfer to the main memory unit 24-1 of processor CPR 22-1 is completed, IPC 2-1 sends the end answer to the IBC 4.

In response to this end answer, the IBC 4 transmits the IPC number of IPC 2-0 (end talker number) to S 10 sending IPC 2-0 as the end information. The IPC determines that the transmitted end talker number is a..

equal to its own IPC number, confirms the completion of the data communication, executes a predetermined communication completion processing and is set in the a 15 standby mode for the next communication.

Figure 4 is a block diagram showing the "circuit arrangement of the IBC 4, IPC 2-0 and IPC 2-1 shown in Figure 3 in more detail.

As shown in Figure 4, each IPC 2 is composed 20 of a talker unit 30 and a listener unit 31. In Figure 4, for simplicity, IPC 2-0 is represented as the talker side and IPC 2-1 is represented as the listener side. Also, only the talker unit 30 is illustrated for IPC 2-0 and only the listener unit 31 is illustrated for IPC 2-1. Further, as shown in Figure 26 3, IPC 2-0 is connected to a processor 24-0 composed of CC23-0 and MM 24-0 via the P-bus 25-0 and IPC 2-1 is connected to a processor 24-1 composed of CC23-1 and MM24-1 via the P-bus 25-1.

The talker unit 30 comprises a data transmitting circuit 40, a data answer decoding circuit 41, a final answer detecting circuit 42, a communication bus use go request circuit 43, and an end information receiving circuit 44. The data transmitting circuit 10 transmits data to the data communication bus 3. The data answer decoding circuit 41 decodes an answer transmitted from the listener unit 31 which sends the data through the data communication bus 3 each time reception of one unit of data is completed. The final a 15 answer detecting circuit 42 detects the final answer from answers decoded by the data answer decoding 4* circuit 41. The communication bus use request circuit 43 receives the polling number from the IBC 4 through .4 9 the polling number line L3 and determines whether or 20 not the received polling number coincides with its own polling number and, if they coincide, transmits a bus use request through the communication bus use request line L7 to the IBC 4. The end information receiving circuit 44 receives the end talker number transmitted from the IBC 4 through the polling number line L3 and 27 determines whether or not the end talker number coincides with its own IPC number and, if they coincide, performs the end interrupt to CC 23-0 of the processor CPR 22-0.

The listener unit 31 of IPC 2-1 comprises a data receiving circuit 45, a data order content decoding circuit 46, a listner designating circuit 48, an IPC-interprocessor communication control circuit 47, and an end information circuit 49. The data

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a 10 receiving circuit 45 receives data via the data communication bus 1. The data order content decoding a circuit 46 receives and decodes an order content signal indicating the content of data transmitted from the talker unit 30 via the data order content

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15 information line L2. The listener designating circuit 48 determine s whether or not this data and its own B a data coincide when the content of data is decodtc, as the listener designating data by the data order content decoding circuit 46 and, when they coincide, 20 designates itself as the listener. The IPC interprocessor communication control circuit 47 transmits a data transfer request to the processor CPR 22-1 when the data is decoded as the final data by the order content decoding circuit 46 to thereby control the communication between the IPC2-1 and the processor 28 22-1. The end information circuit 49 receives from the IPC interprocessor communication control circuit 47 information indicating that the transmission of all received data to the MM 24-1 of the processor CPR 22-1 has ended and transmits the end answer to the polling number line L3 at its arbitrary line designated by the IBC 4.

I* The IBC 4 comprises a polling number generating circuit 32, a communication bus use 10 permission circuit 33, an end information line designating circuit 34, an end talker number memory circuit 35, an end answer receiving circuit 36, a polling number transmitting gate circuit 37, an end talker number transmitting gate circuit 38, and an end 15 answer receiving gate circuit 39. The polling number 0 generating circuit 32 generates a polling number. The Scommunication bus use permission circuit 33 gives a use right of the data communication bus LI to the o*0 talker unit 30 of the IPC 2-0 within the data 20 transmission side processor CPR 21-0. The information line designating circuit 34 designates an arbitrary communication line in the polling line L3 used when the listener unit 31 of the data reception side IPC 2-1 transmits the end answer to the IBC 4 at the completion of the data transfer to the MM 24-1 29 within the processor 22-1. The end talker number memory circuit 35 stores the IPC number of the data transmission side IPC 2-0 as the end talker number.

The end answer receiving circuit 36 receives the end answer transmitted from the listener unit 31 of IPC 2- 1 on the receiving side CPR 22-1. The polling number transmitting gate circuit 37 outputs the polling :Og ha number to the polling number line L3. The end talker number transmitting gate circuit 38 outputs the end 10 talker number output from the end talker number memory 0* US circuit 35 to the polling number line L3. The end S* answer receiving gate circuit 39 receives the end answer transmitted from the listener unit 31 of the IPC 2-1 through the polling number line L3 and 15 transmits it to the end answer receiving circuit 36.

Communication lines utilized in the IBC 4 and s in the talker unit 30 and the listener unit 31 of the IPCs 2-0 and 2-1 are described next. A data 0"06 communication bus Li is connected to each IPC 2 in go 20 order to transmit data to the listener unit 31 from the talker unit 30. This data communication bus Li can be changed in response to the system arrangement and is formed of a bus of, for example, 8-bit width.

A data order content answer line L2 is provided to connect the talker unit 30 and the listener unit 31 of 30 each IPC in order to transmit the order content (kind) of data transmitted on the data communication bus Li from the talker unit 30 of each IPC 2 to the listener unit 31.

Communication lines utilized in the control of the data communication bus Li or the like may comprise a polling number line L3, a polling number line use mode control line L4, a polling number synchronizing a line L5, an end talker number synchronizing line L6, a 10 communication bus use request line L7, a communication 0* 00 bus use permission line L8, an end information line

B.

i designating line L9 and a listner designating receiving line L10. The polling number line L3 is formed of a plurality of communication lines for 15 transmitting the polling numbers to respective .[PCs 2 0o from the IBC 4. The polling number line use mode *control line L4 connects the IBC 4 and the respective IPCs 2 necessary to transmit a polling number line use mode signal S30 needed to determine whether or not 20 the IBC 4 has transmitted the end talker number to the polling number line L3, whether or not the polling number has been transmitted and whether or not the listener unit 31 has transmitted the end answer to the IBC 4. The polling number synchronizing line connects the IBC 4 and each IPC 2 used to transmit the 31 polling number synchronizing signal S3 necessary for each IPC 2 to correctly receive the polling number of the IBC 4 to each IPC 2. The end talker number synchronizing line L6 connects the IBC 4 and the talker unit 30 of each IPC2 and is utilized to transmit to each IPC 2 a synchronizing pulse required by each ICP 2 to correctly recei final talker number output from the IBC 4. Th cc .,nunication bus use request line L7 connects each ICP 2 and the IBC 4 4.

1 and is utilized by the talker unit 30 of each IPC to transmit the use right request signal of the data communication bus 3 to the IBC 4. The communication bus use permission line L8 connects the IBC 4 and the talker unit 30 of each IPC 2 and is utilized by the 15 IBC 4 to transmit the use permission of the communication bus to the talker unit 30 of each IPC 2.

The end information line designating line L9 connects the IBC 4 and the listener unit 31 of each IPC 2 and o. is utilized by the IBC 4 to designate the information 20 line of the end answer information to the listener unit 31 of each IPC 2. The listener designation receiving line L10 connects the listener unit 31 of each IPC 2 and the IBC 4 and is utilized by the talker unit 30 of each IPC 2 to transmit to the IBC 4 information indicating that the listener unit 31 of 32 other IPC 2 designated by the talker unit 30 of each IPC 2 is designated.

The data transmission operation from the processor CPR 22-0 to the processor CPR 22-1 in the first embodiment of this system is described with reference to the operation flowchart of Figure Assume that a data transmission request is issued from the processor CPR 22-0 to the processor 22-1.

10 The processor CPR 22-0 transmits through the Pbus 25-0 to the talker unit 30 of the IPC 2-0 DMAC data setting data S41 which is the information necessary to transfer the transmission data to the buffer memory within the talker unit 30 in a DMA 0 15 fashion. This DMAC data setting information S41 might Sbe transfer amount data, read memory address of transfer data, the kind of data, and so on.

Further, the processor CPR 22-0 transmits a listener number designating information S42 through

C

20 the Pbus 25-0 to the IPC 2-0 in order to transmit the transmission destination, i.e. listener number, to the IPC 2-0. Subsequently, transmission order information S43 is transmitted from the processor CPR 22-0 to the IPC 2-0 to activate the talker unit 30 of the Then, the IPC 2-0 reads out the transmission data 33 stored in the main memory unit MM 24-0 and transfers the transmission data 512 words) of the IPC to the buffer memory within the talker unit 30 in a DMA fashion (S44).

Incidentally, in the IBC 4, a polling number signal S45 is generated by the polling number generating circuit 32, and the polling number signal to S. $45 is synchronized with the polling synchronizing *Q S signal S31 and transmitted through the gate circuit 37 10 to the polling number line L3. At that time, the z polling number generating circuit 32 simultaneously

S

S..transmits the polling number line use mode signal and the polling number synchronizing signal S31 to the polling number use mode control line L4 and the 15 polling number synchronizing line L5. In this case, S" the use mode signal S30 indicates the polling number "transmission mode.

The polling number S45 transmitted to the polling number line L3 is received by the w as.

20 communication bus use request circuit 43 within the as talker unit 30 of each IPC 2-0 which determines whether or not the polling number coincides with its IPC number. If they do, the communication bus use request circuit 43 transmits the use request signal, which requests the use of the data communication bus 34 L1, that is, the polling inhibit request S46 which inhibits the subsequent polling of the IBC 4 to the communication bus use reqaest line L7.

When receiving the polling inhibit request S46, the communication bus use permitting circuit 33 of the IBC 4 transmits, if the data communication bus L1 is vacant, the use permission S47 of the data b communication bus Li through the communication bus use c permission line L8 to the talker unit 30 of the IPC 2k 10 0 which transmits the polling inhibit request S46.

0U *When receiving the use permission signal S47 @06 of the data communication bus Li from the data communication use permission line L8, the data transmitting circuit 40 of the talker unit 30 of each 15 IPC 2-0 designates the listener unit by utilizing the o 0 data communication bus Li. The listener unit is V. St designated such that the data transmitting circuit transmits the IPC number S48 of the IPC 2-1, which is designated as the listener, to the data communication bus L'I and transmits to the data order content information line L2 a signal indicating that the signal output to the data communication bus Li is the listener designating data.

The data order content decoding circuit 46 within the listener unit 31 of each IPC receives this 35 signal from the data order content information line L2 and decodes its data content. Then, the circuit 46 determines that the data is the listener designating data and activates the listener designating circuit 48. When activated, the listener designating circuit 48 receives the listener designating number S48 from the data communication bus Li and determines whether or not the listener designating number S48 coincides 9 with its IPC number. If they do, the listener r S' 10 designating circuit 48 transmits reception preparation S" OK signals S49 and S50 through the data receiving *3 :S circuit 45 if the data reception is already prepared.

Then, the reception preparation OK signal S49 is transmitted from the data receiving circuit 45 of the 15 IPC 2-1 through the data communication bus LI to the

C*

data answer decoding circuit 41. When receiving the reception preparation OK signal S49, the talker unit of the IPC 2-0 determines that the data transmission to the listener unit 31 of the IPC 2-1 is 20 possible. The reception preparation OK signal S50 is transmitted from the data receiving circuit 45 to the listener designation receiving line L10 and received by the end information line designating circuit 34 of the IBC 4.

When receiving the receiving preparation OK 36 signal S49, the talker unit '0 of the IPC transmits transmission data S52 accumulated in the inside buffer memory through the data transmitting circuit 40 to the data communication bus L1. At the same time, the data transmitting circuit 40 transmits a signal indicating that the content of data is the transmission data to the data oider content information line L2. The data order content decoding circuit 46 of the listener unit 31 of the IPC 2-1 S 10 decodes the signal transmitted via the data order 0e content information line L2. If the decoding circuit 46 determines that the signal is the transmission data, the decoding circuit 46 activates the data receiving circuit 45, and transmission data S52 transmitted through the data communication bus Li is &*sees 15 received by the data receiving circuit 45. The data receiving circuit 45 stores received data in the buffer memory provided within the listener unit 31.

Each time the data receiving circuit 20 receives transmission data of a predetermined unit, it e. transmits an answer S53 indicating that data has been received correctly by the data communication bus L This answer S53 is received by the data answer decoding circuit 41 of the talker unit 30 of the IPC 2-0 and decoded by the data answer decoding circuit 37 41. If the data answer decoding circuit 41 determines that the data is correctly received, the data transmitting circuit 40 continues the transmission of data.

As described earlier, the reception preparation OK signal S50 to the IBC 4 is received by the end information line designating circuit 34 within the IBC 4 via the listener designating signal line L10. When the end information line designating 0'o 10 circuit 34 receives the reception preparation OK signal S50, at a timing point in which the CPR 22-0 completes the data transmission to the CPR 22-1, the listener unit 31 of the IPC 2-1 transmits to the IBC 4 an end answer S55, to be described later, and 15 transmits an end answer line designating information S51 which designates an arbitrary information line within the polling number line L3 to the end information line designating line L9. The end answer line designating information S51 is received by the 20 end information circuit 49 of the listener unit 31 of the IPC 2-1 and the listener unit 31 of the IPC 2-1 holds therein the end answer line designating information S51.

When receiving the reception preparation OK signal, the end information line designating circuit 38 34 activates the end talker number memory circuit to store the IPC number of the IPC 2-0, which is the transmission side talker, as the end talker number.

Then, the data transmission from the talker unit 30 of the IPC2-0 to the listener unit 31 of the IPC 2-1 is continued and the final transmission data is transmitted from the data transmitting circuit 40 of the talker unit 30 of the IPC 2-0 to the data communication bus L1. Then, when the data receiving 10 circuit 45 of the listener unit 31 of the IPC 2-1 receives such final transmission data, the data receiving circuit 45 transmits the answer to the data communication bus L1. When receiving the answer, the data answer decoding circuit 41 of the talker unit 15 of the IPC 2-0 transmits the answer 53 to the final answer detecting circuit 42. When detecting that the 66 answer indicates the completion of the data transmission, the final answer detecting circuit 42 withdraws the polling inhibit request, which is the 20 communication bus using request signal S46, via the communication bus using request circuit 43. The IBC 4 then detects the change of the signal on the communication bus use request line L7 by the communication bus use permission circuit 33, and again starts the polling interrupted by the polling inhibit 39 request S46 by the polling number generating circuit 32. Since the polling is started again, other processor MPR21 and CPR22 can use the data communication bus L1.

After transmitting the final answer to the talker unit 30 of the IPC 2-0, the listener unit 31 of the IPC 2-1 executes the transfer of data received from the talker unit 30 of the IPC 2-0 to the main memory unit 24-1 of the processor CPR 22-1. That is, 10 the IPC-interprocessor communication control circuit co" 47 within the listener unit 31 of IPC-2 transfers Sreception data stored in the buffer memory to the main memory unit 24-1 of the processor CPR 22-1 in a DMA fashion (S54). Then, when all received data are S 15 transferred to the main memory unit 24-1 of the processor CPR 22-1, the completion information circuit 49 within the listener unit 31 of the IPC 2-1 e transmits the completion answer S55 to the corresponding communication line of the polling number 20 line L3 with reference to the completion information line data held therein. After the completion information circuit 49 transmits the completion answer to the polling num' 1 line L3, the completion information circuit 49 transmits a completion information interrupt signal S58 which indicates that I! 40 the transmission of all data to the processor CPR 22- 1 connected to the IPC 2-1 via the Pbus 25-1 is completed.

Further, the completion answer S55 transmitted from the listener unit 31 of the IPC 2-1 is received by the completion answer receiving gate circuit 36 within the IBC 4 via the completion answer receiving gate circuit 39. That is, when the polling number 0 line use mode control line L4 is at low level 10 the IBC 4 interrupts the polling) by the gate .o circuit 39, the completion answer signal S55 is 6 06 received by the completion answer receiving circuit 36 of the IBC 4.

When the completion answer receiving circuit 36 receives the completion answer S55, the completion 0 talker number memory circuit 35 outputs the completion talker number synchronizing signal S56 to the completion talker number synchronizing line L6 and also transmits the completion talker number S57 20 via the completion talker number transmitting gate circuit 38 to the polling number line L3.

The completion talker number signal S57 transmitted to the polling number line L3 is received by the completion information receiving circuit 44 provided within the talker unit 30 of the IPC 41 The completion information receiving circuit 44 determines whether or not the number indicated by the completion talker number signal S57 and its own IPC number coincide. If they do, the circuit 4, recognizes that the executed data communication is completely ended, and transmits a completion information interrupt signal S59 to the processor CPR 22-0 connected to the IPC 2-0, whereby the data communication between the processor CPR22-0 and the 10 processor 22-1 is completed.

The second embodiment of the present invention

S

Sis described next.

Figure 6 is a schematic diagram showing the arrangement of the entire system of the second 15 embodiment. In Figure 6, reference numerals IPC 50-0, IPC 50-n denote inter-processor communication units similar to the IPC 2 of the first embodiment, and IBC 40 denotes an inter-processor bus control unit similar to the IBC 4 of the first embodiment. Though see* 20 not shown, IPC 51 is connected to the management *g g processor MPR, and IPC 50-0 to IPC 50-n designate IPCs connected to the call processor CPR.

Communication lines for connecting the IBC and the respective IPCs 51 and 50-0 through comprise a polling number line use mode control line 42 L14, a polling number line LB formed of four communication lines, a polling number synchronizing line L15, a communication bus use request line L17, a communication bus use permission line L18 and a listener designation receiving line Further, respective IPCs are interconnected via the data communication bus L11, the communication bus synchronizing line L21 and the data order content information line L12. A polling number line use mode 10 control signal SEL is output from the IBC 40 via communication line L14 to respective IPCs 52 via 5.

S

communication line L14, polling numbers PNO to PN3 or a completion answer line designation is output from the IBC 40 to the respective IPCs 51 and 52 via the 15 communication line L3, and the completion answer is output from the listener units of the respective IPCs 52 to the talker units of other IPCs 52 and the IBC 5 40. Further, the polling synchronizing signal SYNC is output from the IBC 40 to the respective IPCs 52 via 20 the communication line L15, and a communication bus .I request signal PINH is output from the talker units of the respective IPCs 52 via the communication line L17.

Further, transmission and reception data between respective IPCs 52 and an answer to the reception data or the like are transmitted and 43 received via the data communication bus L11 of 8 bit wide. Also, a data output synchronizing pulse is output from each IPC 52 to the data communication line L21 on the data communication bus L11, and data order content signals TODO,1 of 2 bits indicating the content of data output on the data communication bus L11 are output to the communication line L12.

Furthermore, listener designation reception OK signals TANSO,1 are output from the listener unit of each IPC 10 52 to the talker unit of the transmitting side (talker) IPC 52 and the IBC 40 via the communication line S" Figure 7 is a block circuit diagram of a main portion of the IBC 40 and the IPC 52 relating to the present invention.

As shown in Figure 7, a polling number generating circuit 132 within the IBC 40 includes a 4-

S.

bit polling counter 151 which generates a polling number. The polling number is output through polling 20 number output gate 137 to a polling number line L13 (PNO to 3) when the polling number line use mode control signal SEL is at high level. The polling number output gate 137 is supplied with an output of the polling counter 151 and is also supplied with an output of an AND circuit 152.

44 The AND circuit 152 is supplied with the polling number line use mode control signal SEL (communication line L4) and an inverted communication bus use permission signal TOK (communication line L8).

More specifically, the polling number output from the polling counter 151 is output through the polling number output gate 137 to the polling number lines PNO to PN3 when SEL H and TOK (the use of data communication bus L11 is not yet permitted).

10 A completion information line designating circuit 134 is composed of a completion information *0 line managing circuit 153 for managing information of polling number lines PNO to PN3 utilized by the listener unit of the IPC 52 to transmit the completion :5 information, a completion information line designating 0 40, encoder 154, a completion answer line designating output gate 155 and an AND circuit 156.

*a OS The completion information line designating encoder 154 encodes the information of the polling 0 20 number line utilized in the completion information and o" stored ir the completion information line managing circuit 153 to output the encoded output to the completion answer line designating output gate 155.

This output gate 155 is supplied at the other input terminal with an output of the AND circuit 156 and the 45 output therefrom is input to polling number lines PNO to PN3 as in polling number output gate 131. The AND circuit 156 is supplied with the polling number line use mode control signal SEL (signal on the polling number line use mode control line L14) and the communication bus use permission signal TOK (signal on the communication bus use permission line L18). In other words, the completion information line 0 "designating information resulting from the encoding 10 of the output of the completion information line managing circuit 153 by the completion information 0* @0 S S line encoder 154, is output through the output answer eoo line designating output gate 155 to the polling number lines PNO to PN3 when SEL and TOK (the use of the data communication bus L11 is already permitted).

Further, a completion answer receiving circuit 00 *w 136 within the IBC 40 is comprised of a 4-bit register 157 for designating the IBC completion answer and a *ago 20 delay element 158. The delay element 158 is supplied 0. with the polling number line use mode control signal SEL (signal on the control line L14) and supplies a counter pulse CP to the register 157. The register 157 is connected to polling number lines PNO to PN3 and is supplied with an output of the completion 46 answer input gate 139 through which passes data of polling number lines PNO to PN3 when the above control signal SEL goes to level. The register 157 latches the input from the completion answer input gate 139 at the leading edge of the counter pulse cp and outputs it to the completion information line managing circuit 153.

The circuit arrangement of the IPC 52 relating to the main portion of the present invention is o 10 described below.

The communication bus use request circuit 143 within the talker unit of the IPC 152 is comprised of a polling number collating circuit 159, a polling latch flip-flop 160 and a 3-input AND circuit 161.

The polling number collating circuit 159 is supplied with polling number lines PNO to PN3 through a PNO to PN3 receiving gate 162, and the polling number 0 collating circuit 159 determines whether or not the polling number input thereto through the PNO to PN3 20 receiving gate 162 and its own number coincide. If S* they do, the polling number collating circuit 159 outputs the level signal to the input terminal D of the polling latch flip-flop 160.

The polling latch flip-flop 160 can be formed of a D-F.F (delay-type flip-flop) and is supplied at 47 its counter pulse input terminal CP with the output of the 3-input NAND circuit 161.

The inputs of the NAND circuit 161 are three negative logic inputs of the bus request signal S64 from a talker control unit (not shown), the polling number synchronizing signal PSYNC (signal on the polling number synchronizing line L15) and the communication bus use permission signal TOK (signal on the communication bus use permission line L18). The 10 bus request signal S64 goes high level when the data communication request is output from the talker 88 *8 unit, and the PSYNC is the synchronizing signal and cyclically repeats "high level" and "low level".

Further, the TOK signal goes to level when the communication bus use permission is not obtained.

S When the polling number collating circuit 159 go determines that the polling number coincides with its •8 own number and makes its output from level to "L" level, at the timing in which the PSYNC goes from "H" 20 level to level, the output of the polling latch flip-flop 160 rises from level to level and becomes the communication bus use request signal PZNH which is transmitted to the IBC The completion information circuit 149 in the listener unit of each IPC 52 is composed of a listener 48 completion answer line designation register 163, a delay-type flip-flop 165, a 3-input NAND circuit 164, an AND circuit 166 and a transmission gate 167 for the polling number lines PNO to PN3.

The listener completion answer line designation register 163 is a 4-bit register and its inputs are data of the polling number lines PNO to PN3 input via the PNO to PN3 receiving gate 162. Further, the register 163 is supplied at its counter pulse 10 input terminal CP with the output of the 3-input NAND circuit 164. The 3-input NAND circuit 164 is supplied with the polling number line synchronizing signal PSYNC (signal on the polling number synchronizing line the communication bus use permission signal TOK (signal on the communication bus use permission line L18) and a reception OK status signal S67 from the listener control unit. That is, at the timing in which the PSYNC changes from level to level when the TOK is at level and the reception OK 20 status signal S67 is at level, the counter pulse is applied to the listener completion answer line designation register 163 and the completion answer line designation data is input to the register 163 as input data. The output of the register 163 is input to the PNO to PN3 transmission gate 167.

49 The delay-type flip-flop 165 is supplied with the polling number line use mode control signal SEL (signal on the polling number line use ihlode control line L14) as the counter pulse and is also supplied at its D input terminal with the completion answer condition signal S68 from the listener control unit.

This signal goes to level when the flip-flop 165 can be placed in a condition such that it can transmit

B.

the completion answer. Thus, whereby the output of 10 the flip-flop 165 goes to level at the timing in S

B

which the above-mentioned control signal SEL changes S. 'from level to level. The output of the flipflop 165 is output to the listener control unit as a reset signal for resetting the completion answer.

15 Further, the output of the flip-flop 165 is output to the AND circuit 166, which is supplied at the other input terminal thereof with a negative logic input of

B

the control signal SEL. That is, the AND circuit 166 outputs the "H"-level signal to PNO to PN3 20 transmission gate 167 when the control signal SEL is *8 at level. Accordingly, when the output of the AND circuit 166 is at level, the completion answer is output to polling number lines PNO to PN3.

Finally, the circuit arrangement of the completion information receiving circuit 144 provided 50 within the talker unit of the IPC 52 is described below.

The completion information receiving circuit 144 is composed of a talker completion answer line designation register 168, a 3-input NAND circuit 169, a completion answer collating circuit 170, a completion answer latch flip-flop 171 and a delay element 172.

s* 10 Data of the polling number lines PNO to PN3 input via the PNO to PN3 receiving gate 162 are input Sdata of the talker completion answer line designating register 168. This register 168 is of the 4-bit register and is supplied at its counter pulse terminal CP with the. output of the 3-input NAND circuit 169.

a .This NAND circuit 169 is supplied with the polling

S**

number synchronizing signal PSYNC, the reception OK S* signal TANS and the transmission OK status signal from the talker control unit. In the talker completion 20 answer line designation register 168, the completion information line designating data from the completion information line designating circuit 134 of the IBC is stored via the PNO to PN3 receiving gate 162 at the same time as the PSYNC changes from level to "H" level when TANS is at level and the receiving status signal is at level.

51 The completion answer collating circuit 170 is supplied at one input terminal with the output of the register 168 and is also supplied at the other input terminal thereof with data of the polling number lines PNO to PN3 via the PNO to PN3 receiving gate 162.

This data is the talker number which the talker number memory circuit 135 of the IBC 40 outputs to the polling number lines PNO to PN3. Then, the completion mW answer collating circuit 170 collates this talker 10 number with the number stored in the talker completion o answer designation register 168. If they do, the Lb 4 completion answer collating circuit 170 outputs the Lb "H"-level signal to the D input terminal of the completion answer latch flip-flop 171. This flip-flop 171 is supplied at its counter pulse terminal CP with the control signal SEL via the delay element 172.

This flip-flop 171 transmits the completion answer signal to the talker control unit when the completion answer collating circuit 170 detects the completion talker number transmitted from the IBC 40 and supplies B the "H"-level output to the input terminal D.

Operation of the second embodiment having this circuit arrangement is now described. Figure 8 is a schematic diagram showing the polling sequence of the Mi IBC 40 when the talker unit of each IPC 52 issues no 52 communication bus use request.

The mode in which a communication request is not issued from the talker unit of each IPC 52 might be a mode (polling mode) in which a new communication request is detected by the polling number or a mode (completion answer standby mode) in which the talker unit of each IPC 52 is set in the standby mode to await the completion answer from the listener unit after the data transmission from the talker unit of ob 10o IPC 52 to the listener unit of other IPC 52 is ended and the data communication bus L11 is released.

0* 'When the control signal SEL is at level, 0e the mode is the polling mode and when the control signal SEL is at level, the mode is the completion answer standby mode. In the polling mode (when the 000, control signal SEL is at level), the IBC transmits the polling number to the polling number L *lines PNO to PN3. Then, the communication bus use request circuit 143 of the talker unit of each IPC 52 20 receives the polling number at the same time as the Spolling number line synchronizing signal PSYNC rises from to and the polling number collating circuit 159 shown in Figure 7 determines whether or not the polling number coincides with its own number.

Data transmitted to the polling number lines 53 PNO to PN3 in the completion answer standby mode (when the control signal SEL is at level) is the completion answer transmitted by the completion information circuit 49 of the listener unit 31 of the receiving side IPC 52, and the completion information receiving circuit 144 of the talker unit of the transmitting side IPC 52 receives the completion answer via the polling number lines PNO to PN3 when the PSYNC is at level.

10 Figure 9 is a diagram of the polling sequence when the talker unit of the IPC 52 requests a S* communication.

Oe 'The polling number line use mode control signal SEL cyclically repeats level and level S and, as in the explanation of Figure 8, fundamentally, when the control signal SEL is at level, the signal of the polling number lines PNO to PN3 is the S* polling number and when it is at level, the signal of the polling number lines PNO to PN3 is the 20 completion answer.

o a Assume that the talker unit of the IPC 52 has a communication request. Then, when the control signal SEL is at level and at the timing t1 in which the polling number line synchronizing signal PSYNC rises, the communication bus use request circuit 54 143 of the talker unit of the IPC 52 receives the signal on the polling number lines PNO to PN3 as the polling number and executes the collation of that number of its own number. If the polling number is coincident with its own number, the communication bus use request circuit 143 makes the communication bus use request signal PINH signal at level (t2).

This PINH signal is at level and active. The PINH signal which becomes active is received by the communication bus use permission circuit 133 of the IBC 40, and the communication bus use permission circuit 133, if the data communication bus L11 can be used, makes the communication bus use permission signal TOK The TOK is at level and active.

Subsequently, the data transmitting circuit 140 of the talker unit of the IPC 52 detects that the communication bus use permission signal TOK is changed o" o to level and designates the listener which is the transmission destination by utilizing DATAO to 8, the data communication synchronizing signal TSYNC and data order content signals TODO, 1 on the data communication bus L11. More specifically, the listener designating number is transmitted to the data communication bus L11 (DATAO to 8) and a signal 55 indicating that the signals DATAO to 8 are the listener designating numbers is transmitted to the TODO, 1. The TSYNC repeats level and level at a predetermined cycle.

Then, the listener designating circuit 148 within the listener unit of the receiving side IPC 52 latches the listener designating numbers of DATAO to 8 at the same time as the TSYNC rises (t4) and determines whether or not they coincide with its own collating number. If they do and if the receiving side is in the receivable condition, the listener designating numbers are transmitted to the talker unit of the transmitting side IPC 52 and the IBC 40 as the listener designation receiving OK signals TANSO, 1.

Thus, the talker unit of the transmission side IPC 52 starts the data transmission to the listener unit of the receiving side IPC 52 via the data communication

S

bus L11.

When the completion information line 20 designating circuit 134 of the IBC 40 receives the reception OK signal from the listener unit 31, the listener unit of the data reception side IPC 52 transmits designation information of communication lines (completion answer line) to be transmitted to the polling number lines PNO to PN3. This completion 56 answer line is designated when SEL level (in the polling mode), communication TOK level (the state in which the data communication bus L1 is utilized) and at the timing in which TANSO, 1 reception OK is satisfied The answer line designating informations transmitted to PNO to PN3 are received by the completion information receiving circuit 144 of the talker unit of the transmitting side IPC 52 and the completion information circuit 149 of the listner unit of the reception side IPC 52 at the timing in which the PSYNC rises That is, the completion answer line designating information output from the completion information line designating circuit 134 of S 15 the IBC 40 is stored in the listener completion answer line designating register 163 in the listener unit and is also stored in the talker completion answer line designating register 168 of the talker unit.

As described above, the talker unit of the S' 20 transmission side IPC 52 receives from the listener unit of the reception side IPC 52 the listener designation reception OK signals TANSO, 1 to perform the data transmission. When the final data is transmitted to the listener unit, the final data T- transmitted to the data communication bus L11 (DATAO 57 to 8) is received by the data receiving circuit 45 of the listener unit 31 of the reception side IPC 2 at the timing in which the TSYNC rises Also, the data transmitting circuit 40 of the talker unit simultaneously transmits the data order content signals TODO, 1 which indicate the final data, to the listener unit. The data order content signals TODO, 1 are decoded by the data order content decoding circuit 46 of the listener unit 31 of the reception side IPC 10 2, and when the data order content decoding circuit 46 determines that the received data is the final data, the listener unit 31 transmits the answer indicating

S

5 the final data from the data receiving circuit 45 to the talker unit 30 of the transmitting side IPC 2.

Subsequently, in the talker unit 30 of the transmission side IPC 2, the final answer detecting o circuit 42 detects that the transmitted answer is the final answer, and the communication bus use request signal PINH is returned to level (t7) to thereby withdraw the use request of the data communication bus L11. Then, the communication bus use permission circuit 33 detects that the PINH is changed to "H" level and returns the communication bus use permission signal TOK to level (t8).

As described above, as in the first 58 embodiment, when the data transfer among the processors is finished, the data communication bus L11 is immediately released.

Then, the listener unit of the reception side IPC 52 transfers reception data stored in the buffer memory to the main memory unit within the processor to which the listener is connected in a DMA transfer fashion. When the inside transfer of data is finished, the completion information circuit 144 latches the completion answer condition signal S68 from the listener control unit at the trailing edge of the control signal SEL to thereby change the output of the AND circuit 166 to level. Thus, the completion answer line designating information stored 9 in the listener completion answer line designation register 163 and output from the completion information line designating circuit of the IBC 40 is too*: transmitted through the PNO to PN3 transmission gate 167 to polling number lines PNO to PN3.

S* 20 The completion answer line designating information transmitted to polling number lines PNO to PN3 is received by the completion information receiving circuit 144 of the talker unit of the transmission side IPC 52 and the completion answer receiving circuit 136 of the IBC 59 In the completion information receiving circuit 144 of the talker unit, the completion answer line designating information and the content of the talker completion answer line designation register 168 are compared by the completion answer collating circuit 170. As described before, since the above completion answer line designation information is stored in the register 168, it is determined that the two blocks of information coincide and thus the completion answer collating circuit 170 outputs the completion answer signal to the talker control unit through the completion answer latch flip-flop 171.

Thus, the talker unit of the transmission side IPC 52 S recognizes that the data transmission is complete.

9.

The completion answer is latched in the IBC completion answer line designating register 157 of the completion answer receiving circuit 136 via the 9 completion answer input gate 139, and is input to the completion information line managing circuit 153 via 20 the register 157. Then, the completion information line managing circuit 153 recognizes the fact that the fo* inter-processor data transfer is completed.

co Figure 10 shows an operation flowchart of interprocessor data communication in the second embodiment of the present invention. In Figure 10, operations 60 corresponding to those of the first embodiment are marked with the same reference numbers and therefore need not be described in detail.

As shown in Figure 10, in the second embodiment, the IBC 40 transmits via the polling number line (polling mode (SEL and TOK L13 (PNO to PN3) the blocks of completion answer line designating information S151 and S152 to the talker unit of the transmission side IPC and the listener unit of the reception side IPC, respectively, so that S* the completion information line L9 needed to designate the information line of the completion answer to the listener unit 31 of the reception IPC 2 in the first embodiment becomes unnecessary. Further, as shown in Figure 10, the listener unit of the reception side IPC 52 transmits the blocks completion answer line information S155 and S156 to the IBC 40 and the talker unit of the transmission side IPC 52 via the polling number line L3 (PNO to PN3) in the completion answer S* 20 standby mode (SEL so that the completion talker number synchronizing line L7 required by the first embodiment becomes unnecessary. Accordingly, the second embodiment can reduce the number of communication lines compared with the first embodiment and the wiring can be made easier.

61 Further, in the second embodiment, as shown in Figure 10, since the completion answer (completion answer line designating information) S156 is transmitted directly to the talker unit of the transmission side IPC 52, and not via the IBC 40, the completion answer can be transmitted to the talker unit of the transmission IPC 52 earlier than in the first embodiment.

While data communication among the call process processors CPR is described in the aforementioned embodiments, data communication can be similarly carried out between the management processor MPR and the call processing processor CPR via the IPC.

S" The present invention is not limited to the digital switchboard and can be applied to all apparatuses which utilize a multiprocessor system.

As set forth above, according to the present invention, in interprocessor communication, since the data communication bus can be released at the same S" 20 time as the data transfer is finished between processors, the data communication bus can be released earlier than in the conventional system by a period of time required to transfer data to the interprocessor communication control unit, thus making it possible to increase the throughput. Thus, the entire throughput 62 of the interprocessor communication in the multiprocessor system can be increased.

Furthermore, it becomes possible to increase the processing efficiency of the entire network system which comprises the apparatus of the present invention.

Having described preferred embodiments of the invention with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments and that various changes and modifications thereof could be effected by one skilled in the art without departing from the spirit or scope of the invention as defined in the *r appended claims.

4*s S l 4*

Claims (22)

1. An interprocessor communication system in a multiprocessor system comprising: a plurality of processors, a data communication bus connected to said plurality of processors, a bus control unit for controlling a use right of said data communication bus by polling to transmit polling numbers to polling number lines, and a plurality of interprocessor communication control units, each said interprocessor unit connected to a one of said plurality of processors, and controlling transmission and reception of data among said processors via said data communication bus, and wherein: when a reception side interprocessor communication control unit receives final data from a transmission side interprocessor communication control unit, said reception side interprocessor communication control unit transmits an answer of the reception of said final data to said transmission side interprocessor communication control unit, when said transmission side interprocessor communication control unit receives said answer, said transmission side interprocessor *control unit •control unit 64 transmits information of a withdrawal of a use of said data communication bus to said bus control unit, when said bus control unit receives said information, said bus control unit restarts said polling af-te said reception side interprocessor communication control unit transfers all reception data accumulated therein to the processors connected thereto, said reception side interprocessor communication control unit transmits to said bus control unit a completion answer indicating that data transfer is o completed, and when said bus control unit receives said completion answer, said bus control unit transmits to said transmission side interprocessor communication control unit completion information indicating that the interprocessor data communication is complete.

2. An interprocessor communication system o 4 according to claim 1, wherein said r. ception side 0 e interprocessor communication control unit transmits 20 said completion answer through a communication line designated by said bus control unit to said bus S control unit.

3. An interprocessor communication system S according to claim 2 wherein, when said bus control 4 55 unit receives from said reception side interprocessor communication control unit information indicating that preparation of data reception is finished, said bus control unit designates via a predetermined communication line, a communication line through which said completion answer is to be transmitted to said reception side interprocessor communication control unit.

4. An interprocessor communication system according to claim 3 wherein said bus control unit designates said polling .imber line used by its own polling as said communication line through which said completion answer is transmitted. S S

5. An interprocessor communication system according to claim 1, wherein said bus control unit utilizes a polling number k. of said transmission side interprocessor communication control unit as said completion information transmitted to said transmission side interprocessor communication control unit, and said transmission side interprocessor communication control unit determines whether or not said polling number transmitted from said bus control unit coincides with a polling number allocated thereto, and when it does, said transmission side 66 interprocessor communication control unit detects that interprocessor communication is complete.

6. An interprocessor communication system according to claim 2, wherein said bus control unit utilizes a polling number of said transmission side interprocessor communication control unit as said completion information transmitted to said transmission side interprocessor communication control unit, and said transmission side interprocessor S° communication control unit determines whether or not said polling number transmitted from said bus control unit coincides with a polling number allocated *0 e9 thereto, and when it does, said transmission side interprocessor communication control unit detects that interprocessor communication is complete.

7. An interprocessor communication system according to claim 3, wherein 9 said bus control unit utilizes a polling number 20 of said transmission side interprocessor communication control unit as said completion information transmitted to said transmission side interprocessor communication control unit, and said transmission side interprocessor io communication control unit determines whether or not 67 said polling number transmitted from said bus control unit coincides with a polling number allocated thereto, and if it does, said transmission side interprocessor communication control unit detects that interprocessor communication is completed.

8. An interprocessor communication system according to claim 4, wherein said bus control unit utilizes a polling number of said transmission side interprocessor communication control unit as said completion information transmitted to said transmission side interprocessor .communication control unit, and said transmission side interprocessor communication control unit determines whether or not *4 15 said polling number transmitted from said bus control unit coincides with a polling number allocated thereto, and when it does, said transmission side interprocessor communication control unit detects that 4* interprocessor communication is complete. 'l 20

9. An interprocessor communication system according to claim 1, wherein said bus control unit transmits said polling number or said completion information to said polling number line in a first mode, said reception side interprocessor communication 68 control unit transmits said completion answer to said polling number line in a second mode, and said first and second modes are alternately switched in a time sharing manner. An interprocessor communication system according to claim 4, wherein said bus control unit transmits said polling number or said completion information to said polling number line in a first mode, said reception side interprocessor communication control unit transmits said completion answer to said polling number line in a second mode, and S said first and second modes are alternately a. e.

S* switched in a time sharing manner.

11. An interprocessor communication system according to claim 8, wherein said bus control unit transmits said polling number or said completion information to said polling *4 number line in a first mode, said reception side interprocessor communication control unit transmits said completion answer to said polling number line in a second mode, and said first and second modes are alternately switched in a time sharing manner.

12. An interprocessor communication system in a 69 multiprocessor system comprising: a plurality of processors, a data communication bus connected to said plurality of processors, a bus control unit for controlling a use right of said data communication bus by a polling to transmit polling numbers to polling number lines and an interprocessor communication control unit connected to said plurality of processors and controlling transmission and reception of data among said processors via said data communication bus, and wherein: when a reception side interprocessor communication control unit receives final data from a transmission side interprocessor communication control unit, said reception side interprocessor communication control unit transmits an answer of the reception of said final data to said transmission side interprocessor communication control unit, when said transmission side interprocessor communication control unit receives said answer, said transmission side interprocessor control unit transmits information of a withdrawal of a use of said data communication bus to said bus control unit, f e 70 when said bus control unit receives said information, said bus control unit restarts said polling, after said reception side interprocessor communication control unit transfers all reception data accumulated therein to the processors connected thereto, said reception side interprocessor communication control unit transmits to said bus control unit and said transmission side inter- processor communication control unit a completion answer indicating that the data transfer is finished.

13. An interprocessor communication system S. according to claim 12 wherein, when said bus control *5 unit receives from said reception side interprocessor communication control unit information indicating that preparation of data transfer is finished, said bus control unit transmits to said reception side interprocessor communication control unit and said transmission side interprocessor communication control 20 unit a completion answer line designating information which designates an information line through which said completion answer is to be transmitted.

14. An interprocessor communication system according to claim 13 wherein, said bus control unit designates said polling number line utilized by its 71 own polling as a communication line through which said completion answer is to be transmitted by said completion answer line designating information.

An interprocessor communication system according to claim 12, wherein said reception side interprocessor communication control unit and said transmission side interprocessor communication control unit include means for storing designating information designating a communication 10 line through which said completion answer transmitted 00 00 00 0 S0 from said bus control unit is to be transmitted, said reception side interprocessor communication control unit transmits said designating information 0 B stored therein as said completion answer to said transmission side interprocessor communication control unit as said completion answer, .said transmissio, side interprocessor *00* communication control unit determines whether or not said completion answer coincides with said designating 0 information stored and if it does, said transmission side interprocessor communication control unit recognizes that interprocessor data communication is complete.

16. An interprocessor communication system according to claim 13, wherein 72 said reception side interprocessor communication control unit and said transmission side interprocessor communication control unit include means for storing designating information designating a communication line through which said completion answer transmitted from said bus control unit is to be transmitted, said reception side interprocessor communication ccntrol unit transmits said designating information stored therein as said completion answer to said transmission side interprocessor communication control unit as said completion answer, said transmission side interprocessor 0'00 communication control unit determines whether or not a said completion answer coincides with said designating information stored, and if it does, said transmission side interprocessor communication control unit recognizes that interprocessor data communication is complete.

17. An interprocessor communication system a. so 20 according to claim 14, wherein said reception side interprocessor communication control unit and said transmission side interprocessor communication control unit include means for storing designating information designating a communication line through which said completion answer transmitted r v 73 from said bus control unit is to be transmitted, said reception side interprocessor communication control unit transmits said designating information stored therein as said completion answer to said transmission side interprocessor communication control unit as said completion answer, said transmission side interprocessor communication control unit determines whether or not said completion answer coincides with said designating information stored, and if it does, said transmission o* side interprocessor communication control unit recognizes that interprocessor data communication is S complete. *4 4 0

18. An interprocessor communication system according to claim 13, wherein said bus control unit transmits said polling number or said completion information to said polling 4 number line in a first mode, 0a said reception side inter-processor communication 20 control unit transmits said completion answer to said polling number line in a second mode, and r said first and second modes are alternately switched in a time sharing manner.

19. An interprocessor communication system according to claim 14, wherein 74 said bus control unit transmits said polling number or said completion information to said polling number line in a first mode, said reception side inter-processor communication control unit transmits said completion answer to said polling number line in a second mode, and said first and second modes are alternately switched in a time sharing manner.

An interprocessor communication system according to claim 15, wherein S* ,said bus control unit transmits said polling number or said completion information to said polling number line in a first mode, S4 6. said reception side interprocessor communication control unit transmits said completion answer to said polling number line in a second mode, and said first and second modes are alternately 18pae switched in a time sharing manner.

21. An interprocessor communication system Ott 20 according to claim 16, wherein said bus control unit transmits said polling number or said completion information to said polling number line in a first mode, said reception side interprocessor communication control unit transmits said completion answer to said V 75 polling number line in a second mode, and said first and second modes are alternately switched in a time sharing manner.

22. An interprocessor communication system according to claim 17, wherein said bus control unit transmits said polling number or said completion information to said polling number line in a first mode, said reception side interprocessor communication 10 control unit transmits said completion answer to said *0 SO 0 polling number line in a second mode, and 9 0 0 ,o said first and second modes are alternately 0 switched in a time sharing manner. S DATED this TWENTIETH day of MARCH 1991 Fujitsu Limited Patent Attorneys for the Applicant SPRUSON FERGUSON *050 05 6 3 *S 06