KR950010950B1 - Communication apparatus between processors having bus structures - Google Patents

Abstract

The device is applied to the processor communication of distributed control system, and reduces the delay time for bus communication. The device includes local higher/lower counters(11,12) which select the link address by round robbin method, a counter-part address register(14) which saves the address of received processor, a self address register(15) which saves the address of transmission processor, a comparator(13) which compares the value between a counter-part address and self address, and a local-counter stop signal generator(16) which reserves the transmission of data. The device further includes 1st AND logical means(18), 2nd AND logical means, 3rd AND logical means, OR logical means(20), and a buffer enable signal generator(17).

Description

Interprocessor Communication Device and Method in Bus Structure

1 is a round-robin link selection flowchart for explaining the present invention.

2 is a block diagram of an interprocessor communication apparatus according to the present invention.

3 is a process flow diagram for an interprocessor communication method according to the present invention.

* Explanation of symbols for main parts of the drawings

11, 12: local-counter 13, 13-1 to 13-4: address comparator

14: relative address register 15: magnetic address register

16: Local-Counter Count Stop Signal Generator

17: Buffer Enable Signal Generator

An interprocessor communication device in a bus structure for forming a pint-to-point transmission link and bus arbitration on a bus for a plurality of processors connected by a bus to communicate with each other; and It is about a method.

In general, the existing interprocessor communication method in the bus structure is considered in two aspects. The first is a bus arbitration method, in which selection, random access, and reserve are widely used. Second, a communication method is a method in which a processor transmitting on a bus transmits transmission data to all the other processors, and determines whether or not to receive data on the receiving processor side and selectively receives data to perform mutual communication. In the injection control system which performs various control functions by being interconnected through a bus, which is a communication path shared by a plurality of processors, the interprocessor communication method affects the performance of the system. In the distributed control system, the bus arbitration method is widely used in the selection, competition, and reservation methods. In the communication method, most of the bus arbitration methods allow a processor authorized to transmit data to all the other processors at the same time. The inter-processor communication is performed by a broadcast method in which the receiving processor determines whether to receive data and selectively receives the data. However, in the case of the broadcasting method, as the number of processors connected to the bus increases, the management of the transmission and reception queue (a kind of memory) and the implementation of the protocol become complicated, and the bus cannot be configured in full duplex. There is a problem such as.

In order to solve the above problems, the present invention, unlike the broadcast method widely used for the communication system between the existing distributed control system, between two points between two processors to communicate with each other among a plurality of processors connected on the bus By performing communication by forming a transmission link, it is possible to solve the shortcomings of the existing scheme. The bus arbitration scheme uses a bus arbitration scheme that is a mixture of the selection scheme and the reservation scheme among the existing selection, reservation, and competition schemes. Existing bus arbitration by allowing the next link to be selected immediately if there is no data to send, and granting communication rights to two processors connected to both sides of the link if the link is selected if there is outgoing data, i.e. reserved. In a bus structure to minimize delays It is an object of the present invention to provide an interprocessor communication apparatus and method.

In order to achieve the above object, the present invention receives a clock signal from an external source, receives a local-counter stop signal, inputs a local-counter reset signal, and expresses an address of a link that can be formed, and links the link in a round-robin manner. Local upper and lower counter for selection, relative address register for storing the address of the receiving processor if data is to be transmitted, magnetic address register for storing the address of the sending processor if data is to be transmitted, the local-counter The relative address register which stores the address of the link represented by the link and the address of the processor which is zeroed on both sides of the link, comparing means for determining whether or not the value of the own address register is identical, a local counter with the local upper counter, a count. Output stop signal and receive transmission data A local-count count stop signal generating means for storing transmission processor address in the relative address register and scheduling transmission of data to be transmitted, and an output of the comparing means as an input, both of which are connected to the value of the relative address register and the link; First AND logic means that one of the processor addresses match, and the second AND logic means that one of both processor addresses connected to the link matches the value of the self address register as an input of the output of the comparison means. A third end logic means connected to an output end of the first and second end means to indicate that at least one coincides, and a relative address register and a magnetic address register simultaneously connected to an output end of the first and second end means. OR logic means for outputting a match to said local-counter count stop signal generating means, said local Enabling a buffer located at a matching part of the link formed by receiving a local-counter count stop signal from a counter count stop signal generating unit and a signal indicating at least one match from the third end logic unit; A buffer enable signal generating means is provided for the device.

In addition, the operating method of the inter-processor communication device as described above resets the local upper and lower counters, starts counting the local upper and lower counters, and compares the local upper and lower counter values with their own addresses. If the value is not the same, return to the count start process. If the comparison value is the same and the transmission reservation is made, if the local up / down counter value and the relative address are the same, stop the count of the local upper / lower counter. After performing the second and second steps of investigating the occurrence of the occurrence of the second step, the bus buffer is enabled to form a two-point link between the two processors, thereby performing communication in a full duplex manner, disabling the bus buffer, and starting a local counter count. The third step of returning to Shall be.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1 is a flowchart for selecting a link in a round-robin manner to illustrate the present invention.

In order to form a transmission link between a plurality of processors interconnected by a bus, a unique address assigned to each processor is used. In other words, the link is represented by two processor-specific addresses connected to both sides of the link. Assuming four processors are connected to the bus, each processor's unique address can be represented by two bits, and since there are two processors connected to the transmission link, all links that can be formed on the bus can be represented by four bits. All cases of formable links through the bus are shown in Table 1 below. Among the 16 addresses shown in (Table 1), the address indicated by (a) is removed because both processor addresses of the link are the same, so the link is not formed.

In addition, addresses 00 01 and 01 00 are marked with the same link so that 01 00 is removed. Remove one by one of the addresses that represent the same link, indicated by the remainder (b). In this way, if unnecessary addresses are removed and arranged among addresses representing all possible links on the bus, they are shown in Table 2. In the case of four processors connected to the bus, the total number of links that can be formed is six, and these links are selected in a round-robin manner as shown in the figure to communicate between the processors connected to the selected link. Grant permission to do so. Local-counters are used to select a total of six formable links in a round-robin fashion. That is, each link is configured to be represented by the value of the local-counter, and the local-counter is placed on each processor so that all the local-counters have the same value and are sequentially increased, thereby forming all formable links in a round-robin manner. To be selected.

TABLE 1

TABLE 2

2 is a block diagram of a device according to the present invention, including local-counters 11 and 12, address comparators 13-1 to 13-4, relative address register 14, magnetic address register 15, local A counter count stop signal generator 16, a buffer enable signal generator 17, present in all processors connected to the bus.

Local-counter 12 represents the address of the formable link and is a means for selecting the link in a round-robin fashion. The clock and the local-counter reset signal input to the local-counter 12 select one processor among the processors connected on the bus as the main processor and the other as the subordinate processor to distribute from the main processor to the subordinate processor. . The clock signal is a signal for driving the local-counter 12, and the local-counter reset signal is a reset for causing all links to be selected once by the local-counter 12 in a round-robin manner and then the first link is selected again. It is a signal.

The relative address register 14 is a means for storing the address of the receiving processor when data is to be transmitted. The address comparator 13 checks whether the address of the link represented by the local-counter 12 and the values of the relative address register 14 and the self address register 15 that store the address of the processor connected to both sides of the link match. Judge.

The local-counter count stop signal generator 16 is logic that operates when there is data to be transmitted. The local-counter count stop signal generator 16 stores a counterpart processor address that should receive the transmission data in the relative address register 14 and transmits that there is data to be transmitted. The reservation signal is used to reserve the local-counter count stop signal generator 16.

If the value of the local-counter 12 and the value of the relative address register 14 and the magnetic address register 15 both match at the same time, that is, the address of the link to be selected is displayed by the local-counter 12, the local- The counter count stop signal generator 16 outputs a local-counter stop signal to all processors to stop the count of the local-counter 12 and to indicate that the bus is occupied.

The OR logic 20 indicates that both the address and relative address register 14 and magnetic address register 15 of both processors connected to the selected link coincide simultaneously.

The buffer enable signal generator 17 is a means for enabling a buffer located at a matching portion of a link to be formed. When transmitting data, the values of the local-counter 12 representing the addresses of both processors connected to the selected link and the relative address register 14 and the self-address register 15 both coincide, and at the same time receive the local-counter. One of both processor addresses of the link indicated by the value of (12) and the value of the self address register 12 coincide. Therefore, the enable signal of the buffer is a local counter, the counter stop signal is enabled, and both the processor address and the relative address register 14 value or the magnetic address register 15 of the link indicated by the value of the local counter 12. It occurs when at least one of the values matches.

The AND logic elements 21 indicate that at least one coincides.

AND logic element 18 indicates that the value of relative address register 14 matches one of both processor addresses connected to the link, and AND logic element 19 indicates both the value of magnetic address register 15 and the link connected to the link. Indicates that one of the processor addresses matches.

3 is a flowchart of a method for communicating in a full duplex manner by forming a physical two-point link in a bus structure according to the present invention.

The local counters 11 and 12 represent the unique addresses of the two processors connected to the two-point link, and thus will be described separately in the upper and lower parts.

The local high and low counter reset 21 is a means for synchronizing, ie, synchronizing all local high and low counters located in each processor at all times while maintaining the same value. Supply to the determined processor. After resetting the local high and low counters 11 and 12, each local high and low counters 11 and 12 start counting (22), the value of which is compared with the magnetic address of each processor (23), and the processor's self address and local high rank. Or, if the lower counter value is the same, that is, if a link that is connected to the own processor is selected, it is determined whether to reserve a transmission (24).

If a transmission reservation is made, the local upper or lower counter value is compared with the relative processor address to be transmitted (25). In the same case, the own processor address and the relative processor address to be transmitted are identical. Since the link connecting the processors is selected, the count stop signal of the local upper and lower counters is generated to stop the count (26), and the bus buffer is enabled (27) to form a two-point link between the two processors. If a transmission reservation is not made, it is determined whether a local upper / lower counter count stop signal is generated (28). If a signal is generated, the bus processor is enabled because the self-processor is designated by the transmitting processor as the receiving processor. Form a link between two points.

If no signal is generated, the count of the local upper and lower counters 11 and 12 is continued since it is not designated to the receiving processor. When the two-point link formation is completed by the buffer enable 27, communication is performed in full duplex (29). When full duplex communication is completed (30), the bus buffer is disabled (31) and the round-robin method is performed. The counting of the local high and low counters 11 and 12 is then restarted so that the link is immediately selected.

The present invention can be used as it is for inter-processor communication of a distributed control system having not only a bus structure but also a link bus, a parallel bus or a serial bus structure, as well as a star, tree, or mesh structure. Can be.

Therefore, the effects of the present invention as described above are as follows.

1) Can be used for interprocessor communication in all distributed control systems with linkable structures.

2) It can be implemented to communicate by selecting only necessary links among the linkable links on the bus.

3) Since communication is performed by forming a link on the bus, management of a transmission and reception queue and implementation of a protocol are simple.

4) It is possible to communicate by full-duplex line configuration on the bus, which improves performance.

5) Minimize delay time in bus arbitration.

Claims (2)

Local high and low counters (11, 12) for receiving the clock signal from the outside, receiving the local-counter stop signal, inputting the local-counter reset signal, expressing the address of the link that can be formed, and selecting the link in a round-robin manner. ) The relative address register 14 for storing the address of the receiving processor if data is to be transmitted, the magnetic address register 15 for storing the address of the sending processor if data is to be transmitted, and the local-counter. Comparison means (13) for determining whether or not the values of the relative address register (14) and the magnetic address register (15) that store the address of the link represented by (12) and the address of a processor connected to both sides of the link are identical. ), A counterpart processor that outputs a local counter count stop signal to the local upper counter 11 and receives transmission data; A counter is stored in the relative address register 14, and the local-counter count stop signal generating means 16, which reserves transmission for the presence of data to be transmitted, and the output of the comparing means 13, are inputted. A link between the value of the magnetic address register 15 and the output of the first end logic means 18 and the comparison means 13 indicating that the value of 14 and one of both processor addresses connected to the link match. Second and logic means 19, which indicate that one of the two processor addresses connected to each other, and the output terminal of the first and second end means 18, 19 are connected to the relative address register 14 and the magnetic address register. OR logic means 20 for outputting to the local-counter count stop signal generating means 16 that (15) coincides simultaneously, and a local-counter count stop signal from the local-counter count stop signal generating means 16; A buffer enable signal generating means (17) for enabling a buffer located at a matching portion of a link formed by receiving a signal indicating at least one match from the third and logic means (21). An interprocessor communication device in a bus structure, characterized in that the. Local upper and lower counters 11 and 12, relative address register 14, magnetic address register 15, comparing means 13, local-counter count stop signal generating means 16, first and logic means 18, A method of operating an interprocessor communication apparatus comprising: a second end logic means 19, a third end logic means 21, an OR logic means 20, and a beeper enable signal generating means 17; A first step (21 to 23) of resetting the local upper and lower counters 11 and 12, starting the counting of the local upper and lower counters 11 and 12, and comparing the values of the local upper and lower counters 11 and 12 with their own addresses; After performing steps 1 to 21, if the comparison value is not the same, the process returns to step 22. If the comparison value is the same and the transmission reservation is made, if the local high and low counter value and the relative address are the same, the local high and low counters 11 and 12 After the second step (24, 25, 26, 28) and the second step (24, 25, 26, 28) of checking whether or not the local count stop signal is generated, Enabling a bus buffer to form a two-point link between the two processors, performing a full duplex communication, disabling the bus buffer and returning to the local counter count start process (29-31). The communication method between the processor in the bus structure to a.