JPH03270210A - Silicon wafer - Google Patents

Abstract

PURPOSE:To facilitate photolithography process and prevent the electric characteristic deterioration of an element caused by dislocation by incorporating boron and germanium which is 2-11 times of the boron concentration in a silicon wafer. CONSTITUTION:A silicon wafer contains boron and germanium which is 2-11 times of the boron concentration (1X10<18>cm<-3> or more is preferable). Therefore, crystal strength can be improved compared with the conventional silicon wafer. Thus, even when high temperature heat process is repeated, especially for the large diameter silicon wafer, camber is suppressed, photolithography process is facilitated and deterioration of the electric characteristic of an element caused by dislocation is prevented so as to improve the yield.

Description

[Detailed Description of the Invention] [Summary] Regarding high-strength silicon wafers, especially large-diameter silicon wafers, warping can be made difficult even when heat treatment is repeatedly performed at high temperatures, thereby facilitating the photolithography process. It is possible,
The purpose is to provide a high-strength silicon wafer that can prevent deterioration of the electrical characteristics of elements due to the generation of dislocations and improve yields. or boron and the boron concentration of 0
．． 4 to 2 times the concentration of tin, or boron and lead 0.3 to 2 times the boron concentration, or boron and 1 to 2 times the boron concentration. It is constructed to contain 7 times as much aluminum or gallium, or it is constructed as to contain indium and boron that is 1 to 5 times as high as the indium concentration.

[Industrial application field]

The present invention relates to silicon wafers, particularly large-diameter wafers, which can be made less likely to warp even when subjected to repeated heat treatments at high temperatures.

Silicon wafers used as substrates for semiconductor integrated circuits (VLSIs) are repeatedly heat-treated at high temperatures for the formation of oxide films, gettering, diffusion of impurities, formation of epitaxial layers, and the like. At this time, because it is impossible with current heat treatment technology to heat and cool the entire silicon wafer while keeping it at the same temperature, a temperature distribution occurs within the surface of the silicon wafer, which causes thermal stress. Due to this thermal stress, dislocations occur within the silicon wafer, causing plastic deformation of the silicon wafer, which is observed as warping.

When a silicon wafer is warped in this way, it becomes difficult to perform a photolithography process. Further, dislocations of 10' cm -2 or more are present in the plastically deformed silicon wafer, which deteriorates the electrical characteristics of the device and lowers the yield. As silicon wafers become larger in diameter and devices become more highly integrated, which will be promoted by the development of LSIs, the allowable warpage of silicon wafers will become smaller and smaller.
The requirements for high-strength silicon wafers that are less likely to generate dislocations will become increasingly strict in the future.

[Conventional technology]

Silicon wafers are manufactured by processing silicon single crystals grown by the Czochralski method (hereinafter referred to as the CZ method) or the floating zone method (hereinafter referred to as the FZ method). Currently, there are approximately 90 silicon crystals for substrates.
% is growing using the CZ method. The reason for this is as follows. CZ silicon is grown by dipping a seed crystal into melted raw material silicon in a quartz crucible and continuously pulling it up. The main component of the quartz crucible is 5 iOz, and since the quartz crucible reacts with and dissolves the silicon melt, the silicon melt inevitably has a high oxygen concentration. Therefore, CZ silicon crystals also contain oxygen, whose concentration is ~10
It is 18C13. It is known that oxygen in CZ silicon wafers fixes dislocations, increases strength, and suppresses warpage1>, 2).For this reason, CZ silicon wafers contain a higher amount of oxygen than FZ silicon wafers, which contain almost no oxygen. It is used.

1) Yasuo Tarui (ed.), “Wafer Warpage and Deformation”, VLSI Technology, Ohmsha (1981) 211°2) H, Shi
mizu et at,, Jpn, J, Appl, P
hys, +25 (1986) 68° FIG. 8 is a diagram showing the relationship between the oxygen concentration in a silicon wafer and warpage measured by Tarui et al. 13. As is clear from Figure 8, the warpage of the CZ silicon wafer containing a large amount of oxygen is overwhelmingly smaller than that of the FZ silicon wafer that contains almost no oxygen, and the CZ silicon wafer is better than the wafer with a high oxygen concentration. is small. Therefore, it can be seen that the higher the oxygen concentration of a silicon wafer, the more dislocations are fixed, the stronger the silicon wafer, and the smaller the warpage.

However, the data shown in FIG. 8 is the result of measurement under heat treatment conditions of 1150° C. for only 30 minutes to cause warping. Generally, when heat-treated at around 1000°C for several hours, oxygen in the silicon wafer forms oxygen precipitates.
This precipitate is well known to increase warpage of silicon wafers2'. In other words, with heat treatment for just 30 minutes as shown in Figure 8, almost no oxygen precipitates, so the warpage decreases as the oxygen concentration increases; 2 as shown
), the warpage of silicon wafers increases significantly with increasing oxygen precipitate density. This warpage is caused by the formation of oxygen precipitates, which expand in volume, and thereby generate new dislocations. For this reason, the strength decreases and warpage increases. In actual VLSI process, the temperature is 1000℃.
Since the heat treatment before and after the process lasts for a long time, the oxygen concentration, heat treatment conditions, and wafer dimensions (diameter, thickness) must be carefully adjusted to the extent that strength reduction and yield can be tolerated3.
)3) Ca5e S, &J,, et al,,E
P-137914-A.

J-60062107-^.

From the above, it is considered that a silicon wafer processed from a silicon crystal that contains a high concentration of oxygen and has a property that this oxygen is difficult to precipitate is extremely difficult to warp. Kishino et al. 4
From this point of view, each of these authors independently developed a high oxygen concentration silicon wafer in which oxygen is difficult to precipitate.

4) Masatake Kishino, Katsu Kanamori, Doji Suehiro, Yoshiaki Matsushita, Published Patent Publication, 1977-77170゜5) T, 5uzuki, N, Isawa + K, H
o5hi+ Y, 0kubo.

and Y, Kato, Fifth International
tional Sy+npo-siua+ on
5ilicon Materials 5cien
ce and Technology, 13B (1
986).

First, the method of Kishino et al.
The idea is to rapidly cool the wafer from a high temperature of 00"C or higher to room temperature to obtain a high-strength wafer that is difficult for oxygen to precipitate. However, small-diameter silicon wafers with a diameter of about 4 inches are susceptible to thermal stress that occurs during rapid cooling. It can be handled without much problem, but if this is done on a silicon wafer with a large diameter of 6 inches or more, the thermal stress generated during quenching will increase, causing dislocations in the silicon wafer and conversely increasing warpage. In addition, the yield of devices decreases.On the other hand, 5u
The method of Zuki et al. uses the CZ method to grow crystals at twice the normal speed in order to reduce the oxygen precipitation that occurs during growth. However, in order to achieve stable growth with a constant diameter control, the growth rate must be lowered as the diameter of the crystal becomes larger. For,
0.5 to 0.8 ++uo for 8 inch diameter wafer
In addition, when growing at high speed, it is difficult to obtain a long length. For the above reasons, Kishino et al.
Methods such as i are difficult to apply to large diameter silicon wafers.

Furthermore, Ito et al. 6' reported that FZ silicon wafers processed from nitrogen-doped FZ silicon crystals have less warpage due to heat treatment than CZ silicon wafers processed from ordinary CZ silicon crystals.

6) Ito T, et al, εP-284
107-A, J-63239200-A.

However, the diffusion rate of nitrogen in high-temperature silicon wafers is very fast; for example, the diffusion coefficient of nitrogen at 1200'C is approximately 10-'cm"5ec-'7), 1
When heat-treated at 200″C for 30 minutes, the nitrogen under 2JI t = 210-’
! / m spread. Here, D is the diffusion coefficient and t is the diffusion time.

7) Itoh and T, Abe, ^pp1. Ph
ys, Lett, 53 (1988) 39゜The thickness of a silicon wafer is usually 600 to 800 am, so by heat treatment at 1200"C for 130 minutes, all the nitrogen in the silicon wafer escapes to the outside of the silicon wafer, which has the effect of suppressing warpage. In an actual VLSI process, a longer heat treatment is performed (for example, 1200'C for 13 hours in a CCD process), so this nitrogen-doped FZ silicon wafer is of little practical use.

[Problem to be solved by the invention]

As mentioned above, conventional silicon wafers have a problem in that dislocations are more likely to occur when heat treatment is repeatedly performed at high temperatures, especially as the silicon wafer becomes larger in diameter, resulting in weakened strength and warpage. For this reason, there have been problems in that, especially as silicon wafers have larger diameters, it becomes more difficult to carry out the photolithography process, and the electrical characteristics of the elements deteriorate due to the occurrence of dislocations, resulting in lower yields.

Therefore, the present invention makes it possible to make it difficult to cause warping even when heat treatment is repeatedly performed at high temperatures, especially in large-diameter silicon wafers, thereby making it possible to facilitate the photolithography process, and to reduce the possibility of warpage due to the occurrence of dislocations. The purpose of the present invention is to provide a high-strength silicon wafer that can prevent deterioration of the electrical characteristics of the silicon wafer and improve the yield.

[Means to solve the problem]

The present invention provides boron and the boron concentration (1×IQI8cII-
The above problem is solved by a silicon wafer containing 2 to 11 times as much germanium (preferably 3 or more).

Here, the reason why the germanium concentration is set to 2 to 11 times the boron concentration is as follows.

■ In the case of boron and germanium, in order to alleviate the lattice strain caused by boron by adding Ge, the Ge concentration is set to 4.
It is calculated that 3 times as much is required. However, in reality, the effect of improving strength appears even when the germanium concentration is around 4.3 times, as shown in FIG.

Therefore, the effect of Qe addition is calculated value (4.3 times) xo, 5 ~ calculated value (4.3 times)
It can be read from FIG. 3 that it appears in the range of 2.5=2.15 times to 10.75 times. That is, the claimed range of germanium concentration is 2 to 11 times the boron concentration.

The present invention also provides boron and the boron concentration (1×1018
A silicon wafer containing 0.4 to 2 times as much tin as Cm −' or higher), boron and the boron concentration (I
A silicon wafer containing 0.3 to 2 times the lead of X 10"am-" or more), boron and 1 of the boron concentration (preferably 3.8X10Iffe11-" or more)
Silicon wafer containing ~7 times as much aluminum or gallium, indium and the indium concentration (5.2 x 1
The above-mentioned problem can also be solved by a silicon wafer containing 1 to 5 times as much boron (preferably 0.17 cm-' or more). The impurity addition here is also considered in the same manner as in the case of the above-mentioned combination of boron and germanium. In other words, ■ In the case of boron and tin, 0.81X0.5~0.81X2.5=0.405
~2.025 That is, the claim range of 5nf3 degrees is B f74 degrees of 0.
Increase the amount by 4 to 2 times.

■For poron and lead 0.61 x O, 5 ~ 0.61 x 2.5 = 0.3
05 to 1.525 In other words, the claimed range of PB concentration is 0.3 to 2 times the B concentration.

■For boron and aluminum, boron and gallium 2.
6 xo, s~2.6 X2-5 =1.3~6.5 That is, the claimed range of aluminum (or gallium) is 1~7 times the boron concentration.

■In the case of indium and boron, 1.9 xo, s ~ 1.9
Double it.

In the present invention, each of the C4-like silicon wafers may contain oxygen at a concentration of 5.2 × 1017C11-' or more, and in this case, dislocations are more difficult to occur, the strength is improved, and the warpage is improved. is less likely to occur, which is preferable.

[Effect]

First, wafer warpage and its suppression will be described in terms of crystal engineering, and then the principle of the present invention will be explained in detail.

The fundamental cause of plastic deformation in crystals is the movement of lattice defects called dislocations. It is known that dislocations move in a specific direction in a crystal under stress and their density increases (referred to as dislocation multiplication). When one dislocation reaches the crystal surface from the inside of the crystal, a fault of one atom appears on the surface.

Naturally, this fault has strain energy. Since dislocations multiply in large numbers during movement, these faults also become large and can be observed with an optical microscope using the etching method. When this phenomenon occurs with a silicon wafer, which is a thin disk, the balance between the strain accumulated on one side of the surface and the strain accumulated on the other side is lost, causing the wafer to warp as a whole. become. Therefore, when observing the surface of a warped silicon wafer on a primitive scale, there are a veritable number of "atomic fault lines".

Now, as can be seen from the above explanation, in order to reduce the warpage of silicon wafers, the first consideration is to suppress the occurrence of dislocations. However, this is not possible with current silicon crystal technology.

For one thing, although crystals grown by the CZ and FZ methods are said to be dislocation-free, recent research has revealed that they contain defects called A defects18) J. Chikawa et al. ,, “Se
m1conductor 5i1icon 1986'
'', 61° It has been confirmed that this A defect is a micro dislocation loop I), and many micro dislocation loops are formed even in a silicon crystal immediately after growth.The second is the processing technology of silicon wafers. This means that the surface of the silicon wafer is not sufficiently charged to form a flat processed surface on the order of atoms.In particular, there is still no technology to finish the rounded part (also called beveled part) around the silicon wafer to a mirror surface. This is the part where the most processing strain is accumulated in the silicon wafer.Therefore, when a silicon wafer is subjected to thermal stress caused by taking it in and out of the furnace during heat treatment, there is an extremely high possibility that dislocations will be introduced from the peripheral part of the silicon wafer. As described above, it is impossible to completely eliminate the occurrence of dislocations mainly for two reasons.

The next possible method for reducing warpage is to suppress the movement of existing dislocations as much as possible under thermal stress. By inhibiting movement, proliferation is also inhibited. It was mentioned above that oxygen and nitrogen reduce warpage, but this effect can be described from the standpoint of crystal engineering as follows. According to Kadono et al., oxygen and nitrogen have the effect of fixing dislocations at high temperatures and inhibiting their movement even when stress is applied9.
) 10) + II) + If) 9) K,5aino et al,, Jpn,
J, Appl, Phys, + 19 (1980) L7
63゜10) K, Su+++ino et al.
J. Appl, Phys., 54 (1983) 50
16°11) 1. Yonenaga and K.S.
amino, J., Appl., Phys.

56 (1984) 2346°22) 1. Yonenaga and K, Sum.
ino, Jpn, J. Appl-Phys,, 23
(1984) 1590° Therefore, CZ silicon wafers and nitrogen-added FZ silicon wafers have small warpage.

However, CZ with oxygen precipitated by long-term heat treatment
When stress is applied to a silicon wafer, dislocation loops are punched out from the precipitates13), and these dislocations multiply, causing plastic deformation of the silicon wafer.

13) 1. Yonenaga and K, Sumi
no, Jpn, J, Appl.

Phys., 21 (1982) 47° Furthermore, since the diffusion coefficient of nitrogen at high temperatures is extremely large, when a nitrogen-doped FZ silicon wafer is subjected to high-temperature heat treatment, nitrogen escapes from the wafer before fixing dislocations. For this reason, nitrogen-doped FZ silicon wafers also become warped as a result of long-term heat treatment. In this way, in order to make the crystal high in strength, it is necessary to suppress the movement of dislocations.

The present invention is characterized in that the crystal strength is increased compared to conventional silicon wafers by using a silicon wafer containing B and germanium Ge at a concentration of 2 to 11 times the B concentration.

Hereinafter, a silicon wafer containing B and Ge will be described as an example.

The detailed principle is as follows. The oxygen concentration of silicon crystal for IC is usually (1.0 to 2.0) × 1017 am
-', and each manufacturer selects an appropriate oxygen concentration within this range to minimize the decrease in strength due to oxygen precipitation.
A TM value of 4,3XIQ17am-' is used.

Same below. In addition, all impurity concentrations that appear in this patent are atomic number concentrations), so we used a silicon crystal with an oxygen concentration in this range, and added B and G as described later.
A preferable S-like case in which further increase in strength can be achieved by adding e will be described. First, as shown in Figure 1, oxygen was added at 1.5
B in the silicon crystal containing l ×1017C! If the amount of B added exceeds 11-', the strength begins to increase and reaches the maximum strength at about 1"O"C11-', J = (I x 1017 am-'), since single crystal growth becomes impossible. The limit for improving strength by adding B only is 1 x 10"ell-" addition.) This strength measurement method is called the indentation method, and the strength is measured as follows: High temperature (
In this experiment, a diamond needle is pressed into the surface of a sample heated to 900° C. to form an indentation. Strain due to deformation is accumulated around the indentation, so when the sample is kept at a high temperature, dislocations are naturally introduced to try to alleviate this strain. Since these dislocations can be observed as etch bits by selective etching, the spread of dislocations from the indentation can be quantitatively measured. Further, as shown in FIG. 2, the spread of this etch focus takes a specific shape depending on the crystal orientation and is called a rosette pattern.

As mentioned above, the more the movement of dislocations is suppressed, the stronger the crystal becomes, so the crystal with a small rosette pattern has a higher strength. Although it has been known that B affects the strength of silicon crystals10, the data shown in FIG. 1 by the present inventors is the first to systematically investigate the effect of B concentration on the movement of dislocations.

14) M-G, Milvidskii et al.
, 5oviet PhysicsSolid 5ta
te, 6 (1965) The covalent bond radius of 2531°B is 0.88, which is about 25% smaller than the covalent bond radius of silicon, 1.17°, so a large amount of B added accumulates lattice strain in the crystal. do. The reason why single crystal growth becomes impossible when B is added in an amount of 1×10″c+a−′ or more is considered to be because this lattice strain increases.

The covalent bond radius of Ge is 1622, which is about 4% larger than that of silicon. Therefore, it is thought that if Qe is added at the same time as B to alleviate the strain of B, the strength will further increase. There are many known techniques in which impurities with different covalent bond radii are simultaneously added to a local area near the surface of a silicon wafer or to a silicon thin film, and the lattice strain caused by one impurity is alleviated by the other impurity. 20)15
) H, J, Herzog eL al,, J, El
electrochem, Soc.

131 (1984) 2969°16) G, A, Rozgonyi et al, +
J, Crystal Growth.

85 (1987) 300°17) T-H-Yeh et al, J, Ele
ctrochem, Soc, +116 (1969)
73゜18) Y, T., Lee et al., J.E.
lectrochem, Soc, 122 (197
5) 530゜19) Gen Shibu Nakamura, Published Patent Publication 51-49674゜20) Gen Shibu Nakamura, Published Patent Publication 51-84577゜However, methods 15) to 20) are carried out by ion implantation method or vapor phase growth method. However, as will be described later, in the wafer of the present invention, impurities are added to the entire wafer by the CZ growth method, and the present invention is the first in which impurities are added to the entire silicon wafer.

FIG. 3 is a diagram showing the change in strength when Ge is further added to a silicon crystal to which B is added at an I x 101 Q value of -2. As is clear from FIG. 3, the strength of the crystal is further increased by adding Ge to 2 to 11 times the B concentration.

Suppressing oxygen precipitation is also important for maintaining crystal strength. However, as is clear from FIG. 9, if the oxygen precipitate density is 10'C11-' or less, there is almost no effect on warpage. When the silicon wafer with simultaneous addition of B and Ge of the present invention was heat treated at 700°C for 30 hours - 1100°C for 2 hours, the density of the formed oxygen precipitates was at most 5XIQ6am-'' (Btffi degree I
XIO19am-”, Ge concentration 1.5 x 1020C
111-3 silicon wafer), there is almost no effect on warping.

〔Example〕

When growing a crystal by the CZ method on a tip, B and Ge are added simultaneously to grow the crystal. Typical oxygen content is 1.5x
lO”an-’, and the typical amount of L and Qe added are B
: I X10X10l9', G e: 7 xIQ
It is I9an-3. During growth, impurity gas evaporates more rapidly than in normal CZ growth (due to the large amount of addition). Therefore, as shown in FIG. 4, it is preferable to provide a purge tube for efficient exhaustion. After the growth, the silicon wafer of the present invention can be obtained by processing the silicon crystal in the same manner as in normal processing steps.

In the present invention, in addition to the addition of Ge, S
The effects of the present invention can also be expected by adding n and Pb. Therefore, in addition to the first embodiment, the following embodiments may be considered.

■ Oxygen I X1Q"cm-" or more and B and Sn added ■ Oxygen I The amount of addition when relaxing the strain caused by the other impurity can be calculated theoretically as follows1
5′. Therefore, the amount of impurities added in Example 2.3 was determined by calculation and is shown below.

The effect of the present invention is obtained when the concentration of added B in the back-scanning group 2B and Sn is 1 x IQ l m cm -3 or more. The Sn concentration necessary to alleviate the strain that occurs when the B concentration is I × 1017 cm-3 is N
If we say s n, we will stand up. Here rε%rgn, r
ti is the covalent bond radius of B%Sn.Silicon. r, =0.88 people, rsr+=1.40 people, rsi
=1.17 people, Ns+s=0.81X10
"cm-" Therefore, the amount of Sn added is 0.81 times the amount of B added.

Therefore, in Example 2, oxygen was
or more and contains B of 1 x io"cm-' or more and Sn
This results in a silicon wafer in which B is added at a concentration 0.81 times the B concentration.

Since the calculation method is the same for Example 3, only the results are shown.

Contains 1.0x10"Ca1-' or more of the main oxygen of the brain and contains 1 B
×10th C111-' group or more pb is 0.61 of B1 degree
Double doped silicon wafer.

The embodiments of the present invention can also be considered in the following way. In Examples 1 to 3, a group 4 impurity was used to alleviate the strain of B, but the same group 3 impurities such as Al, Ge, and In should also be able to alleviate the strain of B. Moreover, B
The concentration of is not necessarily always l x l Q I l all
It can be seen as follows that it does not need to be -3 or more.

For example, taking the addition of B and Af as an example, it is calculated that 2.6 x 10'' value -3 of A1 is required to alleviate the strain caused by B in l x l Q I @ cI+-2.

However, the effects of the present invention can be expected even when the A/concentration is lxlQ"cm-" or more, and in this case, AI! The amount of addition necessary to alleviate the strain is calculated as 3.8X10'' value -
It is found to be 3 or more.

The situation of ■ and ■ is illustrated in Figure 5. 1.
The amount of L added is always 2.6/1 of the concentration of B = 10/
If 3.8=2.6 times, Br3 degree is 3.8xlO1
It is considered that the present invention is effective when the length is 7 cm or more.

Therefore, if the actual m contains 1.0x10"a!I-" or more of oxygen and 3
．． A silicon wafer having a size of 8×10 1 cm −′ or more and containing Al 2.6 times the concentration of B is used.

Since Ge has the same covalent bond radius as AA, it must contain more than 1.0X10"■-3 of oxygen and 3.8
×lQl'1C111-2 or more and Ge is 2.0% of B concentration.
A silicon wafer with 6 times the amount added is used. Similarly, regarding B and In, it is necessary to use B and In containing 1.0X10"C111-' or more of live oxygen and In
wo5.2XIQ17cm-' or more and B is 1 of the In concentration
．． A silicon wafer with 9 times the amount added is used.

〔Effect of the invention〕

Oxygen 1.5X10"am-', B 1X10I9
C! A silicon wafer according to the present invention with a diameter of 6 inches containing 7 x 1019ell-' of Ge and a conventional C
Z silicon wafer (oxygen concentration 1.5xlO”am-3)
After heat treatment at 1050°C for 100 hours in a nitrogen atmosphere, a thermal cycle of 1100°C at room temperature and 30 minutes of holding at room temperature was repeated 1 to 5 times. The speed of loading and unloading into the furnace is 6 seconds. FIG. 6 shows the warpage of both silicon wafers with respect to the number of thermal cycles. As is clear from FIG. 6, the warpage of the silicon wafer according to the present invention was reduced to about ⅓ compared to the conventional silicon wafer.

The most effective application example of the silicon wafer of the present invention is as a support substrate for an SOr device. This device is fabricated by gluing two silicon wafers together via an oxide film. Therefore, when a normal CZ silicon wafer is used, the wafer warps significantly during the thermal process and may even break. However, when the silicon wafer of the present invention was used, there was no cracking at all, and the warpage at the end of the thermal process was about 17 mm compared to when a normal CZ silicon wafer was used.
Reduced to 2.

The silicon wafer of the present invention has P for epitaxial layer growth.
``It is also more useful as a low-resistance substrate than conventional silicon wafers. That is, as a substrate wafer for CCD, 10-
"A low resistance wafer of about Ω value may be used. In this case, the B'1M degree of the substrate wafer is ~101"ell-"
A considerable amount of distortion has accumulated in order to The surface of this board is usually about 10Ω (B concentration IQ "cm-'")
silicon layers are grown by CVD, but mismatches occur in the epitaxial layer due to the lattice constant mismatch caused by the extreme concentration difference between the substrate and the epitaxial layer.
A Fint dislocation is introduced. As the silicon wafer of the present invention, for example, B is IX10''C111-3, Ge is 7
When a silicon wafer containing each of Obtain a high-quality P'' substrate. Figure 7(a) shows the slip caused by trillions-fint dislocations generated in the epitaxial layer of the conventional P'' substrate with oil addition, and Figure 7(b) shows the slip caused by the present invention. The slips that occur in the epitaxial layer when a silicon wafer of 200 nm is used as a P' substrate are shown. As is clear from FIGS. 7(a) and 7(b), the silicon wafer of the present invention greatly reduces the number of multi-spint dislocations. Further, when the silicon wafer of the present invention was used, the amount of warping of the silicon wafer that occurred after epitaxial growth was reduced to about 1/2 of that when a conventional silicon wafer was used.

[Brief explanation of drawings]

Figure 1 is a diagram showing the relationship between boron concentration and rosette pattern length of the present invention, Figure 2 is a diagram showing rosette patterns on the (100) plane and (1111 plane) of a conventional wafer, and Figure 3 is a diagram showing the rosette pattern length of the present invention. FIG. 4 is a diagram illustrating the crystal growth method of the present invention, and FIG. 5 is a diagram showing the relationship between the amounts of B and Af added in the present invention. FIGS. 6 and 7 are diagrams explaining the present invention in detail, FIG. 8 is a diagram showing the relationship between the oxygen concentration in a conventional silicon wafer and the change in warpage, and FIG. FIG. 1 is a diagram showing the relationship between the density of oxygen precipitates and warpage in a silicon wafer according to an example. Figure (100) plane (6') 1m) plane (b) Shows the rosette pattern on the (100) plane and (111) plane of a conventional wafer. Shows the relationship between the Ge concentration and the rosette pattern length of the disclosed invention. Fig. 5 shows the relationship between the amounts of B and A4 added according to the invention Fig. 4 shows a detailed explanation of the invention Fig. 6 shows a detailed explanation of the invention Figure 7 Procedural amendment (method) Flat bottom/via Month 13th 1, Display of the case 1990 Patent Application No. 72377 2, Name of the invention Silicon wafer 3, Person making the amendment Relationship to the case Patent applicant address 1015 Kamiodanaka, Nakahara-ku, Yozaki City, Kanagawa Prefecture Name (522) Fujitsu Ltd. 4, Agent Postal Code 211 Address 1015-6 Kamiodanaka, Nakahara Ward, Yozaki City, Kanagawa Prefecture
Figure 2 (a) of the drawing to be corrected 7. Contents of correction Figure 2 <a) of the drawing will be corrected as shown in the attached sheet. (There is no change in the contents of Figure 2 (b).) 8. List of attached documents (1) Corrected drawings (Figure 2) Above (1oo) plane (Q) (100) plane and (111) plane of conventional wafer Rosé 7)
・Figure 2 showing the pattern

Claims (9)

[Claims] (1) A silicon wafer characterized by containing boron and germanium at a concentration 2 to 11 times that of boron. (2) A silicon wafer characterized by containing boron and tin at a concentration of 0.4 to 2 times the boron concentration. (3) A silicon wafer containing boron and lead at a concentration of 0.3 to 2 times the boron concentration. (4) A silicon wafer characterized by containing boron and aluminum or gallium at a concentration of 1 to 7 times the boron concentration. (5) A silicon wafer containing indium and boron at a concentration of 1 to 5 times the indium concentration. (6) The silicon wafer according to any one of claims 1 to 3, wherein the concentration of boron is 1 x 10^1^8 cm^-^3 or more. (7) Boron concentration is 3.8 x 10^1^7cm^-^3
The silicon wafer according to claim 4, wherein the silicon wafer is as follows. (8) Indium concentration is 5.2 x 10^1^7 cm^-
6. The silicon wafer according to claim 5, wherein the silicon wafer is ^3 or more. (9) The silicon wafer according to any one of claims 1 to 8, characterized in that it contains oxygen at a concentration of 5 x 10^1^7 cm^-^3 or more.