JPH0326934B2 - - Google Patents

Info

Publication number
JPH0326934B2
JPH0326934B2 JP59109208A JP10920884A JPH0326934B2 JP H0326934 B2 JPH0326934 B2 JP H0326934B2 JP 59109208 A JP59109208 A JP 59109208A JP 10920884 A JP10920884 A JP 10920884A JP H0326934 B2 JPH0326934 B2 JP H0326934B2
Authority
JP
Japan
Prior art keywords
signal
timing
circuit
output
polarity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59109208A
Other languages
English (en)
Japanese (ja)
Other versions
JPS60251742A (ja
Inventor
Yasutsune Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP59109208A priority Critical patent/JPS60251742A/ja
Publication of JPS60251742A publication Critical patent/JPS60251742A/ja
Publication of JPH0326934B2 publication Critical patent/JPH0326934B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP59109208A 1984-05-29 1984-05-29 タイミング同期回路 Granted JPS60251742A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59109208A JPS60251742A (ja) 1984-05-29 1984-05-29 タイミング同期回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59109208A JPS60251742A (ja) 1984-05-29 1984-05-29 タイミング同期回路

Publications (2)

Publication Number Publication Date
JPS60251742A JPS60251742A (ja) 1985-12-12
JPH0326934B2 true JPH0326934B2 (enrdf_load_html_response) 1991-04-12

Family

ID=14504335

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59109208A Granted JPS60251742A (ja) 1984-05-29 1984-05-29 タイミング同期回路

Country Status (1)

Country Link
JP (1) JPS60251742A (enrdf_load_html_response)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0693677B2 (ja) * 1987-01-12 1994-11-16 富士通株式会社 識別タイミング制御回路
EP0296253B1 (en) * 1987-01-12 1995-06-28 Fujitsu Limited Discrimination timing control circuit
JPH0624352B2 (ja) * 1989-01-18 1994-03-30 日本電気株式会社 サンプリング位相誤差検出回路

Also Published As

Publication number Publication date
JPS60251742A (ja) 1985-12-12

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term