JPH03268217A - Head adjusting device for magnetic recording and reproducing device - Google Patents

Abstract

PURPOSE:To decrease the drift of a correction time quantity without receiving the influence of the state of patterns, environmental change, change with lapse of time, etc., by determining the time until the count value to start counting at the time of input of a trigger pulse coincides with a set value as the time correction quantity. CONSTITUTION:A D-FG signal which is a drum frequency generating signal and from which 24 pulses are output per revolution of a drum and a D-PG signal which is a drum phase detection signal and from which one pulse is output per revolution of the drum are inputted to a trigger pulse generating circuit 3. The head adjusting device executes the adjustment to match the pre scribed time by a down switch 11 and an up switch 12 connected to a microcom puter 10. Video head selection signal pulses (VH-SW-P) are formed of the digital monomulti signal output from a D-MM counter circuit 6. This digital monomulti signal is formed of the set value of a counter decoder 8 and count value of a count signal (fsc/2) output via the microcomputer 10.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is a method for adjusting the mounting error of a head used in a magnetic recording/reproducing device such as a video tape recorder (VTR) or a video cassette recorder (VCR). The present invention relates to a head adjustment device for a magnetic recording/reproducing device.

[Conventional technology]

In general, heads of magnetic recording/reproducing devices sometimes have errors in mechanical attachment when assembled. This mounting error is usually electrically adjusted by a head adjustment device built into the magnetic recording/reproducing device, and this adjustment is performed by the video head C1.

Conventionally, the above-mentioned head adjustment device, as shown in FIG.
D-FC (Drum Frequency Ge) is a drum frequency generation signal generated by the rotation of the drum.
nerator) signal and the drum phase detection signal D
-PC; (Drum Phase Genera
tor) signal is input, and a trigger pulse generation circuit 41 outputs a trigger pulse using both of these signals, an A-MM circuit 42 forms an analog monomulti signal with this trigger pulse, and an analog Video head switching signal pulse (V-H-3W-P with mono multi signal)
) and a H-3W-P generating circuit 43.

As shown in Figure 7, the above video head switching signal pulse is generated at the falling edge of the first input analog mono multi signal, and at the falling edge of the next input analog mono multi signal (A-MM). This analog monomulti signal ends at A-MM in Figure 6.
A capacitor 44, a resistor 45, and a variable resistor 46 connected to the circuit 42 adjust the correction time amount TA, which is the time from rise to fall.

The above correction time amount TA can be changed arbitrarily by the operator operating the variable resistor 46, and the above correction time amount TA can be adjusted to compensate for errors in head installation. Therefore, the rising or falling edge of the video head switching signal pulse and the vertical synchronization signal of the video output signal -8YNC (Vertica 1-3sync)
) is adjusted by adjusting the interval from the start edge to a predetermined time t0.

[Problem to be solved by the invention]

However, in the above-mentioned conventional head adjustment device for a magnetic recording/reproducing device, the correction time amount TA is set by passive components including a capacitor 44, a resistor 45, and a variable resistor 46 connected to the A-MM circuit 42. , these passive components are subjected to a predetermined time t according to a correction time amount TA initially adjusted due to disturbances such as vibrations during transportation, environmental changes such as temperature, and changes over time. In addition, the above drift also occurs when the threshold voltage changes in the state of the pattern at the time of design, which places an unnecessary burden on the designer when designing the pattern. It is also supposed to be worn.

Furthermore, the adjustment of the correction time amount TA is performed by the operator rotating the variable resistor 46 using, for example, a screwdriver, and when the adjustment is completed and the driver or the like is removed, the variable resistor It is necessary to be careful not to change the adjustment by rotating 46. Therefore, the above-mentioned adjustment places an extra burden on the workers and causes a time loss in production.

Therefore, an object of the present invention is to provide a head adjustment device for a magnetic recording/reproducing device that can reduce the drift of the correction time amount TA without being affected by pattern conditions, environmental changes, changes over time, etc. A further object of the present invention is to provide a head adjustment device for a magnetic recording/reproducing device that can improve production efficiency by eliminating the need for operations when adjusting the amount of correction time TA.

[Means to solve the problem]

In order to solve the above problem, the head adjusting device for a magnetic recording and reproducing device according to the invention of claim 1 includes a D-FG counter circuit that outputs a trigger pulse based on a drum frequency generation signal and a drum phase detection signal. and a trigger pulse generating means which is a trigger pulse generating circuit consisting of a decoder, a mono-multi signal generating means for outputting a mono-multi signal having a correction time amount from the time of inputting the trigger pulse, and an adjusting means for adjusting the correction time amount. , a head adjustment device for a magnetic recording/reproducing device comprising a video head switching signal pulse generating means for forming and outputting a video head switching signal pulse using a monomulti signal, the monomulti generating means comprising a D-MM counter circuit. When a trigger pulse is input, for example, the amount of correction time is set to be the time until the count value that starts counting of the count signal obtained by dividing the color subcarrier frequency by 1/2 matches the set value from the adjustment means. , the adjustment means includes a control means such as a microcomputer that outputs a set value to the monomulti generator, a set value increase/decrease means including a down switch, an up switch, and a resistor that can increase or decrease the set value; EZ FROM that can store
It is characterized in that it consists of storage means such as.

In order to solve the above problem, the head adjustment device for a magnetic recording and reproducing device according to the invention of claim 2 includes a D-FG counter circuit that outputs a trigger pulse based on a drum frequency generation signal and a drum phase detection signal. and a trigger pulse generating means which is a trigger pulse generating circuit consisting of a decoder, a mono-multi signal generating means for outputting a mono-multi signal having a correction time amount from the time of inputting the trigger pulse, and an adjusting means for adjusting the correction time amount. , a head adjustment device for a magnetic recording/reproducing device comprising a video head switching signal pulse generating means for forming and outputting a video head switching signal pulse using a monomulti signal, the monomulti generating means comprising a D-MM counter circuit. When a trigger pulse is input, for example, the amount of correction time is set to be the time until the count value that starts counting of the count signal obtained by dividing the color subcarrier frequency by 1/2 matches the set value from the adjustment means. , the adjustment means includes a synchronization signal separation means comprising a 5YNC-3EP circuit that outputs a vertical synchronization signal detection pulse from the composite synchronization signal, and a synchronization signal separation means so that the vertical synchronization signal detection pulse and the video head switching signal pulse have a predetermined phase difference. It is characterized by comprising a control means such as a microcomputer that increases or decreases the set value, and a storage means such as an E''FROM that can store the set value.

[For production]

According to the configurations of claims 1 and 2, the mono-multi generation means sets the amount of correction time until the count value that starts counting upon input of the trigger pulse matches the set value from the adjustment means. It has become. Therefore, the mono-multi signal generating means outputs a mono-multi signal having the above correction time amount. At this time, the above counted value and set value are all made up of digital signals, and the amount of correction time determined by this counted value and set value is determined by environmental changes such as the pattern condition and temperature, changes over time, and transportation. It does not fluctuate due to external disturbances such as internal vibrations. Thereby, the video head switching signal pulse output from the video head switching signal pulse generating means is always stable.

Further, the adjusting means according to claim 2 provides control for increasing or decreasing a set value so that a vertical synchronizing signal detection pulse obtained separately from a composite synchronizing signal and a video head switching signal pulse have a predetermined phase difference. have the means. Therefore, all adjustments to the set values are performed by the above-mentioned control means, and the burden on the operator during adjustment is eliminated. Thereby, the head adjustment device having this adjustment means can improve production efficiency.

[Embodiment 1] An embodiment of the invention of claim 1 will be described as follows based on FIGS. 1 and 2.

The head adjustment device according to the present embodiment is applicable to, for example, a video tape recorder (VTR) or a video cassette recorder (VCR).
), etc., and as shown in Figure 1, the D-FC signal, which is a drum frequency generation signal that outputs 24 pulses for one rotation of the drum, and the D-FC signal, which is a drum frequency generation signal that outputs 24 pulses for one rotation of the drum. A D-PC signal, which is a drum phase detection signal from which one pulse is output per pulse, is input.

Above D-FG signal and D-PG double signal, input terminal 1
・The input signal is input to a trigger pulse generation circuit 3 which is a trigger pulse generation means that outputs a trigger pulse via a D-FC.
A D-FG counter circuit 4 and a decoder 5 which count the signals and detect the falling edge of the 0-value and 12-value D-PG multiplied signal, and which are reset at the rising edge of the D-PC signal.
It's empty.

The above-mentioned trigger pulse generation circuit 3 includes a D-MM counter circuit 6 which is a mono-multiple generation means having a 16-bit counter, and a V-H-3W- which is a video head change signal pulse generation means having a flip-flop. It is connected to the P generation circuit 7, and is adapted to output a trigger pulse to the I)-MM counter circuit 6 and the ■H-3WP generation circuit 7. Further, a count signal (rsc/2) obtained by halving the color subcarrier frequency fsc is input to the D-MM counter circuit 6, and the period of this count signal (fsc/2) is For example, in the case of the NTSC system, fsC=3.579545M) (set to approximately 0.55873 μsec, which is 1/2 of z).

A counter decoder 8 is connected to the D-MM counter circuit 6, which outputs a set value to be compared with the count value of the input count signal (fsc/2). A microcomputer 10 which constitutes an adjusting means is connected to a down switch 11, an up switch 12, and resistors 13 and 14, which will be described later as setting value increase/decrease means, and an E'' PROM 9, which is a storage means. The counter circuit 6 receives a set value consisting of a digital signal from a counter decoder 8 and a count signal (r sc/
A digital mono multi signal (D-
MM) is output.

The microcomputer 10 described above is connected to an up switch 12 and a down switch 11 that adjust the output time of the digital mono multi-signal. It is designed to extend the output time. On the other hand, the down switch 11 is configured to reduce the set value of the counter decoder 8 to shorten the output time of the digital monomulti signal.

One terminal of the up switch 12 and down switch 11 is connected to a power source, and the other terminal is connected to each input terminal of the microcomputer 10. The microcomputer 10 and the terminals of the switches 11 and 12 are pulled down via resistors 13 and 14. As a result, each input terminal of the microcomputer 10 has
A predetermined voltage is applied by pressing the down switch 11 and the up switch 12.

Furthermore, an electrically erasable and rewritable E" PROM 9 is connected to the microcomputer 10. This E" PROM 9 stores the digital mono multi-signal settings determined by the down switch 11 and up switch 12. The value is stored, and when the microcomputer 10 is reset, the set value is output from the E'' PROM 9.

In the above configuration, the operation of the head adjusting device will be explained below based on the timing chart of FIG.

First, for example, a standard production tape of VH3 standard is prepared,
This tape is played back by a magnetic recording/playback device. On this occasion,
A D-FC signal (FIG. 2A) is input to the D-PG counter circuit 4 from the pulse generator provided on the drum via the input terminal 2, and this D-FC signal (
In A) of the same figure, 24 pulses are output for one rotation of the drum.

The above D-FG counter circuit 4 uses a D-FC signal (A
) is counted. On the other hand, the D-PG counter circuit 4 receives a D-PG multiplied signal (B) in the same figure, in which one pulse is output for one revolution of the drum, through the input terminal 1, and this I)
The -PC signal (B in the same figure) resets the count value of the D-FG signal (A in the same figure) counted by the D-FG counter circuit 4. As a result, the trigger pulse generation circuit 3 consisting of the D-FG counter circuit 4 and the decoder 5 can be used both when the count of the D-FC signal (A in the same figure) is 0 and when the count is 18 from the reference 0°.
A trigger pulse is formed by 12 values when rotated by 0°.

The above trigger pulse is output to the D-MM counter circuit 6 and the ■/H-SW-P generation circuit 7, and in the D-MM counter circuit 6, the count signal (fs
c/2) will be executed up to the limit count number of 65,536.

This counting is executed until the counted value matches the set value of the counter decoder 8 set in advance by the microcomputer, and when it matches, the counted value is set and the digital mono multi signal (C in the same figure) The output of is stopped, and counting and output are on standby until the next trigger pulse is input. As a result, the amount of correction time T. is set by the time it takes for the above-mentioned count value to match the set value of the counter decoder 8 set in advance by the microcomputer.

The above correction time amount T. The digital mono multi-signal (C in the same figure) having the same value is output to the V-H-3W-P generating circuit 7, and causes the flip-flop of the V-H-3t-P generating circuit 7 to go to H level. In this ■H-3t-P generation circuit 7, the flip-flop changes to H level every time a digital mono multi-signal is input.

The video head switching signal pulse (D in the figure) is formed by the H level and L level. Then, this video head switching signal pulse (D in the figure) is outputted from the output terminal 15 to the outside, and is used for drum adjustment by being aligned with a predetermined position according to standards such as the VH3 standard. That will happen.

5 Next, the adjustment method will be explained.

The video head switching signal pulse (D in the same figure) must be set at a position where the rising or falling edge of the pulse precedes the V-3YNCSEP pulse (not shown) obtained from the vertical synchronization signal by a predetermined time by 1v. . Therefore, when adjusting to the above predetermined time tv, the correction time amount T0, which is the time from the rise to the fall of the digital mono multi-signal (C in the same figure) that forms the video head switching signal pulse (D in the same figure) will be adjusted.

The above correction time amount T. The adjustment is performed by a down switch 11 or an up switch 12 connected to the microcomputer 1°. That is, when the down switch 11 is pressed, the set value of the counter decoder 8 is decreased via the microcomputer 1o, while when the up switch 12 is pressed, the set value of the counter decoder 8 is decreased via the microcomputer 10. will be increased. And counter decoder 8
is set to an arbitrary setting value with the down switch 11 and up switch 12 described above, and then this setting value is set to I)
-It will be output to the MM counter circuit 6.

The D-MM counter circuit 6 to which the above set value is input is
The count value of the count signal (r sc/2) input from the other side is compared with the set value. At this time, the time required for the above-mentioned count value to match the set value becomes the correction time amount T, and the output of the digital mono multi-signal (C in the figure) is stopped after the above-mentioned correction time amount T0 has elapsed. And V-H-3
The W-P generation circuit 7 generates the digital mono multi-signal (
The video head switching signal pulse (D in the same figure) is output and stopped at C) in the same figure.

On the other hand, the operator who performs the adjustment operates the down switch 11 and the up switch 12 so that this video head switching signal pulse (D in the figure) precedes the V-3YNCSEP pulse by a predetermined time tv. At this time, the microcomputer 10 monitors the state in which the down switch 11 and up switch 12 are pressed, and if each of the above switches 11 and 12 is not pressed for a certain period of time, such as several hundred meters, for example, In this case, the setting value outputted to the counter decoder 8 is stored in the E''FROM 9.The setting value stored in the E2FROM 9 is then used for subsequent adjustments.

In this way, the head adjustment device of this embodiment has a predetermined time t.
Adjustment according to the voltage v is performed by a down switch 11 and an up switch 12 connected to the microcomputer 1o. Therefore, when making adjustments, each switch 1
Since the process is completed by pressing 1 and 12, the operation becomes easy and the burden on the operator can be reduced.

Further, the video head switching signal pulse is formed by a digital mono multi-signal output from the D-MM counter circuit 6, and this digital mono multi-signal is output from a counter decoder output via the microcomputer 1o. 8 and the count value of the count signal (rsc/2). Therefore, the video head switching signal pulses are all formed by digital signals and are always stable, unaffected by voltage fluctuations due to pattern conditions, disturbances such as vibrations during transportation, environmental changes, and changes over time. will be output.

Furthermore, the set value output from the counter decoder 8 is
It is stored in the E" FROM 9 connected to the microcomputer 10. Therefore, the head adjustment device having this E" FROM 9 can be immediately restored even if the microcomputer 10 is reset due to a power outage, etc. Become.

In addition, in this embodiment, the set value is the counter decoder 8.
Although the signal is outputted from the D-MM counter circuit 6 to the D-MM counter circuit 6, the present invention is not limited thereto. That is, the set value may be directly output from the microcomputer 10 to the D-MM counter circuit 6.

[Embodiment 2] An embodiment of the invention as claimed in claim 2 will be described below with reference to FIGS. 3 to 5. For convenience of explanation, members having the same functions as the nine members shown in the drawings of the above-mentioned embodiment are denoted by the same reference numerals, and the explanation thereof will be omitted.

As shown in FIG. 3, the head adjustment device according to this embodiment outputs a D-FC signal, which is a drum frequency generation signal, in which 24 pulses are output per one rotation of the drum, and one pulse is output per one rotation of the drum. A D-PG signal, which is a drum phase detection signal, is input.

The above D-FC signal and D-PG signal are input to input terminal 1.
・D-FG counter circuit 4 and decoder 5 via 2
The signal is inputted to a trigger pulse generation circuit 3 consisting of a trigger pulse generating circuit 3 comprising: Further, the trigger pulse generation circuit 3 described above has D
-MM counter circuit 6 and ■.H-3W-P generation circuit 7, and outputs a trigger pulse to these circuits 6 and 7.

Furthermore, the D-MM counter circuit 6 is configured to receive a count signal (f3°/2) obtained by halving the color subcarrier frequency rsc, and also to receive the input count signal (fsc A counter decoder 8 is connected which outputs a set value which is compared with the count value of 0/2). A microcomputer 10 is connected to the counter decoder 8 to set the above-mentioned setting values. As a result, the D-MM counter circuit 6 converts to the counter decoder 8.
A set value consisting of a digital signal and a count signal (f sc/
2) A digital mono multi signal (D-MM) that forms a video head switching signal pulse is output using the count value consisting of the digital signal.

The above digital mono multi signal is output to the V-H-3W-P generation circuit 7, and this V-H
The -3W-P generation circuit 7 is connected to the output terminal 15 and also to the microcomputer 10. Thereby, the video head switching signal pulse from the V-H-3W-P generation circuit 7 is input to the microcomputer 10.

The microcomputer 10 also includes a 5YNC-3EP up/down counter circuit 1 which is a synchronizing signal separating means.
7 (hereinafter referred to as 5YNC-3EP circuit 17) is connected, and this 5YNC-12SEP circuit 17 receives a composite synchronization signal (C0M
PO3IT-3YNC) is inputted via the input terminal 19, and the count signal (rsc/2) outputted to the D-MM counter circuit 6 described above is also inputted. And 5YNC-3EP circuit 1
7 is the above composite synchronization signal and counting signal (f, c/2
) to horizontal synchronization signal (H-3YNC) and vertical synchronization signal (
V-SYNC) and H-3, which indicates the horizontal synchronization signal.
■-3YNC indicating YNCSEP pulse and vertical synchronization signal
The SEP pulse is output.

The above 5YN(, -3EP circuit 17 has Up/
It has a d o w n counter, and this up/d
The own counter integrates the count signal (rsc/2) at the rising edge of the composite synchronization signal, and subtracts the count signal (f sc/2) at the falling edge.

Then, when the above integrated value becomes 4 power counts or more, the H-3YNCSEP pulse is output and the integrated value becomes 40
When the power count exceeds the power count, a V-3YNCSEP pulse is output.

In addition, the above 5YNC-SEP circuit 17 is
H-3YNCSEP terminal 17a that outputs SEP pulse
and V-3YNC which outputs V-3YNCSEP pulse.
SEP terminal 17b, V-3YNCSEP
The terminal 17b is connected to the microcomputer 10. Then, the microcomputer 10 calculates the time difference in the rise time of the pulse, which is the phase difference between the H-3YNCSEP pulse from the V-3YNCSEP terminal 17b and the video head switching signal pulse from the H-3W-P generation circuit 7. However, the set value to be output to the counter decoder 8 is determined so that this time difference becomes a predetermined time tv.

Furthermore, an electrically erasable and rewritable EtPROM 9 is connected to the microcomputer 10. This E2FR
OM9 is designed to memorize the set value of the digital mono multi signal determined by the microcomputer 10, and when the microcomputer 10 is reset, the set value is output from this E" PROM9. There is.

In the above configuration, the operation of the head adjustment device will be explained below based on the timing charts of FIGS. 4 and 5.

First, for example, a standard production tape of VH3 standard is prepared,
This tape is played back by a magnetic recording/playback device. On this occasion,
The D-FC signal (A in Fig. 4) is input to the D-FG counter 4 from the pulse generator provided on the drum via the input terminal 2, and the 200-FC; In A), 24 pulses are output for one rotation of the drum.

The above-mentioned D-FG counter 4 counts the D-FC signal with the constant position of the rotating drum being 0° as a reference. On the other hand, the D-FG counter 4 has a value of 1 for each rotation of the drum.
A D-PC signal (B in the same figure) from which a pulse is output is input through input terminal 1, and this D-PC signal (B in the same figure) is
D-FG multiplied signal counted by D-FC counter 4 A in the same figure
) is reset. As a result, the trigger pulse generation circuit 3 consisting of the D-FG counter 4 and the decoder 5
A trigger pulse is formed when the count of the D-FC signal (A in the same figure) is 0 value and when it is 12 values when rotated by 180 degrees from the reference 0°.

The above trigger pulse is output to the D-MM counter circuit 6 and
sc/2) is the limit count number of 6553
It will run up to 6.

Then, this counting is performed until the counted value matches the set value of the counter decoder 8 set in advance by the microcomputer, and when the counted value is reset, the digital monomulti signal (C in the same figure) is The output of is stopped, and counting and output are on standby until the next trigger pulse is input.

The above digital mono multi signal (C in the same figure) is
The signal is output to the 3W-P generation circuit 7, and causes the flip-flop of the Hsw-P generation circuit 7 to go to H level. This■・
In the H-3W-P generation circuit 75 6 , a flip-flop alternately outputs an H level and an L level each time a digital mono multi-signal is input, and a video head switching signal pulse (D in the same figure) is output at this H level and L level. It will be formed by the level. This video head switching signal pulse (D in the figure) is output to the outside from the output terminal 15 and is also output to the microcomputer 10.

On the other hand, the V-3YNC3EP pulse (E in the same figure) is input to the microcomputer 10, and this v-8YNCs
The EP pulse (E in the figure) is generated by the 5YNC-3EP circuit 17.

That is, the 5YNC-3EP circuit 17 has a composite synchronization signal (
A) in Fig. 5 and a count signal (rsc/2) a are input, and this count signal (rsc/2) is integrated by the up/down counter at the rising edge of the composite synchronization signal (A in the same figure). While the integrated value (B in the same figure) is increased, it is subtracted at the falling edge of the composite synchronization signal (A in the same figure), and the integrated value (B in the same figure) is decreased.

At this time, the above-mentioned composite synchronization signal (A in the same figure) has a vertical synchronization signal and a horizontal synchronization signal, and the vertical synchronization signal having a "H" duty of approximately 28 μsec is approximately 4.7 μsec.
This is sufficiently longer than the horizontal synchronization signal which has a "H" duty of μsec. Therefore, 5YNC-3EP
Using this difference in duty, the circuit 17 outputs the H-3YNCSEP pulse (C in the same figure) as a horizontal synchronization signal when the above integrated value (B in the same figure) exceeds 4 counts or more.
-3YNCSEP is output from the terminal 17a.

On the other hand, when the integrated value (B in the same figure) becomes 40 power counts or more, a V-3YNC3EP pulse (D in the same figure) is outputted from the V-3YNCSEP terminal 17b as a vertical synchronizing signal. This output is terminated before the integrated value (B in the figure) completes the fall.

As a result, the V-3YNCSEP pulse (D in the same figure) is
In the case of the NTSC system, the composite synchronization signal (A in the same figure) is 22.35μ, which is 40 watts more than the actual vertical synchronization signal.
The signal is output to the microcomputer 10 with a delay of sec. Therefore, my computer 10 uses the above (7) V-SYNC SEP parameters.
The calculation is performed with /s (D in the figure) corrected by 40 forces. In addition, microcontroller 10 and SYNC-
By providing a circuit for correcting the above 40 counts between the SEP circuit 17 and the SEP circuit 17, correction by the microcomputer 10 may be made unnecessary.

Next, the adjustment operation will be explained.

The video head switching signal pulse (D in Figure 4) is set at a position where the rising and falling edges of the pulse precede the V-SYNC SEP pulse (E in the same figure) obtained from the vertical synchronization signal by a predetermined time tv. need to be done.

Therefore, when adjusting to the above predetermined time tv, the correction time amount T, which is the time from the rise to the fall of the digital mono multi signal (C in the same figure) that forms the video head switching signal pulse (D in the same figure) . will be adjusted.

That is, the microcomputer 10 calculates the time difference in pulse rise time, which is the phase difference between the input video head switching signal pulse (D in the figure) and the V-SYNC SEP pulse, and compares this calculated value with the time difference in advance. 10 is compared with the predetermined time tv stored in 10. Then, from this comparison result, the correction time amount T of the digital mono multi-signal is determined. is increased or decreased in units of one step, and the increase or decrease is repeated until the time difference and the predetermined time tv match.

At this time, for example, V-SYNC SEP pulse (F
) is the reference V-SYNC SEP pulse (E in the same figure).
), the amount of correction time is T. is increased in units of one step, and the amount of correction time T is used as a reference.

A correction time amount T. is added to A time. +A will be determined as the set value. Then, by outputting this set value to the counter decoder 8, the D-MM counter circuit 6 receives the above correction time amount T. A digital mono multi-signal (G in the figure) with +A is output. As a result, the ■H-SW-P generation circuit 7 outputs the v-SYNC
A video head switching signal pulse (H in the same figure) that precedes the SEP pulse (F in the same figure) by a predetermined time tv is output.

9 0 On the other hand, for example, if the V-3YNCSEP pulse (FIG. 1) precedes the reference V-3YNCSEP pulse (FIG. 1E) by B time, the correction time amount T0 is decreased by one step, Correction time amount T serving as a reference. 8 hours is subtracted from the corrected time amount T. -B will be determined as the set value. Then, by outputting this set value to the counter decoder 8, the D-MM counter circuit 6 outputs a digital mono multi signal (J in the figure) having the above correction time amounts T and -B. Become. This results in
(2) The H-3W-P generation circuit 7 outputs a video head switching signal pulse (K in the figure) which is a predetermined time tv ahead of the V-3YNCSEP pulse (■ in the figure).

In this way, the corrected time amount To + that becomes the predetermined time tv
When A-To-B is determined, the microcomputer 10 stores this correction time amount To +A-To-B in the EtPROM 9. The correction time amounts To +A-T, -B stored in the E'' PROM 9 will be used as set values for subsequent adjustments.

In this way, the head adjustment device of this embodiment has a microcomputer 1.
Adjustment is performed by calculating the V-3YNCSEP pulse and the video head switching signal pulse, and adjusting the calculated value to a predetermined time tv. Therefore, all the adjustment work is performed by the microcomputer 10, which relieves the burden on the operator. Eliminating the burden of this adjustment will lead to an improvement in production efficiency.

Further, the video head switching signal pulse is formed by a digital mono multi signal output from the D-MM counter circuit 6, and this digital mono multi signal is output from a counter decoder output via the microcomputer 10. 8 and the count value of the count signal (f sc/2 ). Therefore, the video head switching signal pulses are all formed by digital signals, and are not affected by voltage fluctuations due to pattern conditions, environmental changes, disturbances such as vibrations during transportation, and changes over time. , the output will always be stable.

Furthermore, the setting 4fl output from the counter decoder 8
is stored in the E" PROM 9 connected to the microcomputer 10. Therefore, the head adjustment device equipped with this E" PROM 9 can be immediately restored even if the microcomputer 10 is reset due to a power outage, etc. It becomes possible.

Note that the adjustment to the predetermined time tv in this embodiment is performed using the correction time amount T.
0 in 1-step units, but this is not limited to this, and the DOC detection pulse from the DOC detection pulse generation circuit 18 of the reproduced video envelope (M in FIG. 4) is 0).

That is, in the reproduced video envelope (M in the same figure) inputted through the input terminal 20, there are times 1. A, and a pulse of time tell are generated. At this time, the DOC detection detection pulse light 2 circuit 18 detects the above-mentioned time t81.・The DOC detection pulse (0 in the same figure) with t DP't is output to the microcomputer 10, and the microcomputer 10 outputs this DOC detection pulse (0 in the same figure).
) is corrected by the amount of time T.

, and changes the video head switching signal pulse (N in the same figure) that is significantly deviated to a proper video head switching signal pulse (L in the same figure).

Thereby, the head adjustment device can perform adjustment from the video head switching signal pulse (L in the figure) to the predetermined time tv, and the time required for adjustment is shortened.

〔Effect of the invention〕

As described above, the video head switching signal pulse generation means according to claim 1 corrects until the count value that the mono-multi generation means starts counting upon input of the trigger pulse matches the set value from the adjustment means. control means for outputting a set value to the mono-multi generation means; set value increasing/decreasing means capable of increasing or decreasing the set value; and storage means capable of storing the set value. The structure consists of 3 4 .

As a result, by determining the amount of correction time using the count value and setting value made up of digital signals, the monomultiple The signal makes it possible to output stable video head switching signal pulses.

Further, in the video head switching signal pulse generation means according to claim 2, as described above, the count value that the mono-multi generation means starts counting upon input of the trigger pulse matches the set value from the adjustment means. The adjustment means includes a synchronization signal separation means for outputting a vertical synchronization signal detection pulse from the composite synchronization signal, and a synchronization signal separation means for outputting a vertical synchronization signal detection pulse from the composite synchronization signal, and a synchronization signal separation means for outputting a vertical synchronization signal detection pulse and a video head switching signal pulse at a predetermined time. The configuration includes a control means that increases or decreases the set value so as to have a phase difference, and a storage means that can store the set value.

As a result, as in the case of claim 1, by determining the amount of correction time using the count value and set value consisting of digital signals, environmental changes such as pattern conditions and temperature, changes over time, vibrations during transportation, etc. It is possible to output stable video head switching signal pulses using a monomulti signal that does not fluctuate due to disturbances such as the following.

Furthermore, since the control means increases or decreases the set value so that the vertical synchronization signal detection pulse and the video head switching signal pulse have a predetermined phase difference, all adjustment of the set value is performed by the above control means. This has the effect that the burden on the operator during adjustment is eliminated, making it possible to improve production efficiency.

[Brief explanation of drawings]

FIG. 1 and FIG. 2 show an embodiment of the invention as claimed in claim 1. It's a yard. 3 to 5 show an embodiment of the invention of claim 2. FIG. It's a yard. FIG. 5 is a timing chart when separating the composite synchronization signal. FIGS. 6 and 7 show conventional examples. It's a yard. 3 is a trigger pulse generation circuit (trigger pulse generation means);
6 is a D-MM counter circuit (mono multi generation means), 7
1 is a V-H-3W-P generation circuit (video head switching signal pulse generation means), 10 is a microcomputer (control means), 1 is a down switch (set value increase/decrease means), and 12 is an up switch (set value increase/decrease means) , 9 is an E” FROM (storage means), and 17 is a 5YNC-3EP circuit (synchronizing signal separation means). 7

Claims (1)

[Claims] 1. Trigger pulse generating means for outputting a trigger pulse based on a drum frequency generation signal and a drum phase detection signal, and outputting a monomulti signal having a correction time amount from the time of inputting the trigger pulse. A head adjusting device for a magnetic recording/reproducing device, comprising a mono multi signal generating means, an adjusting means for adjusting the amount of correction time, and a video head switching signal pulse generating means for forming and outputting a video head switching signal pulse using a mono multi signal. In the mono-multi generation means, the amount of correction time is set as the amount of time until the count value that starts counting upon input of the trigger pulse matches the set value from the adjustment means, and the adjustment means is adapted to generate the mono-multi A head for a magnetic recording and reproducing device, comprising a control means for outputting a set value to a generating means, a set value increase/decrease means for increasing or decreasing the set value, and a storage means for storing the set value. Adjustment device. 2. Trigger pulse generating means for outputting a trigger pulse based on a drum frequency generation signal and a drum phase detection signal; a mono-multi signal generating means for outputting a mono-multi signal having a correction time amount from the time of inputting the trigger pulse; In a head adjustment device for a magnetic recording and reproducing device, the head adjustment device for a magnetic recording and reproducing device includes an adjusting means for adjusting the amount of correction time, and a video head switching signal pulse generating means for forming and outputting a video head switching signal pulse using a monomulti signal. The means is configured to set the amount of correction time until the count value that starts counting when the trigger pulse is input matches the set value from the adjustment means, and the adjustment means adjusts the vertical synchronization signal detection pulse from the composite synchronization signal. a synchronizing signal separating means for outputting the vertical synchronizing signal detection pulse and the video head switching signal pulse, a control means for increasing or decreasing a set value so that the vertical synchronizing signal detection pulse and the video head switching signal pulse have a predetermined phase difference, and a storage means capable of storing the set value. A head adjusting device for a magnetic recording/reproducing device, characterized in that the head adjusting device comprises: