JP2519816B2 - Head adjusting device for magnetic recording / reproducing apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to magnetic recording for adjusting a mounting error of a head used in a magnetic recording / reproducing apparatus such as a video tape recorder (VTR) or a video cassette recorder (VCR). The present invention relates to a head adjusting device of a reproducing device.

[Conventional technology]

Generally, the head of the magnetic recording / reproducing apparatus has a mechanical mounting error that occurs during assembly. This mounting error is usually electrically adjusted by a head adjusting device incorporated in the magnetic recording / reproducing apparatus, and this adjustment is performed by a video head switching signal pulse (V.H-SW-).
P) is aligned with a position defined on a standard such as the VHS (registered trademark) standard, for example.

Conventionally, the above-described head adjusting device, as shown in FIG. 6, includes a D-FG (Drum Frequency Generator) signal which is a drum frequency generation signal generated by the rotation of a drum,
D-PG (Drum Phase Gener) which is a drum phase detection signal
signal), and a trigger pulse generation circuit that outputs a trigger pulse with both of these signals.
41, an A-MM circuit 42 that forms an analog mono-multi signal with this trigger pulse, and a V-H-SW-P that forms a video head switching signal pulse (V-H-SW-P) with the analog mono-multi signal It consists of a generation circuit 43.

As shown in FIG. 7, the above video head switching signal pulse is generated at the falling edge of the analog mono-multi signal input first and then the falling edge of the analog mono-multi signal (A-MM) input next. This analog mono-multi signal is output by the capacitor 44, the resistor 45, and the variable resistor 46 connected to the A-MM circuit 42 shown in FIG. 6 from the rise time to the fall time. The correction time amount T _A is adjusted.

Then, the above correction time amount T _A is
By operating 46, the head mounting error can be adjusted by adjusting the correction time amount T _A, and the rising or falling of the video head switching signal pulse and the video output. The signal is adjusted by adjusting the interval between the signal and the start edge of V-SYNC (Vertical-Sync), which is a vertical synchronization signal, to a predetermined time t ₀ .

[Problems to be Solved by the Invention]

However, in the above-described conventional head adjusting device of the magnetic recording / reproducing apparatus, the correction time amount T _A is set by the passive component including the capacitor 44, the resistor 45, and the variable resistor 46 connected to the A-MM circuit 42. However, these passive components have a predetermined time t ₀ based on the correction time amount T _A initially adjusted due to disturbances such as vibration during transportation, environmental changes such as temperature, and changes over time.
Will be drastically drifted. Further, the above-mentioned drift is also caused by a change in the threshold voltage in the state of the pattern at the time of designing, and it also imposes an extra burden on the designer when designing the pattern.

Furthermore, the operator adjusts the correction time amount T _{A by} a variable resistor.
It is performed by rotating the 46, for example, with a screwdriver, etc., and when the driver or the like is pulled out after the adjustment is completed, it is necessary to take care not to disturb the adjustment by rotating the variable resistor 46. is there. Therefore, the above-mentioned adjustments impose an extra burden on the operator and cause a time loss in production.

Therefore, it is an object of the present invention to provide a head adjustment device for a magnetic recording / reproducing device that can reduce the drift of the correction time amount T _A without being affected by the state of the pattern, environmental changes, changes over time, and the like. Further, it is an object of the present invention to provide a head adjusting device for a magnetic recording / reproducing device, which can improve the production efficiency by eliminating the operation for adjusting the correction time amount T _A.

[Means for solving the problem]

In order to solve the above-mentioned problems, a head adjusting device for a magnetic recording / reproducing apparatus according to a first aspect of the present invention outputs a trigger pulse based on a drum frequency generation signal and a drum phase detection signal. And a trigger pulse generating circuit which is a trigger pulse generating circuit composed of a decoder, a monomulti generating means for outputting a monomulti signal having a correction time amount from the time of inputting the trigger pulse, and an adjusting means for adjusting the correction time amount. In a head adjusting device for a magnetic recording / reproducing apparatus, which comprises a video head switching signal pulse generating means for forming and outputting a video head switching signal pulse with a mono-multi signal, the mono-multi generating means comprises a D-MM counter circuit. , When the trigger pulse is input, for example, the count value that starts counting the count signal that is obtained by dividing the color subcarrier frequency by 1/2 The amount of correction time is set to match the set value from the adjusting means, and the adjusting means can increase / decrease the setting value with a control means such as a microcomputer that outputs the setting value to the mono-multi generation means. It is characterized in that it comprises a set value increasing / decreasing means including a down switch, an up switch, and a resistor, and a storage means such as an E ² PROM capable of storing the set value.

In order to solve the above problems, a head adjusting device for a magnetic recording / reproducing device according to a second aspect of the present invention outputs a trigger pulse based on a drum frequency generation signal and a drum phase detection signal. And a trigger pulse generating circuit which is a trigger pulse generating circuit composed of a decoder, a monomulti generating means for outputting a monomulti signal having a correction time amount from the time of inputting the trigger pulse, and an adjusting means for adjusting the correction time amount. In a head adjusting device for a magnetic recording / reproducing apparatus, which comprises a video head switching signal pulse generating means for forming and outputting a video head switching signal pulse with a mono-multi signal, the mono-multi generating means comprises a D-MM counter circuit. , When the trigger pulse is input, for example, the count value that starts counting the count signal that is obtained by dividing the color subcarrier frequency by 1/2 The amount of correction time is set to match the set value from the adjusting means, and the adjusting means is a synchronizing signal separating means including a SYNC-SEP circuit that outputs a vertical synchronizing signal detection pulse from the composite synchronizing signal, It is possible to store the set value and a control means such as a microcomputer that increases or decreases the set value so that the vertical sync signal detection pulse and the video head switching signal pulse have a predetermined phase difference.
It is characterized by comprising storage means such as E ² PROM.

[Work]

According to the configurations of claims 1 and 2, the mono-multi generation means sets the correction time amount until the count value that starts counting when the trigger pulse is input matches the set value from the adjustment means. It has become. Therefore, the mono-multi generation means outputs the mono-multi signal having the above-mentioned correction time amount. At this time, the count value and the set value are all digital signals, and the correction time amount determined by the count value and the set value is the change in the environment such as the state of the pattern and the temperature, the change over time, and the transportation. It does not fluctuate due to disturbances such as internal vibration. As a result, the video head switching signal pulse output from the video head switching signal pulse generating means is always stable.

Further, the adjusting means according to claim 2 is a control for increasing or decreasing the set value so that the vertical sync signal detection pulse obtained by separating from the composite sync signal and the video head switching signal pulse have a predetermined phase difference. Have means. Therefore, the adjustment of the set value is all performed by the above control means,
The burden on the operator at the time of adjustment will be eliminated. As a result, the head adjusting device having this adjusting means can improve the production efficiency.

[Embodiment 1] The following will describe one embodiment of the invention according to claim 1 with reference to FIG. 1 and FIG.

The head adjusting apparatus according to the present embodiment is built in a magnetic recording / reproducing apparatus such as a video tape recorder (VTR) or a video cassette recorder (VCR), and as shown in FIG. A D-FG signal, which is a drum frequency generation signal that outputs a pulse, and a D-PG signal, which is a drum phase detection signal that outputs one pulse for one rotation of the drum, are input.

The above-mentioned D-FG signal and D-PG signal are input terminal 1
The trigger pulse generating circuit 3 is a trigger pulse generating means for outputting a trigger pulse via 2 and the trigger pulse generating circuit 3 counts the D-FG signal and outputs 0 and 12 It is composed of a D-FG counter circuit 4 and a decoder 5 which detect the falling of the value D-FG signal and are reset at the rising of the D-PG signal.

The trigger pulse generating circuit 3 is a D-MM counter circuit 6 which is a mono-multi generating means having a 16-bit counter and a V.H-SW-P which is a video head switching signal pulse generating means having a flip-flop. It is connected to the generator circuit 7, and the D-MM counter circuit 6 and VH-
A trigger pulse is output to the SW-P generation circuit 7. The count signal (f _SC / 2) obtained by halving the color subcarrier frequency f _SC is input to the D-MM counter circuit 6 and the count signal (f _SC / 2 In the case of the NTSC system, for example, the period is set to about 0.55873 μsec which is 1/2 of f _SC = 3.579545M Hz.

The D-MM counter circuit 6 is connected to a counter decoder 8 that outputs a set value to be compared with the count value of the input count signal (f _SC / 2). A down switch 11, an up switch 12, which are setting value increasing / decreasing means, which will be described later, and resistors 13 and 14 and a microcomputer 10 which constitutes an adjusting means by an E ² PROM 9 which is a storing means are connected. As a result, the D-MM counter circuit 6
Mono-multi signal that forms a video head switching signal pulse (V · H-SW-P) using the set value composed of digital signals of the counter decoder 8 and the counted value composed of digital signals of the count signal (f _SC / 2) The digital mono-multi signal (D-MM) is output.

The microcomputer 10 is connected with an up switch 12 and a down switch 11 for adjusting the output time of the digital mono-multi signal, and the up switch 12 increases the set value of the counter decoder 8 to output the digital mono-multi signal. It is designed to extend the output time. On the other hand, the down switch 11 reduces the set value of the counter decoder 8 to shorten the output time of the digital mono-multi signal.

The above-mentioned up switch 12 and down switch 11 are
One terminal is connected to the power source, and the other terminal is connected to each input terminal of the microcomputer 10. The microcomputer 10 and the terminals of the switches 11 and 12 are pulled down via resistors 13 and 14. As a result, each input terminal of the microcomputer 10 has a down switch
A predetermined voltage is applied by pressing the up switch 11 and the up switch 12.

Further, the microcomputer 10 is connected to an electrically erasable and rewritable E ² PROM 9. This E ² PROM9
Stores the set value of the digital mono-multi signal determined by the down switch 11 and the up switch 12, and the set value is output from this E ² PROM 9 when the microcomputer 10 is reset. It has become.

The operation of the head adjusting device having the above configuration will be described below with reference to the timing chart of FIG.

First of all, for example, a VHS standard tape is prepared,
This tape is reproduced by a magnetic recording / reproducing apparatus. On this occasion,
The D-FG signal (FIG. 2A) is input to the D-FG counter circuit 4 from the pulse generator provided on the drum through the input terminal 2, and the D-FG signal (A in FIG. ) Outputs 24 pulses for one rotation of the drum.

The D-FG counter circuit 4 counts the D-FG signal (A in the figure) with a fixed position of the rotating drum as a reference 0 °. On the other hand, the D-FG counter circuit 4 receives a D-PG signal (B in the figure) that outputs one pulse for one rotation of the drum, and inputs the D-PG signal (B in the figure). ) Resets the count value of the D-FG signal (A in the figure) counted by the D-FG counter circuit 4. This gives D
-The trigger pulse generating circuit 3 including the FG counter circuit 4 and the decoder 5 is used when the count of the D-FG signal (A in the figure) is 0 value and when it is 12 values when the reference 0 ° is rotated by 180 °. Will form a trigger pulse.

The trigger pulse is output to the D-MM counter circuit 6 and the V · H-SW-P generation circuit 7, and the D-MM counter circuit 6 uses the trigger pulse to generate a count signal (f _SC / 2).
Will be executed up to the limit count number of 65536. Then, this counting is executed until the count value matches the set value of the counter decoder 8 set in advance by the microcomputer, and when the count value matches, the count value is reset and the digital mono-multi signal (C in the same figure) Output is stopped, and counting and output wait until the next trigger pulse is input. As a result, the correction time amount T
₀ is set by the time until the above-mentioned count value matches the set value of the counter decoder 8 set in advance by the microcomputer.

The digital mono-multi signal (C in the same figure) having the above-mentioned correction time amount T ₀ is output to the V · H-SW-P generation circuit 7,
The flip-flop of the V · H-SW-P generation circuit 7 is set to the H level. In the V / H-SW-P generation circuit 7, the flip-flop alternately outputs the H level and the L level for each input of the digital mono-multi signal, and outputs the video head switching signal pulse (D in the figure) to the H level. And L level. The video head switching signal pulse (D in the figure) is output from the output terminal 15 to the outside, and is used for adjusting the drum by being adjusted to a predetermined position in the standard such as VHS standard. Will be.

 Next, the adjustment method will be described.

The video head switching signal pulse (D in the same figure) has a predetermined time t _{v with} respect to the V-SYNC SEP pulse (not shown) whose rising or falling edge is obtained from the vertical synchronizing signal.
It needs to be set to the preceding position. Therefore, when adjusting to the above-mentioned predetermined time t _v , the correction time amount which is the time from the rise to the fall of the digital mono-multi signal (C in the same figure) forming the video head switching signal pulse (D in the same figure) T ₀ will be adjusted.

The adjustment of the correction time amount T ₀ is performed by the down switch 11 or the up switch 12 connected to the microcomputer 10. That is, when the down switch 11 is pressed, the setting value of the counter decoder 8 is reduced via the microcomputer 10, while when the up switch 12 is pressed, the setting value of the counter decoder 8 is reduced via the microcomputer 10. Will be increased. Then, the counter decoder 8 outputs the set value to the D-MM counter circuit 6 after the down switch 11 and the up switch 12 set the set value to an arbitrary value.

The D-MM counter circuit 6 to which the above set values are input is
The count value of the count signal (f _SC / 2) input from the other side is compared with the set value. At this time, the time until the count value and the set value match becomes the correction time amount T ₀ , and the digital mono-multi signal (C in the same figure) stops the output after the correction time amount T ₀ has elapsed. . Then, the V · H-SW-P generation circuit 7
Will output and stop the video head switching signal pulse (D in the figure) with the digital mono-multi signal (C in the figure).

On the other hand, the operator who performs the adjustment operates the down switch 11 and the up switch 12 so that this video head switching signal pulse (D in the figure) precedes the V-SYNC SEP pulse by a predetermined time t _v. . At this time, the microcomputer 10
Monitors the situation where the down switch 11 and the up switch 12 are pressed.
If is not pressed for a certain period of time such as several 100 msec, the set value output to the counter decoder 8 is stored in the E ² PROM 9. And this E ² PRO
The set value stored in M9 will be used for subsequent adjustments.

As described above, the head adjusting device according to the present embodiment is provided with the predetermined time.
The down switch 11 and the up switch 12 connected to the microcomputer 10 are used to perform adjustment to match t _v . Therefore, the work at the time of adjustment is the above-mentioned switches 11 and 12
Since it is completed by pressing, the operation becomes simple and the burden on the operator can be reduced.

The video head switching signal pulse is formed by a digital mono-multi signal output from the D-MM counter circuit 6, and the digital mono-multi signal is output via the microcomputer 10. 8
And the count value of the count signal (f _SC / 2). Therefore, the video head switching signal pulse is all formed by digital signals,
The output is always stable without being affected by voltage fluctuations due to the state of the pattern, disturbances such as vibration during transportation, environmental changes and changes over time.

Further, the set value output from the counter decoder 8 is stored in the E ² PROM 9 connected to the microcomputer 10. Therefore, the head adjustment device having this E ² PROM9
Even if the microcomputer 10 is reset due to a power outage, etc.
It will be possible to return immediately.

Although the set value is output from the counter decoder 8 to the D-MM counter circuit 6 in the present embodiment, the present invention is not limited to this. That is, the set value may be directly output from the microcomputer 10 to the D-MM counter circuit 6.

[Embodiment 2] The following will describe one embodiment of the invention according to claim 2 with reference to FIG. 3 to FIG. For the sake of convenience of explanation, members having the same functions as those shown in the drawings of the above-described embodiment are designated by the same reference numerals, and the description thereof will be omitted.

As shown in FIG. 3, the head adjusting apparatus according to the present embodiment outputs a D-FG signal, which is a drum frequency generation signal that outputs 24 pulses for one rotation of the drum, and one pulse for one rotation of the drum. The D-PG signal, which is a drum phase detection signal to be generated, is input.

The above-mentioned D-FG signal and D-PG signal are input terminal 1
It is adapted to be inputted via 2 to a trigger pulse generating circuit 3 comprising a D-FG counter circuit 4 and a decoder 5. In addition, the trigger pulse generation circuit 3 described above is a D-MM.
It is connected to the counter circuit 6 and the V · H-SW-P generation circuit 7, and outputs a trigger pulse to these circuits 6 and 7.

Further, the counting signal (f _SC / 2) obtained by halving the color subcarrier frequency f _SC is input to the D-MM counter circuit 6 and the input counting signal (f _{SC SC} / 2)
A counter decoder 8 for outputting a set value to be compared with the count value of is connected. The counter decoder 8 is connected to the microcomputer 10 for setting the above set values. As a result, the D-MM counter circuit 6 uses the set value composed of the digital signal of the counter decoder 8 and the count value composed of the digital signal of the count signal (f _SC / 2) to form the digital signal for forming the video head switching signal pulse. It is designed to output a mono-multi signal (D-MM).

The digital mono-multi signal is output to the VH-SW-P generation circuit 7, and this VH-SW-P signal is generated.
The SW-P generation circuit 7 is connected to the output terminal 15 and the microcomputer 10. As a result, the video head switching signal pulse from the V / H-SW-P generation circuit 7 is input to the microcomputer 10.

Further, the above-mentioned microcomputer 10 has a SYNC-SEP up / down counter circuit 17 (hereinafter, SYNC-SEP
Called circuit 17. ) Is connected, and this SYNC-SEP
The circuit 17 has a composite sync signal (COMPOSIT-SYN
C) is inputted via the input terminal 19, and the counting signal (f _SC / 2) outputted to the above-mentioned D-MM counter circuit 6 is inputted. Then, the SYNC-SEP circuit 17 separates the horizontal sync signal (H-SYNC) and the vertical sync signal (V-SYNC) from the composite sync signal and the count signal (f _SC / 2), and outputs the horizontal sync signal. Shows H-SYNC SEP pulse and V-SYNC S shows vertical sync signal
EP pulse and is output.

The above-mentioned SYNC-SEP circuit 17 has an up / down counter inside, and this up / down counter integrates the count signal (f _SC / 2) at the rising edge of the composite sync signal, and at the falling edge thereof. It is designed to subtract the counting signal (f _SC / 2). When the integrated value is 4 counts or more, the H-SYNC SEP pulse is output, and when the integrated value is 40 counts or more, the V-SYNC SEP pulse is output. ing.

The SYNC-SEP circuit 17 described above includes an H-SYNC SEP terminal 17a that outputs an H-SYNC SEP pulse and a V-SYNC SEP.
It has a V-SYNC SEP terminal 17b for outputting a pulse, and the V-SYNC SEP terminal 17b is connected to the microcomputer 10. Then, the microcomputer 10 causes the time difference of the rising time of the pulse which is the phase difference between the H-SYNC SEP pulse from the V-SYNC SEP terminal 17b and the video head switching signal pulse from the V / H-SW-P generation circuit 7. Is calculated, and the set value output to the counter decoder 8 is determined so that this time difference becomes the predetermined time t _v .

Further, the microcomputer 10 is connected to an electrically erasable and rewritable E ² PROM 9. This E ² PROM 9 is designed to store the set value of the digital mono-multi signal decided by the microcomputer 10.When the microcomputer 10 is reset, the set value is output from this E ² PROM 9. Has become.

The operation of the head adjusting device having the above configuration will be described below with reference to the timing charts of FIGS. 4 and 5.

First of all, for example, a VHS standard tape is prepared,
This tape is reproduced by a magnetic recording / reproducing apparatus. On this occasion,
The D-FG signal (FIG. 4A) is input to the D-FG counter 4 from the pulse generator provided on the drum via the input terminal 2, and the D-FG signal (A in FIG. 4) is input.
Will output 24 pulses per revolution of the drum.

The D-FG counter 4 counts the D-FG signal with a fixed position of the rotating drum as a reference 0 °. On the other hand, D-
To the FG counter 4, a D-PG signal (B in the figure) that outputs one pulse for one rotation of the drum is input through the input terminal 1, and the D-PG signal (B in the figure) is a D-PG signal. The count value of the D-FG signal (A in the figure) counted by the FG counter 4 is reset. As a result, the trigger pulse generating circuit 3 including the D-FG counter 4 and the decoder 5 has a 12-value when the D-FG signal (A in the same figure) has a count of 0 and when the reference 0 ° is rotated by 180 °. In the case of and, the trigger pulse is formed.

The trigger pulse is output to the D-MM counter circuit 6 and the V · H-SW-P generation circuit 7, and the D-MM counter circuit 6 uses the trigger pulse to generate a count signal (f _SC / 2).
Will be executed up to the limit count number of 65536. Then, this counting is executed until the count value matches the set value of the counter decoder 8 set in advance by the microcomputer, and when the count value matches, the count value is reset and the digital mono-multi signal (C in the same figure) Output is stopped, and counting and output wait until the next trigger pulse is input.

The above digital mono-multi signal (C in the same figure) is VH
The signal is output to the -SW-P generation circuit 7 and the flip-flop of the VH-SW-P generation circuit 7 is set to the H level. This V
In the H-SW-P generation circuit 7, the flip-flop alternately outputs the H level and the L level for each input of the digital mono-multi signal, and outputs the video head switching signal pulse (D in the figure) to the H level and the L level. It will be formed with. The video head switching signal pulse (D in the figure) is output from the output terminal 15 to the outside and also to the microcomputer 10.

On the other hand, a V-SYNC SEP pulse (E in the figure) is input to the microcomputer 10 and this V-SYNC SEP pulse (E in the figure) is formed by the SYNC-SEP circuit 17.

That is, the SYNC-SEP circuit 17 receives the composite sync signal (FIG. 5A) and the count signal (f _SC / 2), and the count signal (f _SC / 2) is the composite sync signal ( At the rising edge of (A), the up / down counter integrates and the integrated value (B) is increased, while at the falling edge of the composite sync signal (A), the integrated value (B) is subtracted. Will be reduced.

At this time, the composite sync signal (A in the figure) has a vertical sync signal and a horizontal sync signal, and a vertical sync signal having a “H” duty of about 28 μsec has an “H” duty of about 4.7 μsec. Is sufficiently longer than the horizontal synchronizing signal having Therefore, the SYNC-SEP circuit 17 uses this difference in duty to make H-SYNC as a horizontal synchronization signal when the integrated value (B in the figure) becomes 4 counts or more.
The SEP pulse (C in the figure) is output from the H-SYNC SEP terminal 17a. On the other hand, when the integrated value (B in the figure) becomes 40 counts or more, a V-SYNC SEP pulse (D in the figure) is output from the V-SYNC SEP terminal 17b as a vertical synchronization signal. Then, this output is finished 4 counts before the completion of the fall of the integrated value (B in the figure).

As a result, the V-SYNC SEP pulse (D in the figure) becomes
In the case of the C method, the composite sync signal (A in the figure) is output to the microcomputer 10 with a delay of 22.35 μsec, which is 40 counts more than the actual vertical sync signal. Therefore, the microcomputer 10 sends the above-mentioned V-SYNC SEP pulse (D in the figure) to 40
The calculation is performed with the count corrected. In addition, between the microcomputer 10 and the SYNC-SEP circuit 17,
By providing a circuit to correct the 0 count, the microcomputer 10
The correction by may be unnecessary.

 Next, the adjustment operation will be described.

The video head switching signal pulse (D in FIG. 4) has a predetermined time t with respect to the V-SYNC SEP pulse (E in the same figure) whose rising and falling edges are obtained from the vertical synchronizing signal.
_v Must be set to the position that precedes it. Therefore,
When adjusting to the above-mentioned predetermined time t _v , the correction time amount T _0, which is the time from the rise to the fall of the digital mono-multi signal (C in the figure) that forms the video head switching signal pulse (D in the figure) Will be adjusted.

That is, the microcomputer 10 calculates the time difference of the rising time of the pulse, which is the phase difference between the input video head switching signal pulse (D in the figure) and the V-SYNC SEP pulse. The predetermined time t _v stored in 10 is compared. Then, based on the comparison result, the correction time amount T ₀ of the digital mono-multi signal is increased / decreased in increments of one step, and the increase / decrease is repeated until the time difference matches the predetermined time t _v .

At this time, for example, when the V-SYNC SEP pulse (F in the figure) is delayed by A time from the reference V-SYNC SEP pulse (E in the figure), the correction time amount T ₀ increases by one step unit. Then, the correction time amount T ₀ + A obtained by adding A time to the reference correction time amount T ₀ is determined as the set value. Then, by outputting this set value to the counter decoder 8, the D-MM counter circuit 6 outputs a digital mono-multi signal (G in the figure) having the correction time amount T ₀ + A. . As a result, the V · H-SW-P generation circuit 7 outputs a video head switching signal pulse (H in the figure) that precedes the V-SYNC SEP pulse (F in the figure) by a predetermined time t _v .

On the other hand, for example, when the V-SYNC SEP pulse (I in the figure) is preceded by B time from the reference V-SYNC SEP pulse (E in the figure), the correction time amount T ₀ is reduced by one step unit. , so that the correction amount of time from the correction amount of time T ₀ as a reference B time is subtracted T ₀ -B is determined as the set value. Then, by outputting this set value to the counter decoder 8, the D-MM counter circuit 6 causes the digital mono-multi signal having the above-mentioned correction time amount T ₀ -B (J in the same figure).
Will be output. As a result, the V / H-SW-P generation circuit 7 causes the video head switching signal pulse (K in the figure) that precedes the V-SYNC SEP pulse (I in the figure) by a predetermined time t _v .
Will be output.

In this way, the correction time amount T ₀ + A · which becomes the predetermined time t _v
When T ₀ −B is determined, the microcomputer 10 determines the correction time amount.
T ₀ + A · T ₀ −B will be stored in the E ² PROM 9. Then, the correction time amount T ₀ + A · T ₀ stored in this E ² PROM 9
-B will be used as a set value for subsequent adjustments.

As described above, the head adjusting device of the present embodiment is
Reference numeral 10 calculates a V-SYNC SEP pulse and a video head switching signal pulse, and adjusts the calculated value by adjusting the calculated value to a predetermined time t _v . Therefore, all the adjustment work is performed by the microcomputer 10, and the burden on the operator is eliminated. Then, the elimination of the burden at the time of adjustment leads to the improvement of production efficiency.

The video head switching signal pulse is formed by a digital mono-multi signal output from the D-MM counter circuit 6, and the digital mono-multi signal is output via the microcomputer 10. 8
And the count value of the count signal (f _SC / 2). Therefore, the video head switching signal pulse is all formed by digital signals,
The output is always stable without being affected by voltage fluctuations due to the pattern state, environmental changes, disturbances such as vibration during transportation, and changes over time.

Further, the set value output from the counter decoder 8 is stored in the E ² PROM 9 connected to the microcomputer 10. Therefore, the head adjustment device having this E ² PROM9
Even if the microcomputer 10 is reset due to a power outage, etc.
It will be possible to return immediately.

The adjustment to the predetermined time t _v in this embodiment is performed by the correction time amount T ₀
However, the present invention is not limited to this, and the DOC detection pulse from the DOC detection pulse generation circuit 18 of the reproduced video envelope (M in FIG. 4) (O in FIG. 4). ) May be used.

That is, in the reproduced video envelope (M in the figure) input through the input terminal 20, there is a time t at the portion where the reproduced video envelopes in the 1ch and 2ch (M in the figure) disappear.
A pulse occurs at _DP1 and time t _DP2 . At this time, the DOC detection pulse generation circuit 18 has the time t _DP1 · t _DP2 described above.
The DOC detection pulse (O in the figure) is output to the microcomputer 10, and the microcomputer 10 outputs each time t _{DP1 of the} DOC detection pulse (O in the figure).
• Add t _DP2 to the correction time amount T ₀ and change the video head switching signal pulse (N in the same figure) in a state where it is significantly deviated to an appropriate video head switching signal pulse (L in the same figure).

As a result, the head adjusting device can perform the adjustment from the video head switching signal pulse (L in the figure) to the predetermined time t _v, and the time required for the adjustment can be shortened.

〔The invention's effect〕

As described above, the video head switching signal pulse generating means according to claim 1 corrects the count value at which the mono-multi generating means starts counting when the trigger pulse is input until the count value matches the set value from the adjusting means. The control means outputs the set value to the monomulti generating means, the set value increasing / decreasing means capable of increasing / decreasing the set value, and the storing means capable of storing the set value. It is composed of and.

As a result, by determining the amount of correction time with the count value and set value consisting of digital signals, it is possible to use a multi-multi device that does not fluctuate due to environmental changes such as pattern status and temperature, changes over time, and external disturbances such as vibration during transportation. The signal makes it possible to output a stable video head switching signal pulse.

In the video head switching signal pulse generating means according to the second aspect of the invention, as described above, the count value at which the mono-multi generating means starts counting when the trigger pulse is input matches the set value from the adjusting means. Up to the correction time amount, and the adjusting means outputs a vertical synchronizing signal detecting pulse from the composite synchronizing signal to the synchronizing signal separating means, the vertical synchronizing signal detecting pulse and the video head switching signal pulse are predetermined. The configuration is composed of control means for increasing / decreasing the set value so as to have a phase difference, and storage means capable of storing the set value.

As a result, as in the case of claim 1, by determining the correction time amount by the count value and the set value consisting of digital signals, environmental changes such as the state of the pattern and temperature, changes over time, and vibration during transportation. It becomes possible to output a stable video head switching signal pulse by a mono-multi signal that does not fluctuate due to disturbance such as.

Further, since the control means increases or decreases the set value so that the vertical sync signal detection pulse and the video head switching signal pulse have a predetermined phase difference, the set value is all adjusted by the control means. The effect that the burden on the operator at the time of adjustment can be eliminated and the production efficiency can be improved.

[Brief description of drawings]

1 and 2 show an embodiment of the invention of claim 1. FIG. 1 is a block diagram of a head adjusting device. FIG. 2 is a timing chart of signals of the head adjusting device. FIGS. 3 to 5 show an embodiment of the invention of claim 2. FIG. 3 is a block diagram of the head adjusting device. FIG. 4 is a timing chart of signals of the head adjusting device. FIG. 5 is a timing chart when separating the composite synchronizing signal. FIG. 6 and FIG. 7 show a conventional example. FIG. 6 is a block diagram of the head adjusting device. FIG. 7 is a timing chart of signals of the head adjusting device. 3 is a trigger pulse generation circuit (trigger pulse generation means),
6 is a D-MM counter circuit (mono-multi generation means), 7 is a VH-SW-P generation circuit (video head switching signal pulse generation means), 10 is a microcomputer (control means), 11 is a down switch (set value). (Increase / decrease means), 12 is an up switch (set value increase / decrease means), 9 is E ² PROM (storage means), 17 is SYNC-SE
It is a P circuit (synchronization signal separating means).

Claims (2)

(57) [Claims] 1. Trigger pulse generation means for outputting a trigger pulse based on a drum frequency generation signal and a drum phase detection signal, and mono-multi generation for outputting a mono-multi signal having a correction time amount from the time of inputting the trigger pulse. A head adjusting device for a magnetic recording / reproducing apparatus, which comprises: means, adjusting means for adjusting the correction time amount, and video head switching signal pulse generating means for forming and outputting a video head switching signal pulse with a mono-multi signal, The mono-multi generation means is adapted to set the correction time amount until the count value that starts counting when the trigger pulse is input matches the set value from the adjustment means. From the control means for outputting the set value, the set value increasing / decreasing means capable of increasing / decreasing the set value, and the storing means capable of storing the set value. It has Tsu head adjustment apparatus of a magnetic recording and reproducing apparatus according to claim. 2. Trigger pulse generation means for outputting a trigger pulse based on a drum frequency generation signal and a drum phase detection signal, and mono-multi generation for outputting a mono-multi signal having a correction time amount from the time of input of the trigger pulse. A head adjusting device for a magnetic recording / reproducing apparatus, which comprises: means, adjusting means for adjusting the correction time amount, and video head switching signal pulse generating means for forming and outputting a video head switching signal pulse with a mono-multi signal, The mono-multi generation means is designed to set the amount of correction time until the count value that starts counting when the trigger pulse is input matches the set value from the adjustment means. A sync signal separating means for outputting a signal detection pulse, a vertical sync signal detection pulse and a video head switching signal pulse are provided. Head adjustment apparatus of a magnetic recording and reproducing apparatus for and control means for increasing or decreasing the set value so as to have a phase difference, characterized in that it is the setting value from the storable storage means.