JPH03266514A - Thick film delay line - Google Patents

Thick film delay line

Info

Publication number
JPH03266514A
JPH03266514A JP6626990A JP6626990A JPH03266514A JP H03266514 A JPH03266514 A JP H03266514A JP 6626990 A JP6626990 A JP 6626990A JP 6626990 A JP6626990 A JP 6626990A JP H03266514 A JPH03266514 A JP H03266514A
Authority
JP
Japan
Prior art keywords
inductor
thick film
base
delay line
gnd
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6626990A
Other languages
Japanese (ja)
Inventor
Hiroaki Komoriya
小森谷 宏晃
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nidec Copal Electronics Corp
Original Assignee
Copal Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Copal Electronics Co Ltd filed Critical Copal Electronics Co Ltd
Priority to JP6626990A priority Critical patent/JPH03266514A/en
Publication of JPH03266514A publication Critical patent/JPH03266514A/en
Pending legal-status Critical Current

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  • Filters And Equalizers (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

PURPOSE:To obtain a long delay time by forming an inductor and a capacitor to both sides of an insulation base and connecting the components through a throughhole of the base. CONSTITUTION:GND 6a, 6b, a dielectric 7 and an inductor 8 are subject to multi-layer print and baked onto a front side and a rear side of an insulating base 5 by using a thick film material, and a throughhole 9 to the inner side face of which a conductive material is coated or packed is formed from the front side to the rear side of the base. Thus, it is possible to connect the inductor pattern of one side of the base 5 to a pattern provided to the other side through the throughhole 9a made to the base 5, and the circuit comprising the inductor (L) and the capacitor (C) is increased and expanded, Thus, the entire delay time is increased.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は厚膜型遅延線に関する。特に電子機器のデジタ
ル信号を高速で演算処理するコンピュータ機器等の信号
のタイミング調整用に使用される遅延線に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to thick film delay lines. In particular, the present invention relates to delay lines used for timing adjustment of signals in computer equipment and the like that process digital signals of electronic equipment at high speed.

(従来の技術) 従来より使用されている厚膜型遅延線について添付第3
図を参照して説明する。
(Prior art) Attached No. 3 regarding the conventionally used thick film delay line
This will be explained with reference to the figures.

絶縁性基板18の片面にGND 17を印刷焼成し、そ
の上面に誘電体16とさらにインダクタ15を印刷焼成
し、GND 17とインダクタ15とにそれぞれリード
端子19.20を接続し、これらを絶縁性樹脂14でコ
ーテングした構成が一般的であった。
A GND 17 is printed and fired on one side of the insulating substrate 18, a dielectric 16 and an inductor 15 are printed and fired on the upper surface, and lead terminals 19 and 20 are connected to the GND 17 and the inductor 15, respectively, and these are insulated. A configuration coated with resin 14 was common.

(発明の解決しようとする課題) 従来例の遅延線では片面のみにL及びCの関係素子が形
成されているため、全体の遅延時間は、その物理的特性
に起因して、最大遅延時間が限られており、長い遅延時
間を得ることが困難である等の問題点があった。
(Problems to be Solved by the Invention) In the conventional delay line, the L and C related elements are formed only on one side, so the overall delay time is limited to the maximum delay time due to its physical characteristics. However, there were problems such as difficulty in obtaining a long delay time.

本発明は前記の問題点を解決することを目的とするもの
であり、そのために絶縁基板の両面にL及びCの関係素
子を形成し、これらの素子を基板を介して貫通孔により
接続した構成を提供するものである。
The present invention aims to solve the above-mentioned problems, and for this purpose, it has a structure in which L and C related elements are formed on both sides of an insulating substrate, and these elements are connected through a through hole through the substrate. It provides:

(課題を解決するための手段) 課題を解決するための手段について、本発明の実施例を
図示する図面を参照して説明する。
(Means for Solving the Problems) Means for solving the problems will be described with reference to drawings illustrating embodiments of the present invention.

すなわち、絶縁性を宥する基板5の表面並びに裏面にそ
れぞれ厚膜材料を用いてGND6a、6b、lla、l
lb、誘電体7,12、インダクタ8,13を多層印刷
、焼成し、導電性を有する材料を用いてその内側面を塗
布するか又はその内側に充填してなる貫通孔9を表面か
ら裏面へと形成してなる厚膜型遅延線であり、基板5の
表面と裏面とに同一又は異った遅延時間を有するパター
ンを印刷焼成してなるものである。
That is, GNDs 6a, 6b, lla, l are connected using thick film materials on the front and back surfaces of the substrate 5, which provide insulation properties.
lb, dielectrics 7, 12, and inductors 8, 13 are multi-layer printed and fired, and a conductive material is applied to the inner surface or filled inside to form a through hole 9 from the front surface to the back surface. This is a thick film type delay line formed by printing and baking patterns having the same or different delay times on the front and back surfaces of the substrate 5.

(作 用) 基板に設けたスルーホールにより基板片面のインダクタ
パターンとを他面に設けたパターンと縦列接続すること
が可能であるから、全体的にLとCとよりなる回路を増
加、拡大せしめ、全体の遅延時間を増加させるので遅延
線の性能を向上させることが可能である。
(Function) Since it is possible to connect the inductor pattern on one side of the board in series with the pattern on the other side using the through hole provided on the board, the overall circuit consisting of L and C can be increased and expanded. , it is possible to improve the performance of the delay line as it increases the overall delay time.

(実施例) 以下添付図面を参照して本発明に係る遅延線の実施例を
説明する。第1図乃至第2図は本発明の一実施例を図示
する。詳説すれば、第1図(A)は厚膜型遅延線の正面
図、同(B)は側面図、第2図(A)はコーテング以前
の内部構造を示す表面図、同CB)は裏面図、同(C)
は側面図である。
(Example) Examples of the delay line according to the present invention will be described below with reference to the accompanying drawings. 1-2 illustrate one embodiment of the invention. To explain in detail, Figure 1 (A) is a front view of the thick film delay line, Figure 2 (B) is a side view, Figure 2 (A) is a front view showing the internal structure before coating, and Figure 2 (CB) is a back view. Figure, same (C)
is a side view.

絶縁性基板5は主としてセラミック基板等よりなり、8
1図に図示のようにその表面にはGND層6a、6bを
印刷焼成する。このGND層は例えばAg又はCu系か
らなる厚膜材料よりなるものである0次に比誘電率ε5
=10を有する焼結型ガラスよりなる誘電体7を印刷焼
成し、更にその上面にAg又はCu系の導体であるイン
ダクタ層8を印刷焼成し、その後入力端子1.GND端
子2a、2b、出力端子3を第2図に図示のように、そ
れぞれのパターンにハンダなどにより接続する。
The insulating substrate 5 is mainly made of a ceramic substrate, etc.
As shown in FIG. 1, GND layers 6a and 6b are printed and fired on the surface. This GND layer is made of a thick film material made of, for example, Ag or Cu, and has a zero-order dielectric constant ε5.
A dielectric material 7 made of sintered glass having a diameter of =10 is printed and fired, and an inductor layer 8 made of an Ag or Cu-based conductor is printed and fired on its upper surface, and then input terminals 1. The GND terminals 2a, 2b and the output terminal 3 are connected to their respective patterns by solder or the like as shown in FIG.

第2図(B)は背面図(第2図(A)の裏面図であり、
基板5の背面には、GND層11a。
FIG. 2(B) is a rear view (a back view of FIG. 2(A),
A GND layer 11a is provided on the back surface of the substrate 5.

11b、誘電体12、インダクタ13をそれぞれ第2図
CA)におけると同一手法により印刷、焼成する。
11b, dielectric 12, and inductor 13 are printed and fired using the same method as in FIG. 2CA).

次に本発明の特徴であるスルーホールの構成についての
べる。
Next, the structure of the through hole, which is a feature of the present invention, will be described.

先ず絶縁性基板5の正面(52図(A))のインダクタ
8の終端にスルーホール9aを穿設して、背面(第2図
)B)のインダクタ13のスルーホール9bまで貫通さ
せる。スルーホール9a、9bの内側面に導電性材料を
塗布するか又は充填する。これによりインダンフタ8と
インダクタ13とはスルーホール9a、9bを介して接
続される。更にインダクタ13の終端を出力端子3へ接
続する。この様に基板5の両面にL及びC関係素子を配
設し、これらをスルーホール9a。
First, a through hole 9a is bored at the end of the inductor 8 on the front side of the insulating substrate 5 (FIG. 52(A)), and is passed through to the through hole 9b of the inductor 13 on the back side (FIG. 2B). The inner surfaces of the through holes 9a, 9b are coated or filled with a conductive material. Thereby, the inductor lid 8 and the inductor 13 are connected via the through holes 9a and 9b. Furthermore, the terminal end of the inductor 13 is connected to the output terminal 3. In this way, L and C related elements are arranged on both sides of the substrate 5, and these are connected to the through holes 9a.

9bを介して接続した構成であるから、L、!:Cとよ
りなる遅延回路を増加せしめ、遅延線の性能向上を計る
ものである。
Since the configuration is connected via 9b, L,! The purpose is to increase the number of delay circuits consisting of C and C, thereby improving the performance of the delay line.

尚、本発明に係る遅延線は、関係部材配設完了時にコー
ティング4を施し、外力より保護されるように構成する
ことは勿論である。
It goes without saying that the delay line according to the present invention can be protected from external forces by applying a coating 4 upon completion of the arrangement of related members.

又基板5の表面と裏面とに互いに同一又は異った遅延時
間を有するパターンを印刷、焼成することができること
は勿論である。
It goes without saying that patterns having the same or different delay times can be printed and fired on the front and back surfaces of the substrate 5.

(発明の効果) 本発明によれば、絶縁性基板の両面にLとCの関係素子
で形成するパターンを構成し、スルーホールにより両面
に形成したパターンを連結してなるものであるから、厚
さは異なるが、外形寸法がほぼ同一のままであっても、
その遅延時間特性は、従来例の一面パターン形成方式の
ものを並列に配設して使用するものに比較して、数倍の
向上を計ることができると共に両面を利用することによ
り従来のものを並列に使用するものに比較し小型化を計
るものである等の効果がある。
(Effects of the Invention) According to the present invention, patterns formed of L and C related elements are formed on both sides of an insulating substrate, and the patterns formed on both sides are connected by through holes. Although the size is different, even though the external dimensions remain almost the same,
Its delay time characteristics can be improved several times compared to conventional one-sided pattern forming systems arranged in parallel, and by using both sides, It has the advantage of being more compact than those used in parallel.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(A)は本発明に係る遅延線の正面図。 第1図(B)は側面図。 第2図(A)はコーティング前の第1図(A)の正面図
、第2図CB)は第1図(A)の背面図、第2図(C)
は第2図(A)の側面図。 第3図は従来例の厚膜型遅延線の斜視図。 l・・・入力端子、2a、2b・・・GND端子、3・
・・出力端子、4・・・コーティング、5・・・絶縁性
基板、6a、6b、lla、llb・・・GND層、7
.12・・・誘電体、8.13・・・インダクタ、9a
、9b・・・スルーホール
FIG. 1(A) is a front view of a delay line according to the present invention. FIG. 1(B) is a side view. Figure 2 (A) is a front view of Figure 1 (A) before coating, Figure 2 CB) is a back view of Figure 1 (A), Figure 2 (C)
is a side view of FIG. 2(A). FIG. 3 is a perspective view of a conventional thick-film delay line. l...Input terminal, 2a, 2b...GND terminal, 3.
...Output terminal, 4...Coating, 5...Insulating substrate, 6a, 6b, lla, llb...GND layer, 7
.. 12... Dielectric, 8.13... Inductor, 9a
, 9b...Through hole

Claims (2)

【特許請求の範囲】[Claims] 1.絶縁性を有する基板表面並びに裏面にそれぞれ厚膜
材料を用いてGND、誘電体、インダクタを多層印刷、
焼成し、導電性を有する材料を用いてその内側面を塗布
するか又はその内側に充填してなる貫通孔を表面から裏
面へと形成してなる厚膜型遅延線。
1. Multilayer printing of GND, dielectric, and inductor using thick film materials on the front and back sides of the insulating substrate.
A thick film delay line formed by firing and coating the inner surface with a conductive material or filling the inner surface with through holes formed from the front surface to the back surface.
2.表面と裏面とに同一又は異った遅延時間を有するパ
ターンを印刷、焼成してなる請求項1記載の厚膜型遅延
線。
2. 2. The thick film delay line according to claim 1, wherein patterns having the same or different delay times are printed and fired on the front and back surfaces.
JP6626990A 1990-03-15 1990-03-15 Thick film delay line Pending JPH03266514A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6626990A JPH03266514A (en) 1990-03-15 1990-03-15 Thick film delay line

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6626990A JPH03266514A (en) 1990-03-15 1990-03-15 Thick film delay line

Publications (1)

Publication Number Publication Date
JPH03266514A true JPH03266514A (en) 1991-11-27

Family

ID=13310959

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6626990A Pending JPH03266514A (en) 1990-03-15 1990-03-15 Thick film delay line

Country Status (1)

Country Link
JP (1) JPH03266514A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6277262A (en) * 1985-07-26 1987-04-09 アシエ エ ウティヤージュ プジョ Fixing device for sliding member with latch head used for seat belt device for safety

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6277262A (en) * 1985-07-26 1987-04-09 アシエ エ ウティヤージュ プジョ Fixing device for sliding member with latch head used for seat belt device for safety

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