JPH03263110A - Electronic apparatus - Google Patents

Abstract

PURPOSE:To prevent the occurrence of a runaway of a control circuit of a main body by resetting the whole electronic apparatus, in the case an external storage means is attached and detached in the course of turning on a power source. CONSTITUTION:An external memory card 1 being an external storage means is connected to an address bus, a data bus and other control signal of a main body side electronic circuit O. When attaching/detaching detecting terminals 3, 4 come into contact with each other, since the terminal 4 of the memory card 1 side is in a GND level, a voltage value of the attaching/detaching detecting terminal 3 fixed to 5V until that time is varied to the GND level, and this variation is detected by flip-flops 7, 8 of the inside of an electronic apparatus. In such a way, in the case attachment and detachment of the memory card 1 are detected in the course of turning on a power source, the electronic apparatus is reset. In such a way, a runaway of the device can be prevented surely.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to electronic equipment, and particularly to electronic equipment using removable external storage means using semiconductor memory.

[Prior Art] Conventionally, removable external memories such as font cartridges, expansion memory bags, and control ROMs have been used.
A memory card containing a built-in card, memory card, etc. is used. These memo IJ71 are directly electrically connected to a control circuit 74 inside the device via a bus 79 and a control line 76, as shown in FIG.

[Problems to be Solved by the Invention] However, in the conventional example described above, when the memory is inserted or removed while the power is on, the control circuit of the main body is adversely affected by noise such as chattering generated from the coupling part, resulting in malfunction or malfunction of the control circuit. There is a risk of a runaway.

As a countermeasure against this, it is usually prohibited to insert or remove memory while the power is turned on, but this is inconvenient for the user and may cause problems if memory is inserted or removed by mistake when the power is turned on. There is a problem that the equipment may break down.

In order to solve this problem, a conventional method has been used in which a buffer is provided between the external memory mounting means and the main body of the electronic device, and the buffer is rendered inactive depending on the state of the external memory mounting means.

However, this method requires a buffer to be provided between the main electronic device and the external memory.

In addition, in order to turn on/off the buffer, a detection means for detecting whether the external memory is completely installed or removed, such as an attachment/detachment switch, a cover switch for the external memory storage section, etc., is provided in one main body. An internal control circuit must check the state of this switch and control the buffer.

Therefore, parts for the external memory such as an attachment/detachment switch, an external memory storage cover, and a cover switch are required, which causes an increase in the cost of the main device and has the disadvantage that the control program for the main device becomes complicated.

Yet another conventional example is a method in which when an external memory is attached or removed while the main device is powered on, the main device is once reset.

In this method, the conditions for setting the reset state (
A cartridge type connector is used to detect whether the external memory is installed or removed.For the external memory, an L-shaped contact 81 as shown in Fig. 8 is provided, and the connector on the main body side is used. The terminals 82 adjacent to each other are configured to contact each other and conduct electricity when an external memory is attached or removed.

However, this method requires two or more detection connector terminals, and can only be applied to external memories using card edge type connectors.

Furthermore, it is possible to use a mechanical switch to detect the attachment and detachment of external memory and reset the main unit, but this increases the cost of the main unit because the switch is provided and high precision is required for the switch mounting position. It's connected.

SUMMARY OF THE INVENTION An object of the present invention is to solve one or more problems and provide a configuration that can easily and inexpensively control equipment depending on the state of memory card attachment.

[Means for Solving the Problems] In order to solve the above problems, in the present invention, in an electronic device using a removable external storage means using a semiconductor memory, data input/output with the external storage means is provided. A configuration is adopted in which a means for electronically detecting the attachment state of the external storage means is provided in the interface circuit, and the entire electronic device is reset if the external storage means is attached or removed while the power is turned on.

[Operation] According to the above configuration, when the electronic detection means provided in the interface circuit that performs data input/output with the external storage means detects attachment or detachment of the external storage means while the power is turned on. , reset electronic devices.

[Example] Hereinafter, the present invention will be described in detail based on the example shown in the drawings.

First Embodiment FIG. 1 is a block diagram showing the configuration of an electronic device adopting the present invention. In FIG. 0, reference numeral 1 is an external memory card;
Inside is a control ROM for controlling electronic devices,
It is constituted by one or a combination of an expansion RAM and a character generator ROM, and is connected to the address bus, data bus, and other control signals of the electronic circuit 0 on the main body side.

Reference numeral 2 is the main unit side connector for external memory, which may be any type of connector such as card edge type or bottle type. Reference numerals 3 and 5 are main unit side connector terminals, reference 4.
and 6 are memory card side connector terminals, and in the present invention, the Nth terminals 3i5 and 4 are used as attachment/detachment detection terminals. Terminal 4 is connected to GND level (terminal 5) inside the card.

Terminal 3 is connected to terminal 4 on the external memory side when connecting to memory card l.

When the memory card 1 is connected to an electronic device, the power terminals 515 and 6 are usually configured to contact the power terminal of the memory card connector 2 before other signal terminals. This configuration is realized by setting the lengths of the terminal 3.4 and the power supply terminal 5.6.

Therefore, when the attachment/detachment detection terminals 3 and 4 come into contact, the voltage value of the terminal 4 on the memory card l side is set to a predetermined value (usually Vcc=5
In the present invention, it is set to GND level when the memory card is inserted.

Inside the main electronic circuit 0, there are provided a control circuit 30 consisting of a microprocessor, memory, etc., a clock generation circuit 9 that generates a reference clock for each circuit, and a reset circuit 13 that resets the control circuit 30 and the entire device.

The attachment/detachment detection terminal 3 is pulled up to a predetermined potential by a resistor R1 and a capacitor CI, and the voltage level of the attachment/detachment detection terminal 3 is detected by a control circuit 30 and simultaneously sent to a reset circuit via the circuit shown at the bottom of the figure. Controls the reset operation of 13. @The voltage of the detachment detection terminal 3 is input to the flip-flops and gate circuits indicated by symbols 7 to 12, which operate in synchronization with the clock of the clock generation circuit 9, and the reset circuit 13 is inputted according to the voltage of the detachment detection terminal 3. The reset operation is controlled.

Next, the reset control of the device in the above configuration will be explained using the timing chart of FIG. 2.

When the attachment/detachment detection terminal 3.4 comes into contact, since the terminal 4 of one memory card is at GND level, R1, CI
As a result, the voltage value of the attachment/detachment detection terminal 3, which was fixed at 5V, changes to the GND level (timing TI).

This change is detected by flip-flops 7 and 8 inside the electronic device. First, the input terminal D1 of the flip-flop 7 changes to the GND level and is sampled by the internal clock 9.

Then, due to the rise of the clock generation circuit 9 after the input DI changes to GND level (=low level), Ql
becomes low level (timing T2).

When Ql becomes low level, the input D of flip-flop 8
2 becomes low level, but the output Q of flip-flop 8
2 must wait until the next rising edge of the cycle of the clock generation circuit 9 for the signal 2 to go low. During this period, the output of the exclusive logic (EXOR) gate 10 which receives the outputs Ql and Q2 of the flip-flops 7 and 8 as inputs is Becomes a high level (
timing T2).

With the rise of the output of the EXOR gate IO, the output of the latch flip-flop 11 changes from low level to high level (timing T2). Then, the output of the flip-flop 11 sets the forced reset terminal of the reset circuit 13 to a low level, operating the reset circuit on the main body side and putting the entire device into a reset state (timing T3).

Flip-flops Ti5 and Ti8 are in the reset state depending on the value of the connection/disconnection detection terminal 3 (high level or low level).
The values of Ql and Q2 are set by the initial setting circuit 12. For example, when the power is turned on with an external memory installed, or in a reset state, the flip-flop 7
The outputs of Q1 and Q2 are both low level, and when the power is turned on without an external memory installed or in a reset state, both Q1 and Q2 are high level (timing T4).

Next, a case where the external memory is removed from the main body will be described. T5 to T8 in FIG. 2 show the timing when the memory card 1 is removed from the memory card connector 2 of the main body electronic circuit O.

When the memory card 1 is removed, the voltage level of the attachment/detachment detection terminal 3, which has been kept at a low level, changes to a high level. This change is detected by flip-flop 7.8, and the output of EXOR gate lO becomes 12092
becomes high level (timing T6).

With the rise of the output of the EXOR gate IO, the *Q3 output of the flip-flop 11 (with an upper bar in the figure; negative logic is indicated by an umbrella in the text below) becomes low level (timing T6), and the forced reset terminal of the reset circuit 13 By setting (REST IN) to low level, the entire electronic device is reset.

The reset circuit 13 includes a flip-flop 7 that is initialized (sets the output of Q3 to a high level) within the reset time.
．． 8, the values of Ql and Q2 are set to high level by the initial setting circuit 12 according to the value of the attachment/detachment detection terminal 3 (high level when no memory card is present) during the reset state. The reset time τ of the reset circuit 13 can be set arbitrarily, and varies depending on the logic of the main unit, but is usually 500 m5ec.
It is desirable that it be above.

As described above, when the memory card 1 is inserted or removed from the main body, by putting the electronic device in the reset state, the main body electronic circuit 0
It is possible to prevent malfunction of the main body electronic circuit O due to chattering that occurs in the address bus, data bus, and other control signals connected to the main body when the memory card is inserted into and removed from the main body.

Note that the high level or low level state of the attachment/detachment detection terminal 3 can be detected by the control circuit 30, and based on this, the control circuit 30 determines the presence or absence of the memory card l.

According to the above embodiment, by detecting the instant of a change in the state of the signal line that detects whether an external memory is attached or not, and putting the electronic device into the reset state, there is no need to use a mechanical switch or a new connector terminal. , it is possible to protect the device from runaway when external memory is installed or removed.

Furthermore, by adding the circuit of the present invention as part of a custom LSI, there is no increase in the cost of parts, and it can be realized without changing the mounting space for the parts at all.

Second Embodiment FIG. 3 shows an embodiment of an electronic device in which a plurality of memory cards can be mounted.

In FIG. 3, two memory cards 1 and 15 can be mounted. In FIG. uses the terminal 18 of the memory card connector 16 on the main body side.

Change in state of voltage value of attachment/detachment detection terminal 3 (5V or Ov)
is detected by flip-flop 7.8 and EXOR gate 1
0, it is output as a pulse and latched by the flip-flop 11. In addition, the state change of the voltage value of the attachment/detachment detection terminal 18 (
5V or OV) is detected by flip-flops 20 and 21, outputted as a pulse by exclusive logic gate 22, and latched by flip-flop 11.

Since the flip-flop 11 latches the output pulse of the EXOR gate 1O122 through the OR gate 9, the reset circuit 1
3 can be operated.

Next, the operation of the above configuration will be explained using the timing chart of FIG. 4. FIG. 4 shows a case where the power is turned on with the memory card 1 not mounted and the memory card 15 mounted.

When the attachment/detachment detection terminal 3.4 comes into contact, the terminal 4 of one memory card is at GND level, so R1, CI
As a result, the voltage value of the attachment/detachment detection terminal 3, which was fixed at 5V, changes to the GND level (timing Tl).

This change is detected by flip-flops 7i5 and 8 inside the electronic device. First, the input terminal DI of the flip-flop 7 changes to the GND level and is sampled by the internal clock 9. And input DI is GND
When the clock generation circuit 9 rises after changing the level (=low level), Ql becomes low level (timing T2).

When Ql becomes low level, the input D of flip-flop 8
2 becomes low level, but the output Q of flip-flop 8
2 must wait until the next rising edge of the cycle of the clock generation circuit 9 for the signal 2 to go low. During this time, the output of the exclusive logic (EXOR) gate 10 whose inputs are the outputs Q1 and 02 of the flip 20 knobs 7 and 8. is at a high level (
timing T2).

By the rising edge of the output of EXOR gate lO.

The output of the latch flip-flop 11 changes from low level to high level (timing T2). The output of this flip-flop 11 causes a reset circuit 13
The forced reset terminal of the device is set to a low level to operate the reset circuit on the main body side, and the entire device is brought into a reset state (timing T3).

The flip-flops 7i5 and 7i8 are in the reset state depending on the value of the connection/disconnection detection terminal 3 (high level or low level).
The values of Ql and Q2 are set by the initial setting circuit 12. For example, when the power is turned on with an external memory installed, or in a reset state, the flip-flop 7
The outputs of i5 and 8 are both Ql and Q2 low level, and when the power is turned on without an external memory installed or in a reset state, both Ql and Q2 are high level (timing T4).

This also applies when the electronic device returns from the reset state. Note that the reset output of the reset circuit 13 becomes high level after a predetermined reset time has elapsed (timing T4).

Next, a case where the external memory card 15 is removed from the main body will be described. 1 from the memory card connector 16 of the main body electronic circuit O to the memory card 1 from T5 to T8 in FIG.
The timing is shown when 5 is extracted.

When the memory card 15 is removed, the voltage level of the attachment/detachment detection terminal 18, which has been kept at a low level, changes to a high level. This change is caused by flip-flop 20.
22, and the output of the flip-flop 22 becomes high level for l clocks (timing T6).

With the rise of the output of the flip-flop 22, the Q3 output of the flip-flop 11 becomes low level (timing T6), and the forced reset terminal (RE
The entire electronic device is reset by setting STIN) to a low level. The reset circuit 13 is initialized (the output of Q3 is set to high level) within the reset time.

During the reset state of the flip-flops 20 and 21, the values of Ql and Q2 are set to high level by the initial setting circuit 23 according to the value of the attachment/detachment detection terminal 18 (high level when no memory card is present). The reset time of the reset circuit 13 can be set arbitrarily and varies depending on the logic on the main body side, but it is usually desirable to set it to 500 a+sec or more.

With the above configuration, even in an apparatus using a plurality of memory cards, substantially the same effects as those of the embodiment described above can be obtained.

Third Embodiment In the embodiments described above, a change in the state of the memory card is detected and a pulse output is input to the forced reset terminal of the reset circuit 13 to reset the entire electronic device.
Next, a method of resetting the entire device using a method other than the forced reset terminal will be described.

Usually, a capacitor C3 is added to the reset circuit 13 externally for setting the reset time τ.

Even when using the reset circuit 13 without a forced reset terminal, the charge of the capacitor C3 is transferred to the transistor Tri.
The entire system can be reset by forcibly discharging and lowering the potential using resistor R3. This will be explained below using FIGS. 5 and 6.

FIG. 5 shows an example of an electronic device in which a plurality of memory cards can be mounted.

In FIG. 5, two memory cards 1 and 15 can be installed. In the figure, the terminal 3 of the main body side memory card connector 2 is used as the attachment/detachment detection terminal of the memory card 1, and the terminal 18 of the main body side memory card connector 16 is used as the attachment/detachment detection terminal of the memory card 15.

Change in state of voltage value of attachment/detachment detection terminal 3 (5V or OV)
is detected by flip-flop 7.8, EXOR game) 1
0, it is output as a pulse and latched by the flip-flop 11. In addition, the state change of the voltage value of the attachment/detachment detection terminal 18 (
5V or OV) is detected by flip-flops 20 and 21, outputted as a pulse by exclusive logic gate 22, and latched by flip-flop 11.

Since the flip-flop 11 latches the output pulse of the EXOR gate 10.22 through the OR gate 9, the reset circuit 1
3 can be operated.

Next, the operation based on the above configuration will be explained using the timing chart of FIG. 6. FIG. 6 shows a case where the power is turned on with the memory card 1 not mounted and the memory card 15 mounted.

When the attachment/detachment detection terminal 3.4 comes into contact, since the terminal 4 on the memory card L side is at GND level, R1, C1
The voltage value of the attachment/detachment detection terminal 3, which was fixed at 5V, changes to the GND level (timing TI), and this change is detected by the flip-flops 7 and 8 inside the electronic device.

First, the input terminal DI of the flip-flop 7 changes to the GND level and is sampled by the internal clock 9. Then, due to the rise of the clock generation circuit 9 after the human power D1 changes to the GND level (=low level), the Q
l becomes low level (timing T2).

When Ql becomes low level, the input D of flip-flop 8
2 becomes low level, but the output Q of flip-flop 8
It is necessary to wait until the next rising edge of the cycle of the clock generation circuit 9 for the signal 2 to become low level.

During this time, the output of the exclusive logic (EXOR) gate IO which receives the outputs Ql and C2 of the flip 70 knobs 7 and 8 becomes high level (timing T2), EXOR gate IO
The latch flip-flop 1 is activated by the rising edge of the output of
1, the output changes from low level to high level (timing T2), and the output of this flip-flop 11 sets the forced reset terminal of the reset circuit 13 to low level, operates the reset circuit on the main body side, and resets the entire device. (timing T3).

In the flip-flops 7 and 8, the values of Ql and C2 are set by the initial setting circuit 12 according to the value (high level or low level) of the attachment/detachment detection terminal 3 during the reset state.

For example, if the power is turned on with external memory installed, or in the reset state, the outputs of flip-flops 7 and 8 are both Ql and C2 at low level, and the power is turned on with no external memory installed. case,
Alternatively, in the reset state, both Ql and C2 become high level (timing T4), and this also applies when the electronic device returns from the reset state. Note that the reset output of the reset circuit 13 becomes high level after a predetermined reset time (τ) has elapsed (timing T4).

Next, a case where the external memory card 15 is removed from the main body will be described. From the memory card connector 16 of the main body electronic circuit O to the memory card 1 from T5 to T8 in FIG.
The timing is shown when 5 is extracted.

When the memory card 15 is removed, the voltage level of the attachment/detachment detection terminal 18, which has been kept at a low level, changes to a high level. This change is caused by flip-flop 20.
22, and the output of the flip-flop 22 becomes high level for one clock (timing T6).

As the output of the flip-flop 22 rises, the C3 output of the flip-flop 11 becomes low level (timing T6), and the forced reset terminal (RE
The entire electronic device is reset by setting STIN) to a low level.

The reset circuit 13 includes a flip-flop 2 that is initialized (the output of C3 is set to high level) within the reset time.
0.21 is set to the initial setting circuit 2 according to the value of the insertion/removal detection terminal 18 (high level when no memory card is present) during the reset state.
3 sets the values of Ql and Q2 to high level.

The reset time τ of the reset circuit 13 can be set arbitrarily1.
It varies depending on the logic of the main unit, but usually 500 s
It is desirable to set it to ec or more.

With the above configuration as well, substantially the same effects as those of the embodiment described above can be obtained.

[Effect of the Invention J As is clear from the above, according to the present invention, in an electronic device using a removable external storage means using a semiconductor memory, an interface circuit for outputting data with the external storage means is provided. A configuration is adopted in which means is provided for electronically detecting the attachment state of the external storage means, and the entire electronic device is reset when the external storage means is attached or removed while the power is turned on. In other words, if the electronic device installed in the interface circuit that performs data input/output with the external storage device detects that the external storage device is attached or removed while the power is turned on, the electronic device is reset. Regardless of the connector connection method of the storage device, the electronic device can be reset by detecting the moment the external storage device is attached or removed.Therefore, there is no need to provide a switch or other control means, and the device is reliably prevented from running out of control. This has the excellent effect of preventing data destruction.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an attachment/detachment detection circuit of an electronic device adopting the present invention, FIG. 2 is a timing chart diagram of the device of FIG. 1, and FIG. 3 and FIG. FIG. 3 is a block diagram showing the configuration of each attachment/detachment detection circuit according to the embodiment. 4 and 6 are timing charts for the devices shown in FIGS. 3 and 5, FIG. 7 is a block diagram showing a conventional method, and FIG. 8 is an explanatory diagram of a conventional attachment/detachment detection method. 1.15--Memory card 2.16-Memory card connector 3.18--Attachment/detachment detection terminal 4.5--Connector terminal 7.8.11.22--Flip-flop 9...- Clock generation circuit 1O-EXOR game F- 12, 23-Initial setting circuit 13...Reset circuit

Claims (1)

[Scope of Claims] 1) In an electronic device using a removable external storage means using a semiconductor memory, the mounting state of the external storage means is electronically recorded in an interface circuit that performs data input/output with the external storage means. What is claimed is: 1. An electronic device comprising: a means for detecting the external storage means; and a device for resetting the entire electronic device when the external storage means is attached or removed while the power is turned on.