JP2000105616A - Electronic equipment protecting circuit - Google Patents

Electronic equipment protecting circuit

Info

Publication number
JP2000105616A
JP2000105616A JP10274951A JP27495198A JP2000105616A JP 2000105616 A JP2000105616 A JP 2000105616A JP 10274951 A JP10274951 A JP 10274951A JP 27495198 A JP27495198 A JP 27495198A JP 2000105616 A JP2000105616 A JP 2000105616A
Authority
JP
Japan
Prior art keywords
circuit
signal
output
electronic device
power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10274951A
Other languages
Japanese (ja)
Inventor
Shigenobu Maeda
茂伸 前田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP10274951A priority Critical patent/JP2000105616A/en
Publication of JP2000105616A publication Critical patent/JP2000105616A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a low-priced and high-safety electronic equipment protecting circuit by realizing a short-circuit protecting function of load with a simple circuit. SOLUTION: This electronic equipment protecting circuit is provided with a voltage detecting circuit 5 for detecting a load voltage VCC of electronic equipment, a delay circuit 4 for delaying this output for prescribed time, a timer 2 to be started with a VCCON signal showing the ON/OFF of a power source switch and to output the signal after the lapse of prescribed time, and a register 3 to be reset by the VCCON signal for turning on/off a read power source 8 with the output of an output voltage detecting circuit 5 of delay circuit 4 and the timer 2. Short-circuitting between a load power source and GND is detected during and before the operation of electronic equipment and the power source 8 is turned off.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は負荷などのショート
に対する電子機器保護回路に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic device protection circuit against a short circuit such as a load.

【0002】[0002]

【従来の技術】電子機器の負荷や電源のショートによる
部品などの破壊や過熱などの事故を防止するための従来
の保護回路は、その機能を内蔵した電源用ICを採用、
もしくはショートに対して電子機器を保護する専用のI
Cを使用しなければならない等回路設計上の制約が大き
いうえにコストも高かった。
2. Description of the Related Art A conventional protection circuit for preventing an accident such as destruction of components or overheating due to a load of an electronic device or a short circuit of a power supply employs a power supply IC having the function built in.
Or a dedicated I to protect the electronic device against short circuit
C has to be used, and the circuit design has great restrictions and the cost is high.

【0003】[0003]

【発明が解決しようとする課題】本発明の目的は、前述
の問題を解決して、簡単な回路でこのショート保護機能
を実現し、低価格で自由に設計できる電子機器保護回路
を提供することである。
SUMMARY OF THE INVENTION An object of the present invention is to provide an electronic equipment protection circuit which solves the above-mentioned problems, realizes this short-circuit protection function with a simple circuit, and can be freely designed at low cost. It is.

【0004】[0004]

【課題を解決するための手段】この課題を解決するため
に本発明の電子機器保護回路は、電子機器の負荷電圧を
検出する電圧検出回路と、この電圧検出回路の出力を所
定時間遅延する遅延回路と、電子機器の電源をONした
ことを示す電源ON信号で起動し所定時間後出力するタ
イマーと、電源ON信号で読み込み可否を制御され遅延
回路の出力またはタイマーの出力で電圧検出回路の出力
を読み込み電子機器の電源をON/OFFする信号を出
力するレジスタを備え、電子機器の動作中および動作以
前の両方の状態において負荷電源とGND間ショートを
検出し、ショートを検出すると電源をOFFするように
構成される。。
To solve this problem, an electronic equipment protection circuit according to the present invention comprises a voltage detection circuit for detecting a load voltage of an electronic equipment, and a delay for delaying an output of the voltage detection circuit for a predetermined time. A circuit, a timer which is activated by a power-on signal indicating that the power of the electronic device is turned on and outputs after a predetermined time, and a read / write controllability controlled by the power-on signal, and an output of the delay circuit or an output of the voltage detection circuit by an output of the timer. And a register for outputting a signal for turning on / off the power of the electronic device, detecting a short circuit between the load power supply and the GND during and before the operation of the electronic device, and turning off the power when the short circuit is detected. It is configured as follows. .

【0005】[0005]

【発明の実施の形態】本発明の請求項1に記載の発明
は、電子機器の負荷電圧を検出する電圧検出回路と、前
記電圧検出回路の出力を所定時間遅延する遅延回路と、
前記電子機器の電源をONしたことを示す電源ON信号
で起動し所定時間後出力するタイマーと、を入力とする
OR回路と、前記電源ON信号でリセットされ前記遅延
回路の出力または前記タイマーの出力で前記電圧検出回
路の出力を読み込み前記電子機器の電源をON/OFF
する信号を出力するレジスタを備えた電子機器保護回路
であり、低価格で自由に設計できる電子機器保護回路を
提供することができるという作用がある。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is directed to a voltage detection circuit for detecting a load voltage of an electronic device, a delay circuit for delaying an output of the voltage detection circuit for a predetermined time,
An OR circuit that receives a power-on signal indicating that the power of the electronic device has been turned on and outputs the signal after a predetermined time, and an OR circuit; an output of the delay circuit reset by the power-on signal and the output of the timer; Reads the output of the voltage detection circuit and turns on / off the power of the electronic device.
This is an electronic device protection circuit including a register for outputting a signal to generate an electronic device, and has an effect that an electronic device protection circuit that can be freely designed at low cost can be provided.

【0006】本発明の請求項2記載の発明は、前記レジ
スタの出力と前記電源ON信号を入力とし前記電子機器
の電源をON/OFFする信号を出力する回路を備えた
請求項1記載の電子機器保護回路であり、ショート状態
で電源をOFF状態に保持して安全を保つとともに、使
い勝手のよい電子機器保護回路を提供することができる
という作用がある。
According to a second aspect of the present invention, there is provided the electronic device according to the first aspect, further comprising a circuit which receives the output of the register and the power ON signal and outputs a signal for turning ON / OFF the electronic device. This is a device protection circuit, which has an effect of providing a user-friendly electronic device protection circuit while maintaining safety by keeping a power supply in an OFF state in a short-circuit state.

【0007】次に本発明の電子機器保護回路の実施の形
態を、図1と図2を参照して説明する。
Next, an embodiment of an electronic equipment protection circuit according to the present invention will be described with reference to FIGS.

【0008】(実施の形態1)図1は本発明の電子機器
保護回路の実施の形態1の構成図、図2は本発明の電子
機器保護回路の実施の形態1における通常動作のタイミ
ング図、図3は本発明の電子機器保護回路の実施の形態
1における動作中にショートした場合のタイミング図、
図4は本発明の電子機器保護回路の実施の形態1におけ
る動作以前にショートしている場合のタイミング図を示
す。
(Embodiment 1) FIG. 1 is a block diagram of an electronic device protection circuit according to Embodiment 1 of the present invention, FIG. 2 is a timing chart of a normal operation in Embodiment 1 of the electronic device protection circuit of the present invention, FIG. 3 is a timing chart when a short circuit occurs during the operation of the electronic device protection circuit according to the first embodiment of the present invention;
FIG. 4 is a timing chart when a short circuit occurs before the operation of the electronic device protection circuit according to the first embodiment of the present invention.

【0009】図1において、電子機器保護回路は、OR
回路1と、タイマー2と、レジスタ3と、遅延回路4
と、電圧検出回路5、AND回路6で構成される。
In FIG. 1, an electronic equipment protection circuit is an OR circuit.
Circuit 1, timer 2, register 3, delay circuit 4
And a voltage detection circuit 5 and an AND circuit 6.

【0010】OR回路1は、遅延回路4の出力信号VC
CRST’とタイマー2からの出力TIMER信号を入
力してCLK信号を出力する論理和回路である。
The OR circuit 1 outputs the output signal VC of the delay circuit 4
This is an OR circuit that inputs CRST ′ and the output TIMER signal from the timer 2 and outputs a CLK signal.

【0011】タイマー2は、電子機器の電源スイッチ回
路7の電源スイッチON/OFFの状態を示すVCCO
N信号でローレベル(以下Lと略記する)でリセット状
態に保持されハイレベル(以下Hと略記する)で起動し
所定時間経過後、LからHに変化するTIMER信号を
出力する。
The timer 2 has a VCCO indicating the power switch ON / OFF state of the power switch circuit 7 of the electronic device.
The reset signal is held at a low level (hereinafter abbreviated as L) by an N signal, is activated at a high level (hereinafter abbreviated as H), and outputs a TIMER signal that changes from L to H after a lapse of a predetermined time.

【0012】本発明の電子機器保護回路の実施の形態1
に関係する電子機器側の構成要素は、電源ON信号を出
力する電源スイッチ回路7と、電源8である。
First Embodiment of Electronic Device Protection Circuit of the Present Invention
The components on the electronic device side related to are a power switch circuit 7 for outputting a power ON signal and a power supply 8.

【0013】レジスタ3は、電子機器の電源をHでO
N、LでOFFするPWROFF信号を出力する記憶回
路で,具体例として、リセット端子Rとデータ入力端子
Dおよびクロック端子CKを有するD型フリップフロッ
プと、入力信号の立ち上がり及び立ち下りでクロックを
生成してクロック端子CKに出力する回路とで構成され
ている。
The register 3 is for turning on the power supply of the electronic equipment by H
A storage circuit that outputs a PWROFF signal that is turned off at N and L. As a specific example, a D-type flip-flop having a reset terminal R, a data input terminal D, and a clock terminal CK, and a clock generated at rising and falling edges of an input signal And a circuit for outputting to the clock terminal CK.

【0014】レジスタ3のリセット端子Rに入力される
PWRON信号がLの場合PWROFF信号がH(電子
機器の電源がON可能状態)に保持され、PWRON信
号がHでリセット状態が解除され、データ入力端子Dの
電圧検出回路5の出力信号VCCRSTの立ち上がりで
読み込み、HまたLのPWROFF信号を出力する。
When the PWRON signal input to the reset terminal R of the register 3 is L, the PWROFF signal is held at H (the power of the electronic device can be turned on), the reset state is released when the PWRON signal is H, and the data input is performed. The signal is read at the rise of the output signal VCCRST of the voltage detection circuit 5 of the terminal D, and the H or L PWROFF signal is output.

【0015】遅延回路4は、電圧検出回路5のVCCR
ST信号をレジスタ3のセットアップ時間以上の所定時
間遅延したVCCRST’信号を出力する。
[0015] The delay circuit 4 is connected to the VCCR of the voltage detection circuit 5.
It outputs a VCCRST 'signal obtained by delaying the ST signal by a predetermined time equal to or longer than the setup time of the register 3.

【0016】電圧検出回路5は、電子機器の負荷電圧V
CCを監視し、VCCが所定値例えば規定電圧の70%
以下になるとLになるVCCRST信号を出力する。
The voltage detection circuit 5 is provided with a load voltage V
CC is monitored, and VCC is a predetermined value, for example, 70% of specified voltage.
When it becomes less than the above, it outputs the VCCRST signal which becomes L.

【0017】AND回路6は、電源スイッチ回路7から
のVCCON信号と、レジスタ3からのPWROFF信
号を入力として電源8をON/OFFする信号を出力す
る論理積回路である。
The AND circuit 6 is a logical product circuit which receives the VCCON signal from the power switch circuit 7 and the PWROFF signal from the register 3 and outputs a signal for turning on / off the power supply 8.

【0018】電源スイッチ回路7は、電子機器の電源8
をON/OFFするVCCON信号を出力する。
The power switch circuit 7 includes a power supply 8 for the electronic device.
Output a VCCON signal for turning ON / OFF.

【0019】電源8は、電子機器の電源でその付加回路
や機器に負荷電圧VCCの電力を供給する。
The power supply 8 is a power supply for the electronic equipment and supplies power of the load voltage VCC to the additional circuits and the equipment.

【0020】まず、通常の電源ON/OFF動作を図1
と図2を参照して説明する。図2において、電子機器の
電源スイッチONの時点T1で、VCCON信号がLか
らHに立ち上がり同時に負荷電圧VCCが徐々に立ち上
がる。
First, a normal power ON / OFF operation is shown in FIG.
This will be described with reference to FIG. In FIG. 2, at time T1 when the power switch of the electronic device is turned on, the VCCON signal rises from L to H, and at the same time, the load voltage VCC gradually rises.

【0021】そして、負荷電圧VCCが所定電圧値以上
に達すると、電圧検出回路5のVCCRST信号が立ち
上がる。この変化が遅延回路4で所定時間遅延された時
点T2でVCCRST’が立ち上がる。レジスタ3は、
この立ち上がり時点T2でのVCCRST信号のHを読
む。しかし、レジスタ3の出力PWROFF信号は、既
にVCCON信号のLで保持されていた状態でHなので
変化しない。タイマー2の出力TIMER信号が立ち上
がる時VCCRST信号のHを読むが前述のようにPW
ROFF信号は変化しないでHを保持する。
When the load voltage VCC reaches a predetermined voltage value or more, the VCCRST signal of the voltage detection circuit 5 rises. At time T2 when this change is delayed by the delay circuit 4 for a predetermined time, VCCRST 'rises. Register 3
The H level of the VCCRST signal at the rising point T2 is read. However, the output PWROFF signal of the register 3 does not change because it is H while being already held at L of the VCCON signal. When the output TIMER signal of the timer 2 rises, the H level of the VCCRST signal is read.
The ROFF signal keeps H without changing.

【0022】VCCON信号およびPWROFF信号が
ともにHなのでAND回路6はHとなり、電源スイッチ
回路7のON操作で電源8がONする。
Since the VCCON signal and the PWROFF signal are both H, the AND circuit 6 becomes H, and the power supply 8 is turned on by turning on the power switch circuit 7.

【0023】次に、電子機器の電源スイッチ回路OFF
の時点T3でPWRON信号が立ち下り同時に負荷電圧
VCCが徐々に立ち下がる。そして、負荷電圧VCCが
所定電圧値以下になると、電圧検出回路5のVCCRS
T信号がLになる。この変化で遅延回路4の出力VCC
RST’がLになる。すると、レジスタ3は、VCCR
ST’信号の立ち下り時点T4でのVCCRST信号の
Lを読むと、出力のPWROFF信号がLに変化する。
Next, the power switch circuit of the electronic device is turned off.
At time T3, the PWRON signal falls and the load voltage VCC gradually falls at the same time. When the load voltage VCC falls below a predetermined voltage value, the VCCRS of the voltage detection circuit 5
The T signal becomes L. This change causes the output VCC of the delay circuit 4 to change.
RST ′ becomes L. Then, the register 3 stores the VCCR
When the L of the VCCRST signal is read at the falling point T4 of the ST ′ signal, the output PWROFF signal changes to L.

【0024】VCCON信号およびPWROFF信号が
ともにHなのでAND回路6はHとなり、電源スイッチ
回路7のOFF操作で電源8がOFFする。
Since both the VCCON signal and the PWROFF signal are H, the AND circuit 6 becomes H, and the power supply 8 is turned off by turning off the power switch circuit 7.

【0025】次に、電子機器動作中に負荷電源とGND
間にショートが起こった場合を、図1と図3を参照し
て、保護動作を説明する。
Next, during the operation of the electronic equipment, the load power supply and the GND
The protection operation in the case where a short circuit occurs between them will be described with reference to FIGS.

【0026】時点T1〜T2での電源ON動作は、前述
の通常動作と同じである。T5時点で発生したショート
により負荷電圧VCCが低下し、電圧検出回路5の出力
VCCRSTがLに変化する。そして、遅延回路4の出
力信号VCCRST’が所定時間遅れてLに変化する時
点T6で、レジスタ3はVCCRST信号を読み込みP
WROFF信号をLにする。AND回路6は、VCCO
N信号がHであるがPWROFF信号がLのためLを出
力して電源8がOFFされ、負荷電圧VCCがOFFさ
れ、さらにこの電源8のOFFが保持される。
The power-on operation at the time T1 to T2 is the same as the above-described normal operation. The load voltage VCC decreases due to the short circuit occurring at the time T5, and the output VCCRST of the voltage detection circuit 5 changes to L. Then, at time T6 when the output signal VCCRST ′ of the delay circuit 4 changes to L with a delay of a predetermined time, the register 3 reads the VCCRST signal and sets
The WROFF signal is set to L. The AND circuit 6 has a VCCO
Since the N signal is H but the PWROFF signal is L, L is output and the power supply 8 is turned off, the load voltage VCC is turned off, and the power supply 8 is kept off.

【0027】このOFF保持状態で、時点T10で電源
スイッチをOFFすると、時点T10でVCCON信号
がLになり、PWROFF信号はHに、タイマー2はリ
セット状態Lに変化する。AND回路6は、VCCON
信号がLでPWROFF信号がHのため出力はLであ
る。電源8はOFFのままである。
In this OFF holding state, when the power switch is turned off at time T10, the VCCON signal becomes L at time T10, the PWROFF signal becomes H, and the timer 2 changes to the reset state L. AND circuit 6 is connected to VCCON
Since the signal is L and the PWROFF signal is H, the output is L. The power supply 8 remains off.

【0028】さらに、ショート原因が除去されて後、時
点T11で電源スイッチをONすると、VCCON信号
がHに変化し前述の通常の電源ON動作を開始する。
Further, after the cause of the short circuit is removed, when the power switch is turned on at time T11, the VCCON signal changes to H, and the above-described normal power ON operation is started.

【0029】もし、ショート原因を除去しないでショー
トのままで、電源スイッチをONすると次に説明する保
護動作が行われる。
If the power switch is turned on without removing the cause of the short circuit without removing the cause, the protection operation described below is performed.

【0030】最後に電源ON以前からショートしている
場合の保護動作を図1と図4を参照して説明する。
Finally, a protection operation in the case where a short circuit occurs before the power is turned on will be described with reference to FIGS.

【0031】電源ONの時点T1でVCCON信号がH
になり、電源をONするがショートしているためにVC
Cの電圧が上昇しないため、電圧検出回路5の出力VC
CRSTがHに変化しないしこれにともない遅延回路4
の出力VCCRST’はLのままである。しかしVCC
ON信号でリセットを解除され起動されたタイマー2の
出力TIMER信号が、VCCが立ち上がるのに十分な
所定時間の後時点T7でHへ立ち上がり、OR回路1を
通ってレジスタ3にVCCRST’信号を送り、VCC
RST信号のLを読んでPWROFF信号がLになる。
VCCON信号がH、PWROFF信号がLのためにA
ND回路6のL出力により電源8はOFFされる。
At time T1 when the power is turned on, the VCCON signal goes high.
Is turned on, but the power is turned on.
Since the voltage of C does not rise, the output VC of the voltage detection circuit 5
CRST does not change to H and the delay circuit 4
Output VCCRST 'remains at L. But VCC
After the reset is released by the ON signal, the output TIMER signal of the timer 2 which has been activated rises to H at a time T7 after a predetermined time sufficient for VCC to rise, and sends the VCCRST 'signal to the register 3 through the OR circuit 1. , VCC
After reading L of the RST signal, the PWROFF signal becomes L.
A because the VCCON signal is H and the PWROFF signal is L
The power supply 8 is turned off by the L output of the ND circuit 6.

【0032】ショート原因を除去した後、時点T10で
電源スイッチをOFFし時点T11で再びONすれば、
前述のように通常のON動作をする。もし、ショート原
因が除去されずに電源をOFFし、再びONすると前述
の時点T1、T7での動作が繰り返されて電源をOFF
してショートによる障害の発生を防止する。
After removing the cause of the short circuit, if the power switch is turned off at time T10 and turned on again at time T11,
The normal ON operation is performed as described above. If the power is turned off and the power is turned on again without removing the cause of the short circuit, the operation at the above-described time points T1 and T7 is repeated to turn off the power.
To prevent failures caused by short circuits.

【0033】なお、本発明の実施の形態1では、レジス
タとしてフリップフロップで説明したが、これに限定さ
れない。電源ON信号でリセット状態が解除され、負荷
の電圧検出信号の変化を読み、読んだ信号を保持し出力
する回路であれば本発明と同じ効果が得られる。
In the first embodiment of the present invention, the flip-flop is used as the register. However, the present invention is not limited to this. The same effects as those of the present invention can be obtained if the reset state is released by the power ON signal, the change in the voltage detection signal of the load is read, and the read signal is held and output.

【0034】[0034]

【発明の効果】以上のように本発明によれば、特別なI
Cを使うことなく汎用ICを使い、安価で単純な回路構
成で、動作時と動作以前の2つの状態で電源とGNDの
ショートを検出して電子機器の電源をOFFして安全を
確保する電子機器保護回路を提供することができる。
As described above, according to the present invention, a special I
Using a general-purpose IC without using C, an inexpensive and simple circuit configuration, an electronic device that detects a short circuit between the power supply and GND in two states before and after operation and turns off the power supply of the electronic device to ensure safety. An equipment protection circuit can be provided.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の電子機器保護回路の実施の形態1の構
成図
FIG. 1 is a configuration diagram of an electronic device protection circuit according to a first embodiment of the present invention.

【図2】本発明の電子機器保護回路の実施の形態1にお
ける通常動作のタイミング図
FIG. 2 is a timing chart of a normal operation in the electronic device protection circuit according to the first embodiment of the present invention;

【図3】本発明の電子機器保護回路の実施の形態1にお
ける動作中にショートした場合のタイミング図
FIG. 3 is a timing chart when a short circuit occurs during operation of the electronic device protection circuit according to the first embodiment of the present invention;

【図4】本発明の電子機器保護回路の実施の形態1にお
ける動作以前からショートしている場合のタイミング図
FIG. 4 is a timing chart in the case where a short circuit has occurred before the operation of the electronic device protection circuit according to the first embodiment of the present invention;

【符号の説明】[Explanation of symbols]

1 OR回路 2 タイマー 3 レジスタ 4 遅延回路 5 電圧検出回路 Reference Signs List 1 OR circuit 2 Timer 3 Register 4 Delay circuit 5 Voltage detection circuit

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) // H02H 7/20 G06F 1/00 341Q ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) // H02H 7/20 G06F 1/00 341Q

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】電子機器の負荷電圧を検出する電圧検出回
路と、前記電圧検出回路の出力を所定時間遅延する遅延
回路と、前記電子機器の電源をONしたことを示す電源
ON信号で起動し所定時間後出力するタイマーと、前記
電源ON信号で読み込み可否を制御され前記遅延回路の
出力または前記タイマーの出力で前記電圧検出回路の出
力を読み込み前記電子機器の電源をON/OFFする信
号を出力するレジスタを備えた電子機器保護回路。
1. A voltage detecting circuit for detecting a load voltage of an electronic device, a delay circuit for delaying an output of the voltage detecting circuit for a predetermined time, and a power ON signal indicating that the power of the electronic device is turned on. A timer which outputs after a predetermined time, and a read / write control which is controlled by the power ON signal, outputs an output of the voltage detection circuit by an output of the delay circuit or an output of the timer, and outputs a signal for turning on / off the power of the electronic device. Electronic device protection circuit with register
【請求項2】前記レジスタの出力と前記電源ON信号を
入力とし前記電子機器の電源をON/OFFする信号を
出力する回路を備えた請求項1記載の電子機器保護回
路。
2. The electronic device protection circuit according to claim 1, further comprising a circuit which receives the output of the register and the power ON signal and outputs a signal for turning on / off the power of the electronic device.
JP10274951A 1998-09-29 1998-09-29 Electronic equipment protecting circuit Pending JP2000105616A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10274951A JP2000105616A (en) 1998-09-29 1998-09-29 Electronic equipment protecting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10274951A JP2000105616A (en) 1998-09-29 1998-09-29 Electronic equipment protecting circuit

Publications (1)

Publication Number Publication Date
JP2000105616A true JP2000105616A (en) 2000-04-11

Family

ID=17548841

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10274951A Pending JP2000105616A (en) 1998-09-29 1998-09-29 Electronic equipment protecting circuit

Country Status (1)

Country Link
JP (1) JP2000105616A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012022533A (en) * 2010-07-14 2012-02-02 Hagiwara Electric Co Ltd Power-on-control circuit
KR101832985B1 (en) 2011-04-01 2018-03-02 페어차일드코리아반도체 주식회사 Auto restart circuit, switch controlling circuit, and switch controlling method
CN108508315A (en) * 2017-02-27 2018-09-07 发那科株式会社 Connect the connection circuit of equipment

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012022533A (en) * 2010-07-14 2012-02-02 Hagiwara Electric Co Ltd Power-on-control circuit
KR101832985B1 (en) 2011-04-01 2018-03-02 페어차일드코리아반도체 주식회사 Auto restart circuit, switch controlling circuit, and switch controlling method
CN108508315A (en) * 2017-02-27 2018-09-07 发那科株式会社 Connect the connection circuit of equipment
JP2018143029A (en) * 2017-02-27 2018-09-13 ファナック株式会社 Connection circuit of connection device
US10447029B2 (en) 2017-02-27 2019-10-15 Fanuc Corporation Connection circuit of interconnect device

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