JPS6160508B2 - - Google Patents

Info

Publication number
JPS6160508B2
JPS6160508B2 JP57076192A JP7619282A JPS6160508B2 JP S6160508 B2 JPS6160508 B2 JP S6160508B2 JP 57076192 A JP57076192 A JP 57076192A JP 7619282 A JP7619282 A JP 7619282A JP S6160508 B2 JPS6160508 B2 JP S6160508B2
Authority
JP
Japan
Prior art keywords
cassette
power supply
circuit
signal
control device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57076192A
Other languages
Japanese (ja)
Other versions
JPS58194191A (en
Inventor
Keiichi Kaneko
Shigeru Takai
Katsunori Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57076192A priority Critical patent/JPS58194191A/en
Publication of JPS58194191A publication Critical patent/JPS58194191A/en
Publication of JPS6160508B2 publication Critical patent/JPS6160508B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C19/00Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/02Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements
    • G11C19/08Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements using thin films in plane structure
    • G11C19/0875Organisation of a plurality of magnetic shift registers

Description

【発明の詳細な説明】 発明の技術分野 本発明は、磁気バブルカセツトが差し込まれて
電源供給、書込み読取り制御などを行なう制御装
置に関する。
TECHNICAL FIELD OF THE INVENTION The present invention relates to a control device into which a magnetic bubble cassette is inserted and which performs power supply, write/read control, etc.

従来技術と問題点 一般に磁性チツプ、駆動コイル、および保持用
磁石などからなるバブルデバイスをプリント板に
搭載しケースに収容した磁気バブルカセツトは、
制御回路(周辺回路ともいう)に差し込むことで
着脱自在に接続される。バブルデバイスの電源は
周辺回路側から供給されるが、従来はカセツトの
非接続時にも電源オン状態にしていたので、カセ
ツトの差し込み時に異常電流が流れ、情報を破壊
する恐れがあつた。これは第5図に示すようにバ
ブルデバイスの各フアンクシヨンゲートの導線に
分布容量Csが存在するので、これを充電する電
流iが急激に流れるためである。同図において
MJLはメジヤーループ、MNLは複数本のマイナ
ーループ、REPはマイナーループMNLからメジ
ヤーループMJLにバブルを読出すリプリケー
タ、GENはバブルを発生させるジエネレータ、
SWPはジエネレータGENが発生し伝播路PLを転
送されるバブル列をマイナーループMNLに取込
む(書込む)スワツプゲートである。REP,
SWP,GENはフアンクシヨンゲートと総称され
電流動作型であるので要部は導線で、ここに前述
した分布容量Csが存在する。またこれらのゲー
トの非電源側には定電流源が接続されるがこの定
電流源が例えばトランジスタで構成される場合に
はそのコレクタ、ベース間の容量なども充電対象
となる。そしてこれらの容量に対する充電電流i
のピーク値が大きいと通常動作時と変らない多量
の磁束を発生させこれが情報破壊の原因となる。
例えばリプリケータREPに電流iが流れるとバ
ブル(スワツプゲートの下にはバブルが有るのが
普通である)伸長、分割が行なわれ、メジヤール
ープにバブルが入り込んだりする。これは勿論エ
ラーとなる。
Conventional technology and problems In general, a magnetic bubble cassette, in which a bubble device consisting of a magnetic chip, a driving coil, a holding magnet, etc. is mounted on a printed board and housed in a case, is
It is removably connected by being plugged into a control circuit (also called a peripheral circuit). Power for bubble devices is supplied from the peripheral circuit, but in the past, the power was kept on even when the cassette was disconnected, so there was a risk that abnormal current would flow when the cassette was inserted, destroying information. This is because, as shown in FIG. 5, there is a distributed capacitance Cs in the conductor wire of each function gate of the bubble device, and the current i that charges the distributed capacitance Cs flows rapidly. In the same figure
MJL is a major loop, MNL is multiple minor loops, REP is a replicator that reads bubbles from the minor loop MNL to the major loop MJL, GEN is a generator that generates bubbles,
SWP is a swap gate that takes in (writes) into the minor loop MNL the bubble train generated by the generator GEN and transferred through the propagation path PL. REP,
SWP and GEN are collectively called function gates and are current-operated, so the main part is a conductor, where the distributed capacitance Cs described above exists. Further, a constant current source is connected to the non-power supply side of these gates, and if this constant current source is composed of, for example, a transistor, the capacitance between its collector and base is also charged. And the charging current i for these capacities
If the peak value of is large, a large amount of magnetic flux is generated, which is the same as during normal operation, and this causes information destruction.
For example, when a current i flows through the replicator REP, a bubble (usually there is a bubble under the swap gate) is expanded and divided, and the bubble enters the major loop. This, of course, results in an error.

カセツトを差し込んでから電源を投入する、例
えばカセツトの接続を検出してリレーを動作させ
これにより電源を投入しても依然問題は残る。即
ちこの方法でも、電源の立上がりは急峻であるか
ら容量Csの充電電流iが急激に流れる点に変り
はない。
Even if the power is turned on after the cassette is inserted, for example, the connection of the cassette is detected and a relay is activated to turn on the power, the problem still remains. That is, even with this method, since the power supply rises steeply, the charging current i of the capacitor Cs flows rapidly.

発明の目的 本発明は、磁気バブルカセツトが接続されてか
ら徐々に電源を立上げることにより、フアンクシ
ヨンゲートに異常電流が流れエラーを生じるのを
防止しようとするものである。
OBJECTS OF THE INVENTION The present invention aims to prevent abnormal current from flowing through the function gate and causing an error by gradually turning on the power after the magnetic bubble cassette is connected.

発明の構成 本発明は、磁気バブルカセツトが挿入されて該
カセツトの電源供給、書込み読取り制御などを行
なう制御装置において、該制御装置に該カセツト
の挿入を検出する回路を設け、また出力する電源
電圧の立上がりが緩やかになるように時定数を設
定した電源回路を設け、そして前記検出回路が該
カセツトの挿入を検出した後に該電源回路が出力
し始めるようにしてなることを特徴とするが、以
下図示の実施例を参照しながらこれを詳細に説明
する。
Structure of the Invention The present invention provides a control device into which a magnetic bubble cassette is inserted and which performs power supply, write/read control, etc. of the cassette. The invention is characterized in that a power supply circuit is provided with a time constant set so that the rise of the cassette becomes gradual, and the power supply circuit starts outputting after the detection circuit detects insertion of the cassette. This will be explained in detail with reference to the illustrated embodiment.

発明の実施例 第1図は本発明の一実施例を示すブロツク図
で、第2図はその各部信号波形図である。磁気バ
ブルカセツト10は前述のようにバブルデバイス
をプリント基板上に搭載し、周辺回路との接続は
多ピン式のコネクタで行なう。11,12はその
ピン(端子)の一部で、11は電源用の端子、1
2は接続を知らせる端子である。周辺回路20側
にはこれらの端子11,12と篏合する端子2
1,22がある。Rは端子22を一定電圧Vcに
つり上げ、カセツト10が非接続であればカセツ
ト接続検出信号をVcつまり高レベルにしてお
くプルアツプ抵抗である。この信号はカセツト
10のアースされた端子12が周辺回路20の端
子22に接続されると0Vに低下してカセツト接
続を知らせる。第2図のt0がこの時点である。電
源回路23はこの時点から出力を立上げ始めて
もよいが、カセツト10のコネクタは例えば24ピ
ンなどの多ピン型であるから、端子12が篏合し
た時点でも残りの端子が全て篏合しているとは限
らない。そこで遅延回路24で信号をT1時間
遅延させ、時刻t1で立下る遅延出力で電源回路
23を起動する。電源回路23は信号で起動さ
れても出力を急峻に立上げるのではなく、カセ
ツト10側の分布容量等を考慮して決定した容量
を出力段に付加して徐々に定格値VFまで上昇さ
せる。これによりカセツト10に流入する電流i
のピーク値は著しく低減できる。併せてバブルメ
モリの書込み読取り制御回路への動作可能信号
を電源が充分にVFまで立上つた後(t2)に与え
ることにより、電源立上り前の動作を禁止して情
報破壊を防止する。この信号は例えば遅延回路
24で信号にT2なる遅延時間を与えることで
作成できる。
Embodiment of the Invention FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a signal waveform diagram of each part thereof. As described above, the magnetic bubble cassette 10 has a bubble device mounted on a printed circuit board, and is connected to peripheral circuits using a multi-pin connector. 11 and 12 are some of the pins (terminals), 11 is the power supply terminal, 1
2 is a terminal that notifies connection. On the peripheral circuit 20 side, there is a terminal 2 that mates with these terminals 11 and 12.
There are 1 and 22. R is a pull-up resistor that pulls up the terminal 22 to a constant voltage Vc, and keeps the cassette connection detection signal at Vc, that is, a high level, if the cassette 10 is not connected. This signal drops to 0V when grounded terminal 12 of cassette 10 is connected to terminal 22 of peripheral circuit 20, indicating cassette connection. This point is t 0 in FIG. 2. The power supply circuit 23 may start outputting from this point, but since the connector of the cassette 10 is a multi-pin type, such as 24 pins, even when the terminal 12 is mated, all the remaining terminals are mated. It doesn't necessarily mean there are. Therefore, the delay circuit 24 delays the signal by T 1 time, and the power supply circuit 23 is activated by the delayed output that falls at time t 1 . Even when the power supply circuit 23 is activated by a signal, the output does not rise abruptly, but gradually increases to the rated value V F by adding a capacity determined in consideration of the distributed capacitance on the cassette 10 side to the output stage. . As a result, the current i flowing into the cassette 10
The peak value of can be significantly reduced. In addition, by giving an operation enable signal to the write/read control circuit of the bubble memory after the power supply has sufficiently risen to V F (t 2 ), operations before the power supply is started are prohibited to prevent information destruction. This signal can be created, for example, by applying a delay time of T 2 to the signal using the delay circuit 24.

第3図は電源回路23と遅延回路24の具体例
である。遅延回路24の抵抗R1と容量C1は信号
に遅延時間T1を与え、また抵抗R2と容量C2
信号に遅延時間T2を与える。これらの遅延時
間はデイレイラインにより与えてもよい。I1〜I4
は反転および波形整形用のインバータである。電
源回路23は出力段に立上りをなまらせる容量
C3を有する。カセツト10が非接続であれば信
号はL(ロー)であるからトランジスタQ1
オフ、従つてトランジスタQ2もオフで出力お
よびコンデンサC3は高抵抗R4を通してアースさ
れ0Vに保たれている。これに対しカセツト10
が接続され一定時間後に信号がH(ハイ)にな
るとトランジスタQ1がオンし、つれてトランジ
スタQ2がオンするので容量C3は抵抗R3を通して
充電され始める。このときの出力の立上りが
R3,C3の時定数で緩やかに抑えられるので、第
2図のように電流iのピーク値は低くて済む。つ
まり i=C・dv/dt の関係から充電時間tを長くすることで、電流i
のピーク値を低下させることができる。この場合
Cはカセツト側の前述した分布容量Cs、vは定
格値VFの電源電圧である。電源回路23は上記
の例に限定されず、例えばスイツチングレギユレ
ータと平滑回路を用いスイツチングのオン、オフ
期間を制御するようにしてもよい。
FIG. 3 shows a specific example of the power supply circuit 23 and the delay circuit 24. The resistor R 1 and capacitor C 1 of the delay circuit 24 give a delay time T 1 to the signal, and the resistor R 2 and capacitor C 2 give a delay time T 2 to the signal. These delay times may be provided by a delay line. I1 to I4
is an inverter for inversion and waveform shaping. The power supply circuit 23 has a capacity that smooths the rise of the output stage.
Has C3 . If the cassette 10 is not connected, the signal is L (low), so the transistor Q1 is off, so the transistor Q2 is also off, and the output and capacitor C3 are grounded through the high resistance R4 and kept at 0V. . In contrast, cassette 10
is connected and the signal becomes H (high) after a certain period of time, transistor Q 1 turns on, and as a result transistor Q 2 turns on, so capacitor C 3 begins to be charged through resistor R 3 . The rise of the output at this time is
Since it can be moderately suppressed by the time constants R 3 and C 3 , the peak value of the current i can be kept low as shown in FIG. In other words, by increasing the charging time t from the relationship i=C・dv/dt, the current i
can reduce the peak value of In this case, C is the aforementioned distributed capacitance Cs on the cassette side, and v is the power supply voltage of the rated value VF . The power supply circuit 23 is not limited to the above example, and may be configured to control the on/off period of switching using, for example, a switching regulator and a smoothing circuit.

第4図は本発明の他の実施例で、バブルメモリ
制御回路へ与える動作許可信号を電源回路23
の出力から直接検出するようにしたものであ
る。第1図の例では信号は遅延回路24で作成
したが、この信号の性質上出力が充分に立上つ
た後に変化する必要があるので、電源検出回路2
5で出力を直接検出すれば信号の変化タイミ
ングは一層確実になる。
FIG. 4 shows another embodiment of the present invention, in which the operation permission signal given to the bubble memory control circuit is sent to the power supply circuit 23.
It is designed to detect directly from the output of . In the example shown in FIG. 1, the signal is created by the delay circuit 24, but due to the nature of this signal, it needs to change after the output rises sufficiently, so the power supply detection circuit 24
If the output is directly detected in step 5, the signal change timing will be more reliable.

発明の効果 以上述べたように本発明によれば、磁気バブル
カセツト接続時に以上電流を発生させないので、
該カセツト着脱時の情報破壊を防止できる利点が
ある。
Effects of the Invention As described above, according to the present invention, no more current is generated when the magnetic bubble cassette is connected.
This has the advantage of preventing information from being destroyed when the cassette is attached or detached.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示すブロツク図、
第2図はその各部信号波形図、第3図は第1図の
具体例を示す要部回路図、第4図は本発明の他の
実施例を示すブロツク図、第5図はバブルデバイ
スの要部構成図である。 図中、10は磁気バブルカセツト、11は電源
用端子、12は接続報知用端子、20は制御装
置、23は電源回路、C3は立上り制御用の容
量、Rはカセツト接続検出用抵抗である。
FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a signal waveform diagram of each part, FIG. 3 is a main circuit diagram showing a specific example of FIG. 1, FIG. 4 is a block diagram showing another embodiment of the present invention, and FIG. 5 is a bubble device diagram. It is a main part configuration diagram. In the figure, 10 is a magnetic bubble cassette, 11 is a power supply terminal, 12 is a connection notification terminal, 20 is a control device, 23 is a power supply circuit, C3 is a capacitor for start-up control, and R is a resistor for detecting cassette connection. .

Claims (1)

【特許請求の範囲】 1 磁気バブルカセツトが挿入されて該カセツト
の電源供給、書込み読取り制御などを行なう制御
装置において、該制御装置に該カセツトの挿入を
検出する回路を設け、また出力する電源電圧の立
上がりが緩やかになるように時定数を設定した電
源回路を設け、そして前記検出回路が該カセツト
の挿入を検出した後に該電源回路が出力し始める
ようにしてなることを特徴とする磁気バブルカセ
ツトの制御装置。 2 電源回路は、検出回路がカセツト挿入を検出
してから一定時間後に出力開始するようにされて
なることを特徴とする特許請求の範囲第1項記載
の磁気バブルカセツトの制御装置。
[Scope of Claims] 1. In a control device into which a magnetic bubble cassette is inserted and which performs power supply, write/read control, etc. of the cassette, the control device is provided with a circuit for detecting the insertion of the cassette, and also has a power supply voltage to be outputted. A magnetic bubble cassette characterized in that a power supply circuit is provided with a time constant set so that the rise of the magnetic bubble cassette becomes gradual, and the power supply circuit starts outputting after the detection circuit detects insertion of the cassette. control device. 2. The control device for a magnetic bubble cassette according to claim 1, wherein the power supply circuit is configured to start outputting after a certain period of time after the detection circuit detects insertion of the cassette.
JP57076192A 1982-05-07 1982-05-07 Controller of magnetic bubble cassette Granted JPS58194191A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57076192A JPS58194191A (en) 1982-05-07 1982-05-07 Controller of magnetic bubble cassette

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57076192A JPS58194191A (en) 1982-05-07 1982-05-07 Controller of magnetic bubble cassette

Publications (2)

Publication Number Publication Date
JPS58194191A JPS58194191A (en) 1983-11-12
JPS6160508B2 true JPS6160508B2 (en) 1986-12-20

Family

ID=13598267

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57076192A Granted JPS58194191A (en) 1982-05-07 1982-05-07 Controller of magnetic bubble cassette

Country Status (1)

Country Link
JP (1) JPS58194191A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61216193A (en) * 1985-02-14 1986-09-25 Fujitsu Ltd Cassette type magnetic bubble memory device
JPS61198494A (en) * 1985-02-28 1986-09-02 Fujitsu Ltd Bubble cassette device

Also Published As

Publication number Publication date
JPS58194191A (en) 1983-11-12

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