JPH04310193A - Ic card insertion/ejection detecting circuit - Google Patents

Ic card insertion/ejection detecting circuit

Info

Publication number
JPH04310193A
JPH04310193A JP3076082A JP7608291A JPH04310193A JP H04310193 A JPH04310193 A JP H04310193A JP 3076082 A JP3076082 A JP 3076082A JP 7608291 A JP7608291 A JP 7608291A JP H04310193 A JPH04310193 A JP H04310193A
Authority
JP
Japan
Prior art keywords
card
information processing
output
low level
detection circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3076082A
Other languages
Japanese (ja)
Inventor
Kenichi Saito
賢一 斎藤
Toshio Kamimura
俊夫 上村
Junji Nakada
順二 中田
Koji Hosoki
浩二 細木
Yoshihiro Fujigami
藤上 義弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP3076082A priority Critical patent/JPH04310193A/en
Publication of JPH04310193A publication Critical patent/JPH04310193A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent any abnormal condition such as run-away or the like by automatically restarting a system when an IC card is inserted/ejected while operating the system of an information processor. CONSTITUTION:At the information processor, a detection circuit 3 is provided to detect the state of loading an IC card 1. When the IC card 1 is loaded or ejected after the system is activated, the detection circuit 3 resets the entire system, and the system is restarted.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明はパ−ソナルコンピュ−タ
、ワ−ドプロセッサなどの情報処理機器において、シス
テム動作中にICカ−ドの抜き差しを行った場合の動作
を保証する回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for guaranteeing operation in information processing equipment such as personal computers and word processors when an IC card is inserted or removed during system operation.

【0002】0002

【従来の技術】従来のパ−ソナルコンピュ−タ(以下パ
ソコン)、ワ−ドプロセッサ(以下ワ−プロ)などの情
報処理機器に拡張メモリ用のICカ−ドを着脱する場合
は、構造上、本体ケ−スを分解しなければならなかった
ため、システム動作中にICカ−ドを着脱するという作
業を行うことは不可能であった。しかし、近年、ICカ
−ドが日本電子工業振興協会で規格化され、ユ−ザがメ
モリ容量を容易に拡張できるようになり、情報処理機器
も、システム動作中にICカ−ドを挿抜できる構成とな
っている。
[Prior Art] When inserting or removing an IC card for expansion memory into information processing equipment such as a conventional personal computer (hereinafter referred to as a personal computer) or a word processor (hereinafter referred to as a word processor), it is difficult to attach or remove an IC card for expansion memory. However, since the main body case had to be disassembled, it was impossible to insert or remove the IC card while the system was in operation. However, in recent years, IC cards have been standardized by the Japan Electronics Industry Promotion Association, allowing users to easily expand their memory capacity, and information processing equipment can also insert and remove IC cards while the system is operating. The structure is as follows.

【0003】0003

【発明が解決しようとする課題】上記従来技術でICカ
−ドが着脱可能のものでも、システム動作中にICカ−
ドを挿抜すると情報処理機器の正常な動作を保証できな
いと問題があった。本発明はユ−ザが誤って、システム
動作中にICカ−ドを挿抜した場合、システムの再起動
を行うことにある。
[Problems to be Solved by the Invention] Even if the IC card is removable in the above-mentioned conventional technology, it is difficult to remove the IC card during system operation.
There was a problem in that normal operation of the information processing equipment could not be guaranteed if the card was inserted or removed. The present invention is to restart the system when a user accidentally inserts or removes an IC card while the system is operating.

【0004】また、同様にシステムを再起動させ、IC
カ−ドを再度挿抜しないよう情報処理機器の表示部に警
告を表示する。
[0004] Similarly, the system can be restarted and the IC
A warning is displayed on the display of the information processing equipment to prevent the card from being inserted or removed again.

【0005】[0005]

【課題を解決するための手段】上記目的を達成するため
に、メ−カ独自の専用ICカ−ドの場合、コネクタにカ
−ド挿抜検知用の端子を設ける。また、日本電子工業振
興協会で規格化されたICカ−ドでは、専用の検知端子
を用いる。
[Means for Solving the Problems] In order to achieve the above object, in the case of a dedicated IC card unique to a manufacturer, a terminal for detecting card insertion/removal is provided in the connector. Furthermore, the IC card standardized by the Japan Electronics Industry Promotion Association uses a dedicated detection terminal.

【0006】ICカ−ドの検知端子の信号を情報処理機
器内の検知回路が検知し、システム動作中にICカ−ド
を抜き差しした場合には、本体全体にリセットをかけ、
システムの再起動を行う。
[0006] A detection circuit within the information processing equipment detects the signal from the detection terminal of the IC card, and if the IC card is inserted or removed while the system is operating, the entire main body is reset.
Restart the system.

【0007】また、この場合に、システム再起動後、警
告を情報処理機器の表示部に表示する。
Furthermore, in this case, after the system is restarted, a warning is displayed on the display section of the information processing device.

【0008】上記手段により、通電中にICカ−ドが抜
き差しされても、本体全体にリセットがかかり、システ
ムが再起動するので、情報処理機器本体の動作が異常に
なったままになることを防ぐことができる。
[0008] With the above means, even if the IC card is inserted or removed while the power is on, the entire main body is reset and the system is restarted, so that the information processing equipment main body does not continue to operate abnormally. It can be prevented.

【0009】[0009]

【作用】ICカ−ドの検知用端子に接続する本体回路側
の端子は常時5V(Vcc)電源に抵抗を介してプルア
ップしている。ICカ−ドがシステム動作中に接続され
ると、検知用信号が5V(以下ハイレベル)の状態から
グランドレベル(GND、以下ロ−レベル)に変化する
。また、ICカ−ドが接続された状態でシステム動作中
に抜いた場合、検知用信号はロ−レベルからハイレベル
に変化する。この検知用信号のレベルが変化するのを検
知することにより、本体をリセットする信号を生成する
[Operation] The terminal on the main circuit side connected to the detection terminal of the IC card is always pulled up to the 5V (Vcc) power supply via a resistor. When the IC card is connected during system operation, the detection signal changes from 5V (hereinafter referred to as high level) to ground level (GND, hereinafter referred to as low level). Further, if the IC card is connected and removed while the system is operating, the detection signal changes from low level to high level. By detecting a change in the level of this detection signal, a signal for resetting the main body is generated.

【0010】また、システム起動中にICカ−ドを抜き
差しされたことを情報処理機器内に記憶しておき、シス
テムが再起動した後、警告を情報処理機器の表示部に表
示する。
[0010]Furthermore, the fact that the IC card has been inserted or removed during system startup is stored in the information processing equipment, and after the system is restarted, a warning is displayed on the display section of the information processing equipment.

【0011】また、情報処理機器本体がパワ−セ−ブモ
−ド、レジュ−ムモ−ドなどのように、本体機能は停止
しているが、一部の機能にのみ通電されている場合にも
、ICカ−ドの挿抜を検知し、本体をリセットする。
[0011] Furthermore, when the information processing device is in power save mode, resume mode, etc., the main body functions are stopped but only some functions are energized. It also detects the insertion and removal of an IC card and resets the main body.

【0012】0012

【実施例】以下、本発明の一実施例を図1、図2により
説明する。
[Embodiment] An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

【0013】メ−カ独自の専用ICカ−ドの場合には、
検知用端子を二本設け、情報処理機器本体側2にも同様
の端子を設ける。専用ICカ−ド側の検知用端子をグラ
ンドレベルに接続しておく。また、標準規格のICカ−
ドの場合は、図2のように36ピン、67ピンの検知用
端子を用いる。システム動作中にICカ−ド1が抜き差
しされると検知信号11、12のレベルが変化する。こ
の信号の変化により検知回路3が本体システム6へのリ
セット信号37(リセット信号52)を生成し、システ
ム全体2をリセットする。
[0013] In the case of a manufacturer's own dedicated IC card,
Two detection terminals are provided, and a similar terminal is provided on the information processing equipment main body side 2. Connect the detection terminal on the dedicated IC card side to ground level. Also, standard IC card
In the case of 36-pin and 67-pin detection terminals as shown in FIG. When the IC card 1 is inserted or removed during system operation, the levels of the detection signals 11 and 12 change. Due to the change in this signal, the detection circuit 3 generates a reset signal 37 (reset signal 52) to the main system 6, and resets the entire system 2.

【0014】また、図1の検知回路3の内部構成、動作
について図2、図3を用いて説明する。
Further, the internal configuration and operation of the detection circuit 3 shown in FIG. 1 will be explained using FIGS. 2 and 3.

【0015】電源をオンすると図1のリセット回路5が
動作し、リセット信号51、52がアクティブになり、
システム全体が初期化される。この時、図3の検知回路
3内のフリップフロップ32、33、34がICカ−ド
1の装着状態を検知する。すなわち、ICカ−ドが装着
されていない場合、検知信号11、12は、本体側で5
Vにプルアップされているので、ハイレベルとなり、ア
ンドゲ−ト31の出力もハイレベルになる。アンドゲ−
ト31の出力をフリップフロップ32、33、34が、
基本クロック信号41に従ってサンプルし、保持する。 この場合、排他的ORゲ−ト35(以下EXORゲ−ト
)は、フリップフロップ32、33、34が、ICカ−
ド装着状態をサンプルし終ると出力が、ロ−レベルとな
る。最終段のフリップフロップ36は、リセット信号5
2が解除されるまでリセットされ、出力Qはロ−レベル
となる。リセット信号52が解除されると、EXORゲ
−ト51の出力を基本クロック41の立上りで保持する
。この場合は、ロ−レベルを保持するので、フリップフ
ロップ36の出力Qは、ロ−レベルのまま変化しない。 リセット信号52が解除されると、システムが起動する
。システム起動後、ICカ−ド1を装着すると検知信号
11、12がハイレベルからロ−レベルに変化し、アン
ドゲ−ト31の出力もロ−レベルに変化する。アンドゲ
−ト31出力のロ−レベルをフリップフロップ32がサ
ンプルすると、出力信号321がハイレベルからロ−レ
ベルに変化し、出力信号341はハイレベルのため、E
XORゲ−ト35の出力はロ−レベルからハイレベルへ
変化する。EXORゲ−ト35出力のハイレベルをフリ
ップフロップ36がサンプルすると、QN出力であるリ
セット信号37がロ−レベルとなる。リセット信号37
がロ−レベルとなると図1のリセット信号52がアクテ
ッブ(ロ−レベル)となり、本体システム6がリセット
され、再起動する。
When the power is turned on, the reset circuit 5 shown in FIG. 1 operates, and the reset signals 51 and 52 become active.
The entire system is initialized. At this time, flip-flops 32, 33, and 34 in the detection circuit 3 shown in FIG. 3 detect the mounting state of the IC card 1. That is, when the IC card is not installed, the detection signals 11 and 12 are
Since it is pulled up to V, it becomes a high level, and the output of the AND gate 31 also becomes a high level. And game
Flip-flops 32, 33, and 34 output the output of
It is sampled and held according to the basic clock signal 41. In this case, exclusive OR gate 35 (hereinafter referred to as EXOR gate) is configured such that flip-flops 32, 33, and 34 are
When the sample of the card attachment state is completed, the output becomes low level. The final stage flip-flop 36 receives the reset signal 5
2 is reset until it is released, and the output Q becomes a low level. When the reset signal 52 is released, the output of the EXOR gate 51 is held at the rising edge of the basic clock 41. In this case, since the low level is maintained, the output Q of the flip-flop 36 remains at the low level and does not change. When the reset signal 52 is released, the system starts up. After the system is started, when the IC card 1 is inserted, the detection signals 11 and 12 change from high level to low level, and the output of AND gate 31 also changes to low level. When the flip-flop 32 samples the low level of the AND gate 31 output, the output signal 321 changes from high level to low level, and since the output signal 341 is high level, E
The output of the XOR gate 35 changes from low level to high level. When the flip-flop 36 samples the high level of the output of the EXOR gate 35, the reset signal 37, which is the QN output, becomes low level. Reset signal 37
When becomes low level, the reset signal 52 in FIG. 1 becomes active (low level), and the main system 6 is reset and restarted.

【0016】また、システム起動後に装着されていたI
Cカ−ド1を抜いた場合にも、装着した場合と同様に全
体システム6がリセットされる。
[0016] Also, the I
Even when the C card 1 is removed, the entire system 6 is reset in the same way as when it is inserted.

【0017】また、ユ−ザリセット8によるシステム起
動の場合でも、電源オンと同様の検知動作を行う。
Furthermore, even when the system is started by the user reset 8, the same detection operation as when the power is turned on is performed.

【0018】次に、ICカ−ド1をシステム起動後、装
着したり、抜いたりしてシステムが再起動し、ユ−ザに
警告を表示部6に表示する場合の一実施例について説明
する。システム起動後に、ICカ−ドを装着したり、抜
いたりすると、リセット信号37(フリップフロップ3
6のQ出力)がロ−レベルとなり、ICカ−ド1がシス
テム起動中に挿抜されたか否かを保持するためのフリッ
プフロップ38がハイレベルにセットされる。フリップ
フロップ38の出力信号381の状態を本体システム6
が再起動中または起動後に読みだし、ハイレベルであれ
ば、ICカ−ド1が挿抜されたと判断し、図4のように
警告を表示部7に表示する。
Next, an embodiment will be described in which a warning is displayed on the display section 6 to the user when the IC card 1 is inserted or removed after the system is started and the system is restarted. . When the IC card is inserted or removed after system startup, the reset signal 37 (flip-flop 3
6 (Q output) becomes low level, and the flip-flop 38 for holding whether or not the IC card 1 is inserted or removed during system startup is set to high level. The state of the output signal 381 of the flip-flop 38 is transmitted to the main body system 6.
is read out during or after restarting, and if it is at a high level, it is determined that the IC card 1 has been inserted or removed, and a warning is displayed on the display section 7 as shown in FIG.

【0019】これにより、ICカ−ド1がシステム動作
中に挿抜されても、システムを再起動することができ、
暴走等の異常事態になることを防ぐことができる。また
、ユ−ザに警告できるので、同じ過ちを繰り返すことを
防ぐことができる。
As a result, even if the IC card 1 is inserted or removed during system operation, the system can be restarted.
It is possible to prevent abnormal situations such as runaway behavior. Furthermore, since the user can be warned, it is possible to prevent the user from repeating the same mistake.

【0020】[0020]

【発明の効果】本発明によれば、ICカ−ドを通電中に
装着したり、抜いたりした場合、自動的にシステム全体
を初期化し再起動できるので、暴走等の異常事態になる
ことを防ぐことができる。
[Effects of the Invention] According to the present invention, if an IC card is inserted or removed while power is being applied, the entire system can be automatically initialized and restarted, thereby preventing abnormal situations such as runaway. It can be prevented.

【0021】また、ICカ−ドを通電中に装着したり、
抜いたりした場合、自動的にシステム全体を初期化し、
再起動後、表示部に警告を表示できる同じ過ちを繰り返
すことを防ぐことができる。
[0021] Also, it is possible to insert the IC card while it is energized,
If you unplug it, the entire system will be initialized automatically.
After restarting, a warning can be displayed on the display to prevent you from making the same mistake again.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】本発明の一実施例のICカ−ドと情報処理機器
のブロック図、
FIG. 1 is a block diagram of an IC card and information processing equipment according to an embodiment of the present invention;

【図2】日本電子工業振興協会で規格化されたICカ−
ドのピン配置図、
[Figure 2] IC cards standardized by the Japan Electronic Industry Promotion Association
pin layout diagram of the

【図3】本発明におけるICカ−ド挿抜検知回路図、[Fig. 3] IC card insertion/removal detection circuit diagram in the present invention;


図4】本発明の一実施例のICカ−ドを挿抜した場合、
ユ−ザへの警告の説明図。
[
Figure 4: When inserting and removing an IC card according to an embodiment of the present invention,
An explanatory diagram of a warning to a user.

【符号の説明】[Explanation of symbols]

1…ICカ−ド、 3…検知回路、 4…基本クロック、 5…リセット回路。 1...IC card, 3...detection circuit, 4...Basic clock, 5...Reset circuit.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】情報処理機器のシステム起動中にICカ−
ドの抜き差しを行った場合、本体内でそれを検知しシス
テム全体を再起動することを特徴とするICカ−ド挿抜
検知回路。
Claim 1: An IC card is installed during system startup of information processing equipment.
An IC card insertion/removal detection circuit is characterized in that when a card is inserted or removed, it is detected within the main body and restarts the entire system.
【請求項2】請求項1において、前記システム全体を再
起動した場合に、前記情報処理機器の表示部へ警告を表
示するICカ−ド挿抜検知回路。
2. The IC card insertion/removal detection circuit according to claim 1, which displays a warning on a display section of the information processing device when the entire system is restarted.
JP3076082A 1991-04-09 1991-04-09 Ic card insertion/ejection detecting circuit Pending JPH04310193A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3076082A JPH04310193A (en) 1991-04-09 1991-04-09 Ic card insertion/ejection detecting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3076082A JPH04310193A (en) 1991-04-09 1991-04-09 Ic card insertion/ejection detecting circuit

Publications (1)

Publication Number Publication Date
JPH04310193A true JPH04310193A (en) 1992-11-02

Family

ID=13594904

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3076082A Pending JPH04310193A (en) 1991-04-09 1991-04-09 Ic card insertion/ejection detecting circuit

Country Status (1)

Country Link
JP (1) JPH04310193A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6745147B2 (en) * 2001-10-04 2004-06-01 International Business Machines Corporation Data processing system, method, and product for automatically tracking insertions of integrated circuit devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6745147B2 (en) * 2001-10-04 2004-06-01 International Business Machines Corporation Data processing system, method, and product for automatically tracking insertions of integrated circuit devices

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