JP3440383B2 - Card interface device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a card interface device, and more particularly to detection of card insertion / removal when the first power supplied to the arithmetic unit is stopped after being supplied and then supplied again.

[0002]

2. Description of the Related Art Generally, a memory card is a ROM card,
There are types such as a flash ROM card and a SRAM card with a built-in battery. Such a memory card is one in which internal data is read by being inserted into the card interface section and the data is transferred to the main body section. The card interface unit includes a card controller, a card insertion / removal monitoring circuit, a CPU, and a data connector and a power connector that electrically connect the memory and the memory card. For example, when the power supply for driving the memory card is determined as Vcc1, when Vcc1 is connected to the power supply connector and data is read from the memory card,
The power supplies of the card controller, the card insertion / removal monitoring circuit, and the CPU are set to Vcc1 so that there is no read error. Even when the power is turned off, the power supply to the memory is set to a power supply voltage Vcc0 lower than Vcc1 even when the power is turned off, and Vcc0 is supplied while the main switch is on. It had been.

[0003]

The card interface as described above is designed to operate with a power supply of two systems of Vcc1 and Vcc0. Vcc1 is a power supply for reading data from a memory card. Yes,
For example, in a portable personal computer, in order to reduce power consumption, after reading the data of the memory card, V
The supply of cc1 may be stopped. In such a case, the card interface unit generally saves the attribute information and data written in the attributive area of the memory card in the memory. When the memory card is newly inserted, Vcc1 is not supplied to the card controller, the card insertion / removal monitoring circuit, and the CPU, so that the insertion of the card cannot be detected. Especially when a different memory card is inserted, Vc
When c1 is supplied, the card interface unit saves the attributes and data of the previous memory card,
Since the saved data is preferentially processed, even if a new memory card is inserted, the interruption of card insertion is not accepted. Therefore, V
When the memory card is inserted after the supply of cc1 is stopped and the Vcc1 is supplied again, the insertion of the memory card cannot be detected and the data of the previous memory card is transferred to the main body side. If the next memory card is inserted and the next data is read and processed, the main body may malfunction or the main body program may run out of control. Therefore, it is desirable to be able to detect the insertion / removal of the memory card regardless of whether Vcc1 is stopped or supplied.

[0004]

According to the present invention, a first power source is supplied to a memory card, a card controller and an arithmetic section, and a second power source having a voltage different from the first power source is supplied to a card monitoring section and a memory. It is related to the card interface device to be supplied. The arithmetic unit controls the card controller to read the information of the memory card after the initial setting when the first and second power supplies are supplied, and the first power supply while the second power is being supplied. Means for saving and masking the information of the memory card in a predetermined area of the memory when the supply of power is stopped, and means for writing the saved information to the card controller when the supply of the first power is supplied again. ,
Means for unmasking a predetermined area of the memory when the first power supply is supplied again so that new card controller information is written in the predetermined area of the memory;
And a means for executing a card reading process based on information in a predetermined area of the memory when there is a card interruption.
Further, the card monitoring unit is activated based on the supply of the second power source, detects insertion or removal of the memory card,
It has means for generating a card interrupt signal when the card is inserted or removed.

[0005]

In the present invention, the first power source is supplied to the memory card, the card controller and the arithmetic section, and the second power source having a voltage different from the first power source is supplied to the card monitoring section and the memory. The arithmetic unit controls the card controller to read the information of the memory card after initial setting when the first and second power supplies are supplied, and when the supply of the first power supply is stopped, When the information of the card is saved and masked in a predetermined area, and when the first power supply is supplied again, the saved information is written to the card controller, the mask is released, and the new card controller is saved in a predetermined area of the memory. Information is written, and when a card is interrupted, a card reading process is performed based on information in a predetermined area of the memory. Further, the card monitoring unit is activated based on the supply of the second power source, detects insertion or removal of the card, and generates a card interrupt signal when the card is inserted or removed.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Generally, a portable personal computer or the like is designed to supply power from a main power supply separately to several kinds of power supplies. Particularly, in the card interface section, for example, Vcc1 and Vc are provided.
c0 (Vcc1> Vcc0) is supplied separately. Then, when Vcc1 and Vcc0 are first supplied simultaneously, a cold start is performed, when Vcc0 is supplied, a suspend state is supplied when Vcc1 is stopped, and when Vcc1 is supplied from the suspended state again, resume is performed. It is called. FIG. 1 is a schematic configuration diagram of the embodiment. 1 is a memory card. The memory card 1 has various types such as ROM, flash ROM, and SRAM, and the attribute information is written in the attobute area in each of them. Reference numeral 1a is a control address and data terminal of the memory card 1, and 1b is a power supply terminal of the memory card 1. 3 is a card interface unit. The card interface unit 3 has at least the following configuration.

Reference numeral 5a is a control address and data terminal of the card interface unit 3, and 5b is a power supply terminal for supplying power to the memory card 1. 7 is a card controller. The card controller 7 is activated by the supply of Vcc1 power and has an internally writable memory register. The attribute information, data, etc. of the memory card 1 are read into the memory register in response to the input of a read command from the CPU. Write. Reference numeral 9 denotes a memory that is activated by the supply of Vcc0. The memory 9 is at least the Vcc1 initial setting process, Vcc0 initial setting process, master card BIOS, and cold BIOS that will be described later.
S, Suspend BIOS, Resume BIOS, application software (hereinafter referred to as AP) and the like are provided.
Reference numeral 11 denotes a CPU which is activated by the supply of Vcc1 and which performs predetermined arithmetic processing according to a program in the memory 9.

Reference numeral 13 denotes a card monitoring unit which is activated when Vcc0 is supplied. The card monitoring unit 13 includes a decoder 14 and a card insertion / removal detection circuit 15. The decoder 14 becomes operative with the supply of Vcc0, and CP
Decode the read instruction from U11, the I / O read and the card insertion / removal data read completion signal, read the card status read signal, I / O read the interrupt clear write signal,
The card insertion / removal data read completion signal is output to the card insertion / removal detection circuit 15 as a mask control write signal. The card insertion / removal detection circuit 15 enters the operating state with the supply of Vcc0, receives the card status read signal, the interrupt clear write signal and the mask control write signal from the decoder 14, and the insertion / removal state of the memory card 1 is changed. In this case, the interrupt mask held in the internal flip-flop is released after the CPU 11 becomes ready for interrupt processing at the time of resume. Reference numeral 20 denotes a main power source, which uses, for example, a battery. Reference numeral 22 is a main switch, and 24 is a Vcc1 power supply that supplies Vcc1 when the main switch 22 is turned on. Reference numeral 26 is a Vcc0 power supply that supplies Vcc0 when the main switch 22 is turned on. 28 is a power transistor. The power transistor 28 is on / off controlled by the main control unit 30 to stop or supply Vcc1.

Next, the memory format of the memory 9 will be described. FIG. 2 is an explanatory diagram of the memory format. In the figure, 33 is a Vcc1 initialization process. The Vcc1 initial setting process 33 indicates that when Vcc1 is supplied, Vcc1 is supplied after performing initial setting processes such as operation check of each unit.
1 Output the power-on reset signal. 35 is Vcc0
Initial setting process. Initial setting process 35 for Vcc0
When it is found from the operating state of the memory 9 that Vcc0 is being supplied, the
After performing initial setting processing such as creation of a memory area based on the master card BIOS, a Vcc0 power ON reset signal is output. 37 is a master card BIOS.
When both Vcc0 and Vcc1 are supplied and the master card BIOS 37 is ready to accept insertion / removal of the memory card 1, the logic of the address terminal is set to a combination for reading insertion / removal of the card (hereinafter referred to as a read instruction). .

Further, the master card BIOS 37 suspends the output of the I / O read signal and disables the interrupt until the memory card 1 is determined to have been inserted in order to prioritize the initial setting process. When the memory card 1 is inserted, an I / O read signal is output to enter the interrupt enable state. Reference numeral 39 is a cold BIOS. Cold BIOS
39 is supplied with both Vcc0 and Vcc1, and the CPU
When 11 is in the interrupt enable state, a read instruction is output and the card information is written in the memory register of the card controller 7. 41 is a suspend BIOS. When the supply of Vcc1 is stopped, the suspend BIOS 41 saves and masks the card information written in the memory register of the card controller 7 in the user memory area 45 of the card BIOS of the memory 11. 43 is a resume BIOS. Resume BIOS 43 is V
When cc1 is supplied again, the card information of the user memory area is written in the memory register of the card controller 7, and the mask of the user memory area 45 of the card BIOS is released so that new card information is written.

Reference numeral 47 is an AP. AP47 is Vcc1
Is supplied, the card BIOS is started after the card BIOS processing, and predetermined processing is executed based on the flag of the memory register of the card controller 7. Next, a flow chart will be described. FIG. 3 is a flow chart for explaining the operation of the present invention. For example, when the suspend mode is resumed, the CPU 11 controls the BIOS 43
Based on the program, the register value indicating the card information in the user memory area 45 is written in the memory register of the card controller 7 (S1). Then, when it is ready to accept an interrupt, the card interrupt mask is released (S3). Next, it is determined whether or not there is an interrupt from the card monitoring unit 13 (S5), and when there is an interrupt, the register value written in the memory register of the card controller 7 is read to check whether or not there is the memory card 1. A determination is made (S7). Next, when it is determined that the memory card 1 is present, the card information is referred to from the register value (S9), and it is determined whether the memory card 1 is the same as before (S11). Next, when it is determined that they are not the same memory card 1, the card controller 7 and the memory card 1 are initialized (S13). If it is determined in step S11 that they are the same memory card 1, the process ends.

That is, when the same memory card 1 is used, A
Since P47 performs a predetermined process based on the register value of the card controller 7, the program does not run away. FIG. 4 is a schematic configuration diagram of the card insertion / removal detection circuit 15. In the figure, 51 is a pull-up resistor in which Vcc0 is added to one and the other is connected to a GND terminal 50 for a card.
Reference numeral 2 is a NOT circuit whose input side is connected to the GND terminal 50. 54 is a tri-state buffer. The tri-state buffer 54 has an input side connected to the output side of the NOT circuit 52 and an output side connected to the data terminal 0 of the CPU 11, and has a low impedance when a card status read signal is input from the decoder 14. 56 is NOT on the input side
It is a NOT circuit connected to the output side of the circuit 52 and the input side of the tri-state buffer 54. One of 58 is NO
A resistor connected to the output side of the T circuit 56, a resistor 58
The input side is connected to the other side of the NOT circuit, and 62 is a capacitor having a predetermined capacity, one side is connected to the other side of the resistor 58 and the input side of the NOT circuit 60, and the other side is connected to GND. 64
Is an exclusive OR. The exclusive OR 64 has one input side on the output side of the NOT circuit 60 and the other input side on the N side.
It is connected to the output side of the OT circuit 52, and when both inputs match, the output is set to L level, and when they do not match, H level is set. 66 is an AND circuit. The AND circuit 66 has a C
The Vcc0 power ON reset signal and the interrupt clear signal are input from the PU 11 to the input side, and the logical product of both signals is output.

Reference numeral 70 denotes a D flip-flop (hereinafter referred to as D-FF).
That is). The D-FF 70 inputs the output of the exclusive OR 64 to the clock terminal and the AND circuit 6 to the reset terminal.
When the output of 6 is input and the voltage of Vcc0 is input to the D terminal through a resistor and there is a signal at the clock terminal, the state of the D terminal is output and when there is a signal at the reset terminal, it is output. To the reset state. 71 is a D-FF. The D-FF 71 receives Vcc1 and Vcc from the CPU 11.
When 0 was supplied together, a signal (data 1) was input to the D terminal after a predetermined time, the Vcc1 power ON reset signal was input to the reset terminal, the mask control write signal was input to the clock terminal, and the signal was present at the clock terminal. At that time, the state of the D terminal is output, and when there is a signal at the reset terminal, the output is reset. 72 is an AND circuit. The AND circuit 72 inputs the outputs of the D-FF 40 and the D-FF 71 and outputs a logical product of both signals as an interrupt signal associated with card insertion / removal.

The operation of the card interface device configured as described above will be described below. First, the operation of the card insertion / removal detection circuit 15 will be described. FIG. 5 is a timing chart for explaining the operation of the card insertion / removal detection circuit 15. For example, when the main switch 22 is pressed, Vc
At the cold start when both c0 and Vcc1 are supplied, the card controller 7 and the CPU 11 are
As shown in FIG. 1, Vcc1 is supplied to the CPU 11 and the memory card 1, and Vcc0 is supplied to the card monitoring unit 10 and the memory 9. Then, the CPU 11 makes Vcc0 and Vc
Vcc0 power ON reset signal F is output (F is set to H level) and Vcc1 power ON reset signal K is output (K is set to H level) after the lapse of time ta for performing the initial setting process accompanying the supply of c1. To do. Therefore, since both signals F and K are at the L level during the time ta at the cold start, they are output as Vcc0 and Vcc1 power ON reset signals. At the cold start, Vc is applied to the resistor 51 of the card insertion / removal detection circuit 15.
c0 is supplied, so when there is no memory card 1,
The input A of the NOT circuit 52 goes high and the output B goes low.
Since it becomes the level, the input of the NOT circuit 56 and the other input of the exclusive OR 64 become the L level.

As for the card status signal, since the CPU 11 has not completed the initial setting operation at the time of cold start, the address data of the CPU 11 is all 0, so the card status read signal from the decoder 14 is set to H level. There is. That is, the card status read signal is not output to the tri-state buffer 54 at the cold start time. That is, while the card status read signal is not input to the tri-state buffer 54, the memory card 1 and the CPU 11 are electrically insulated. When the initial setting is completed, the CPU 11 sets the card status read signal to the L level for a predetermined time when the predetermined time ta has elapsed. That is, it is the output of the card status signal. Also, the NOT circuit 5
6 output D1 is memory card 1 at cold start
When is not inserted, the input side is at L level during that time, so the output D1 is at H level and the output D2 of the NOT circuit 60 is at L level. Therefore, when the memory card 1 is not inserted, both the B and D2 of the exclusive OR 64 are at the L level, and the output E is at the L level. That is, the clock signal is not output to the clock terminal of the D-FF 70 while the memory card 1 is not inserted.

At the time of cold start, the CPU
11 is, even if the memory card 1 is inserted,
Card interrupt IR because the initial setting has the highest priority for processing
The interrupt clear signal G is output (H level) so that Q is not output, and thereafter, the card interrupt acceptance state is entered, and every time the card insertion / removal data C is output, the output of the interrupt clear signal G is stopped after a predetermined time ( L level). Therefore, the interrupt clear signal G is output while the memory card 1 is not inserted after the cold start, and the logical product of the interrupt clear signal G and the Vcc0 power ON reset signal F is the AND circuit. Since the output H of 66 is output, the output H is at the L level during the time ta associated with the initialization processing of the CPU 11, and the output H is at the H level after the elapse of the time ta. And is output to the reset terminal of the D-FF 70. That is, D
In the -FF 70, the output I of the D-FF 70 becomes the L level even if the voltage of Vcc0 is applied to the D terminal.

Further, since the CPU 11 keeps all the data terminals 0 during the processing time ta accompanying the initial setting at cold start and until the card insertion / removal data C is output in the interrupt acceptance state, the data 1 Is set to the L level and is output to the D terminal of the D-FF 71, the card insertion / removal data C is read, and then the data 1 is set to the H level. Also,
Data 1 is set to H level from the cold start,
Until a predetermined time elapses, the mask control write signal L indicating that the minimum required program or data area of the memory is masked is output (H level) to the clock terminal of the D-FF 71. That is, while the mask control write signal L is at H level, the D-FF 7
The output M of 1 becomes L level and is output to the AND circuit 72. Therefore, since the signal I and the signal M are input at the L level to the input of the AND circuit 72, the output IRQ remains at the L level, so that the memory card 1 is not operated during the time ta of the initialization process accompanying the cold start. When it is not inserted, the IRQ is not output from the AND circuit 72 to the CPU 11.

Next, a case will be described in which both Vcc0 and Vcc1 are continuously supplied and the memory card 1 is inserted. When the memory card 1 is inserted in such a state, the other of the resistors 51 of the card insertion / removal detection circuit 15 is connected to the GND of the memory card 1, so the memory card 1
The input A of the NOT circuit 52 is at the L level and the output B is at the H level while the signal is inserted. Further, the output D1 of the NOT circuit 56 tends to become L level as the memory card 1 is inserted, but since the discharge of the resistor 58 and the capacitor 62 starts, it becomes L level after the elapse of this discharge time. Further, the output D2 of the NOT circuit 60 becomes H level after the output D1 of the NOT circuit 56 becomes L level. That is,
When the memory card 1 is inserted, the output D2 of the NOT circuit 60 does not immediately go to the L level, but goes to the L level after the discharge is completed and is input to one of the exclusive OR 64. Therefore, since the exclusive OR 64 receives the output B of the NOT circuit 52 and the output D2 of the NOT circuit 60, the output E is set to H level during discharging, and then becomes L level. It is output to the clock terminal of the D-FF 70.

Further, the CPU 11 outputs a card status read signal after a lapse of a predetermined time after the discharge is completed, and sets the tristate buffer 54 to a low impedance CP.
U11 and the memory card 1 are electrically connected.
In this case, since the memory card 1 is inserted, the card insertion / removal data C is output at H level. Also, CP
Since U11 has not completed the card interrupt process associated with the generation of IRQ, it still sets the interrupt clear signal G to the H level. Therefore, the output H of the AND circuit 66 is still at the H level and is output to the reset terminal of the D-FF 70, so that the D-FF 70 does not enter the reset state. Therefore, the D-FF 70 outputs the state of the D terminal when the state of the clock terminal changes to the H level with the insertion of the memory card 1. In this case, since the potential Vcc0 is applied to the D terminal, the output I is at H level. Since the data 1 is at L level and the mask control write signal L is at H level, the output M of the D-FF 71 remains at H level.

Therefore, since the AND circuit 72 outputs the logical product of the output I of H level and the output M of H level, the IRQ is output to the CPU 11 when the memory card 1 is inserted. When the CPU 11 outputs the card status read signal to set the tristate buffer 54 to a low impedance and electrically connects the memory card 1 and the CPU 11, when the card insertion / removal data C is at the H level, the CPU 11 After determining that the memory card 1 is present, the output of the card interrupt clear signal G is stopped (L level) for a predetermined period in order to accept a card interrupt. this,
When the card interrupt clear signal G is stopped, A
The output H of the ND circuit 66 becomes L level and the D-FF 70
It is output to the reset terminal of. That is, since the D-FF 70 is in the reset state, the output I of the D-FF 70 becomes L level and is output to the AND circuit 72. Therefore, A
The output IRQ of the ND circuit 72 becomes L level. That is,
When the CPU 11 knows that a card interrupt has occurred and that the memory card 1 has been inserted, it ends the predetermined processing. Next, a case will be described in which both Vcc0 and Vcc1 are continuously supplied and the memory card 1 is removed.

When the memory card 1 is removed in this state, Vc is applied to the resistor 51 of the card insertion / removal detection circuit 15.
Since c0 is supplied, the input A of the NOT circuit 52 is at H level and the output B is at L level while the memory card 1 is removed.
It becomes a level. Further, the output D1 of the NOT circuit 56 tends to become H level as the memory card 1 is removed, but since the charging of the resistor 58 and the capacitor 62 starts, it becomes H level after the elapse of this charging time. Also,
The output D2 of the NOT circuit 60 is the output D1 of the NOT circuit 56.
Becomes H level and then becomes L level. That is, when the memory card 1 is removed, the output D of the NOT circuit 60
2 does not reach the H level immediately, but goes to the H level after charging is completed and is input to one of the exclusive ORs 64. Therefore, since the exclusive OR 60 receives the output B of the NOT circuit 52 and the output D2 of the NOT circuit 60, the output E is changed from the L level to the H level during charging, and then the L level is output. Is output to the clock terminal of the D-FF 40. Therefore, the output I of the D-FF 70 changes from the L level to the H level when the memory card 1 is removed, and the AND circuit 72 outputs the IRQ of the H level.

When the CPU 11 outputs a card status read signal to set the tristate buffer 54 to a low impedance and electrically connects the memory card 1 and the CPU 11, when the card insertion / removal data C is at the L level. After determining that the memory card 1 has been removed, the CPU 11 stops the output of the card interrupt clear signal G for a predetermined period (L level) to accept a card interrupt. When the card interrupt clear signal G is stopped,
During that time, the output H of the AND circuit 66 becomes L level and D
-It is output to the reset terminal of FF70. That is, D-
Since the FF 70 is in the reset state, the output I of the D-FF 70 becomes L level and is output to the AND circuit 72.
Therefore, the output IRQ of the AND circuit 72 becomes L level. In other words, the CPU 11 knows that a card interrupt has occurred,
Moreover, the predetermined processing is ended by knowing that the memory card 1 has been removed. Next, a case where the supply of Vcc1 is stopped (suspend state) will be described. When the memory card 1 is pulled out and becomes the suspend state, the supply of Vcc1 to the card controller 7 and the CPU 11 is stopped, so that the CPU 11 writes the card information written in the memory register of the card controller 7 to the memory 1
The data is saved in the user memory area 45 of the first card BIOS and masked, and the data save flag is written in the card controller 7.

The card insertion / removal detection circuit 15 has Vcc
Since 0 is supplied, the output I of the D-FF 70 is at the L level, which is the same as when the memory card 1 is removed. However, since the supply of Vcc1 was stopped, Vcc1
The cc1 power-on reset signal K is immediately set to the L level when the supply of Vcc1 is stopped. Since Vcc0 is supplied to the decoder 14, the mask control signal L is still output. That is, D-FF7
Since the Vcc1 power ON reset signal K of L level is input to the reset terminal of 1, the output M immediately becomes L level, and the output IRQ of the AND circuit 72 remains L level. Therefore, if the supply of Vcc1 is stopped and there is no change in the insertion or removal of the memory card 1, the card interrupt signal IRQ is not output. Then, when the memory card 1 is inserted in the suspend state, the other of the resistors 51 of the card insertion / removal detection circuit 15 is connected to the GND of the memory card 1, so that N is maintained while the memory card 1 is inserted.
The input A of the OT circuit 52 becomes L level and the output B becomes H level. Further, the output D1 of the NOT circuit 56 tends to become L level as the memory card 1 is inserted, but the resistor 58
Also, since the discharge of the capacitor 62 starts, it becomes L level after this discharge time has elapsed. Further, the output D2 of the NOT circuit 60 becomes H level after the output D1 of the NOT circuit 56 becomes L level.

That is, when the memory card 1 is inserted, the output D2 of the NOT circuit 60 does not immediately go to the L level, but goes to the L level after the discharge is completed and is input to one of the exclusive OR 64. To do. Therefore, exclusive OR 6
4 is the output B of the NOT circuit 52 and the output D of the NOT circuit 60
Since 2 is input, output E is set to H while discharging.
Set to level and then to L level D-FF70
Since it is output to the clock terminal of, the output of the D-FF 70 becomes H level and is output to the AND circuit 72. However, when the supply of Vcc1 is stopped, Vcc1 power O
Since the N reset signal K is stopped (L level),
The output M of the D-FF 71 does not change. That is, Vcc
When the memory card 1 is inserted while the supply of 1 is stopped, the card interrupt signal IRQ is not generated. Then, after a lapse of time, Vcc1 again
Is supplied, the Vcc1 power ON reset signal K immediately goes to the H level, but the output M of the D-FF 71 does not change, and the output I of the D-FF 70 does not change at the H level.

Therefore, according to the present invention, when the CPU 11 initializes when the suspend mode is resumed,
The data 43 is set to H level (interrupt enable signal is output) and the mask control write signal L is output by the BIOS 43 at the time of resume controlling the suspend / resume even if the interrupt is not accepted. Therefore, the output M of the D-FF 71 changes from the L level to the H level and is output to the AND circuit 72, so that the AND circuit 72 outputs IRQ,
Since the process is performed according to the flowchart of FIG. 3 described above, the insertion / removal of the memory card 1 can be detected regardless of whether the Vcc1 is stopped or supplied. That is, even if the card is inserted / removed in the suspended state, the access will not be disabled during the resume. Further, when the software is divided into the BIOS controlling the card control and the BIOS controlling the suspend / resume, the suspend / resume BIOS saves, recovers and unmasks.

[0026]

As described above, according to the present invention, the first power source is supplied to the memory card, the card controller and the arithmetic section, and the second power source is supplied to the card monitoring section and the memory. The arithmetic unit, when the first and second power supplies are supplied,
After the initial setting, the card controller is controlled to read the information of the memory card, and when the supply of the first power supply is stopped, the information of the memory card is saved and masked in a predetermined area of the memory. When the power is supplied again, write the saved information to the card controller,
The mask is released so that the information of the new card controller is written in a predetermined area of the memory, and when there is a card interruption, the card reading process is executed based on the information of the predetermined area of the memory. In addition, the card monitoring unit is activated based on the supply of the second power supply, detects insertion or removal of the memory card, and generates a card interrupt signal when the memory card is inserted or removed. Therefore, even if the memory card is exchanged, it is not possible to access the program, and the program does not run out of control.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of an embodiment.

FIG. 2 is an explanatory diagram of a memory format.

FIG. 3 is a flowchart explaining the operation of the present invention.

FIG. 4 is a schematic configuration diagram of a card insertion / removal detection circuit.

FIG. 5 is a timing chart for explaining the operation of the card insertion / removal detection circuit.

[Explanation of symbols]

1 memory card 7 card controller 9 memory 11 CPU 13 Card monitoring section 14 Decoder 15 Card insertion / removal detection circuit

Claims (2)

(57) [Claims] 1. A card interface device for supplying a first power supply to a memory card, a card controller and a computing unit, and supplying a second power supply having a voltage different from the first power supply to a card monitoring unit and a memory. Te, before Symbol arithmetic unit when said first and second power source is supplied, after the initial setting, and means for controlling the card controller reads the information of the memory card, the second power supply Means for saving and masking information of the memory card in a predetermined area of the memory when supply of the first power supply is stopped during supply, and when supply of the first power supply is supplied again, means for writing the saved information to the card controller, when the supply of the first power source is supplied again to release the mask of a predetermined area of the memory, where the memory Area
A new piece of the card controller of the information write Murrell to
Means for sea urchin, when a card interrupt, and means for implementing the card reading processing based on the information of a predetermined area of the memory, the card monitoring unit, the supply of the second power supply A card interface device comprising means for detecting the insertion or removal of the memory card, and generating a card interrupt signal when the memory card is inserted or removed. Wherein when the supply of the first power source is supplied again, and means for writing the information the saved to the card controller, when the supply of the first power is supplied again, the memory unmask predetermined region, before
Serial card interface device of claim 1, wherein the the means for new information of the card controller in a predetermined area to write Murrell so carried by the card BIOS memory.