JP2002351585A - Computer system, power feeding device and power feeding method of computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption when a computer with a mini PCI card or a device corresponding to the mini PCI card inserted thereinto is in an inactive state. SOLUTION: An I/O bridge 21 for outputting inactive information about whether or not a computer system is in an inactive state and a Vaux off at sleep resister 42d holding information about whether or not to feed auxiliary power VccAUX to a mini PCI device 60 when the computer system is inactive, are provided. When a signal from the I/O bridge 21 is L and a signal from the register 42d is L, the feeding of the auxiliary power VccAUX is stopped from a DC/DC converter 55.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a function (wake-up function or wake-up function) of turning on a power source by a remote control used in a personal computer (PC) such as a notebook personal computer (notebook PC). -On-LAN function).

[0002]

2. Description of the Related Art In one company, a large number of Ps are required to reduce the total cost including system maintenance.
For example, there is a case where the user wants to simultaneously rewrite a program for C. In such a case, the power supply is turned off without operator intervention for each PC.
n is required. For such a request,
PC's BIOS (Basic Input / Output System), OS (Op
erating System), a network card, or the like, there is a method of activating the PC by Wake-On-LAN. This Wake-On-LAN is
This is a function of turning on the power of a computer located at a place remote from the computer at hand and starting it. This is a technology of turning on the power by an instruction from a network based on a remote operation instead of turning on the power by hand. .

[0003]

This technique can be realized through a miniPCI card mounted in a PC. In other words, the system (PC) sleeps
Alternatively, even in a suspended state such as suspend, power is always supplied to the miniPCI card, and the system is powered on in response to a command defining a Wake-On-LAN from a remote location. The problem here is that power is always supplied to the miniPCI card even in the hibernation state. The system consumes power even in the sleep state, but the miniPCI card increases its consumption. According to a study by the present inventor, in the case of a notebook PC, the power of the built-in battery lasts for about 8 days in the hibernation state, but when the miniPCI card is inserted, the power of the battery is consumed in about 4 days. Therefore, for example, when the notebook PC is carried on a business trip or the like, the system may not be activated. Also, if the PC is used in a state where the Wake-On-LAN function cannot be used, power is wasted. Therefore, the present invention
It is an object to provide a system capable of smoothly reducing power consumption even when a computer equipped with a miniPCI card or a device equivalent thereto is in a hibernation state.

[0004]

SUMMARY OF THE INVENTION According to the present invention, there is provided a boot control means for receiving an auxiliary power and controlling the start of a system according to an external instruction, and for generating and supplying the auxiliary power to the boot control means. An auxiliary power supply generating means for outputting the auxiliary power to the activation control means when the system is in a hibernation state; a hibernation state output means for outputting halt information as to whether the system is in a hibernation state; Supply permission / prohibition setting means for holding setting information on whether or not to perform, based on the pause information from the pause state output means and the setting information retained by the supply permission / prohibition setting means, from the auxiliary power generation means A computer device comprising: an auxiliary power supply availability determining unit that determines whether to supply the auxiliary power to the activation control unit.

If the auxiliary power supply is turned on and off when the system is not in the sleep state, some functions may not operate normally. Therefore, the computer device of the present invention, based on the sleep information from the sleep state output means and the setting information held by the supply availability setting means, from the auxiliary power generation means to the start control means, Determine whether to supply auxiliary power.
That is, the computer device of the present invention can determine whether or not to supply the auxiliary power after confirming the suspension information of the system, so that it is possible to eliminate the possibility that some function does not operate normally. Therefore, miniP
Even if the computer on which the CI card or a device corresponding thereto is mounted is in a hibernation state, power consumption can be reduced smoothly.

[0006] Whether the auxiliary power can be supplied to the computer device of the present invention can be determined as follows. That is, in the computer device of the present invention, the auxiliary power supply availability determination means outputs the sleep information indicating that the system is in the sleep state by the sleep state output means, and performs the startup when the system is in the sleep state. When the supply permission / prohibition setting unit holds information indicating that the auxiliary power is not supplied to the control unit, it is possible to determine that the auxiliary power is not supplied to the activation control unit. The computer apparatus of the present invention may further include main power generation means for generating main power to be supplied to a device mounted in the system, and sleep information indicating that the system is in a sleep state from the sleep state output means. Main power supply availability determination means for determining to stop the supply of the main power to the device to the main power generation means when output, the halt information indicating that the system is halt The main power supply is provided when the supply enable / disable setting unit holds information indicating that the auxiliary power is not supplied to the activation control unit when the sleep state output unit emits and the system is in the sleep state; The supply of the auxiliary power from the auxiliary power generation means can be stopped after the supply of the main power from the generation means is stopped. That is, the stop of the supply of the main power is performed prior to the stop of the supply of the auxiliary power.

Further, in the computer apparatus of the present invention, the auxiliary power supply availability determining means outputs sleep information indicating that the system is not in a sleep state, the sleep state output means outputs the sleep information, and sets the system in a sleep state. The auxiliary power supply can be supplied to the activation control unit when the supply permission / prohibition setting unit holds information indicating that the auxiliary power is not supplied to the activation control unit. Further, in the computer apparatus according to the present invention, main power generation means for generating main power to be supplied to a device mounted in the system, and sleep information indicating that the system is in a sleep state from the sleep state output means. And main power supply availability determination means for determining to stop the supply of the main power to the device to the main power generation means when is output, wherein the system cancels the sleep state. When the sleep state output means outputs the sleep information, and the supply availability setting means holds information indicating that the auxiliary power is not supplied to the activation control means when the system is in the sleep state. After the supply of the auxiliary power from the auxiliary power generation means is restarted, the supply of the main power from the main power generation means can be restarted. That is, the restart of the supply of the main power is performed prior to the restart of the supply of the auxiliary power.

Further, the present invention provides a main power supply for supplying a main power, an auxiliary power supply for supplying an auxiliary power, and a first power supply for receiving a main power supplied from the main power supply. Power consuming means, second power consuming means for receiving a supply of auxiliary power from the auxiliary power supply section, supply of main power from the main power supply section and auxiliary power from the auxiliary power supply section Power supply for controlling the supply of power to the first power consuming means, and instructing to stop supplying the auxiliary power to the second power consuming means after stopping the supply of the main power to the first power consuming means Control means;
A computer device comprising: In the computer apparatus of the present invention, the power supply control unit instructs to stop supplying the auxiliary power to the second power consuming unit after stopping supplying the main power to the first power consuming unit. I do. Therefore, in the computer device of the present invention, the supply of the main power is stopped at the stage of stopping the supply of the auxiliary power, that is, the operation of the CPU of the computer device is also stopped, so that the possibility that some function does not operate normally is eliminated. be able to.

The computer apparatus of the present invention can control the supply of the main power and the supply of the auxiliary power while the computer apparatus is in a halt state. That is, the computer device of the present invention includes a sleep state output unit that outputs sleep information as to whether the computer device is in a sleep state, and the power supply control unit transmits the sleep information from the sleep state output unit to the sleep information. The main power supply from the main power supply unit and the auxiliary power supply from the auxiliary power supply unit can be controlled based on the main power supply unit. In the present invention,
Auxiliary power supply stop setting means for setting the supply of the auxiliary power to the second power consuming means to be stopped when the computer device is in a hibernation state, wherein the power control means comprises a hibernation state output means The auxiliary power supply from the auxiliary power supply unit can be stopped based on the sleep information from the CPU and the setting by the auxiliary power supply stop setting unit.

In the present invention, the power supply control means can not only stop the supply of the auxiliary power but also stop the supply of the main power from the main power supply unit when the computer device is in a halt state. Further, in the present invention, when the computer device shifts to a hibernation state, the power supply control means stops the supply of the main power to the first power consumption means, and then stops the main power supply to the second power consumption means. An instruction to stop the supply of the auxiliary power can be issued in conjunction with the sleep information from the sleep state output means. Further, in the present invention, when the computer device returns from the hibernation state, the power supply control means restarts the supply of the auxiliary power to the second power consumption means and then supplies the first power consumption means to the second power consumption means. Resuming the supply of the main power,
An instruction can be given in conjunction with the sleep information from the sleep state output means.

The present invention can be applied not only to a computer device but also to a power supply device generally used for electric equipment. Therefore, the present invention is a power supply device for supplying power to a predetermined power consuming means provided in an electric device, and supplies the power to the power consuming means based on an externally supplied power. A power generation unit that generates power, a supply stop setting unit that holds setting information for stopping supply of power to the power consuming unit when the electric device is in a sleep state, and a transition to the sleep state of the electric device. Sleep state detecting means for detecting whether to perform or return from the sleep state, and when the sleep state detection means detects whether the electric device shifts to the sleep state or returns from the sleep state, the supply stop setting means And a power supply control unit that instructs a stop of power supply to the predetermined power consumption means in accordance with the setting information. .

In the present invention, the predetermined power consuming means may perform a function of releasing the sleep state of the electric device by remote control. For example,
miniPCI card is applicable. Further, in the present invention, when the function for canceling the hibernation state of the electric device by remote control in the predetermined power consuming means is invalid, the power control section controls the power supply to the predetermined power consuming means. The supply stop can be instructed. Further, in the present invention, a user of the electric device can set that the function for canceling the sleep state of the electric device is effective by the predetermined power consuming means. In addition, this setting can be set based on the usage environment of the electric device in addition to the user setting. For example, when the electric device is a computer device, the computer device is connected to a LAN.
(Local Area Network) based on whether or not the predetermined power consuming means is effective for canceling the sleep state of the electric device.

The present invention provides the following advantageous power supply method for a computer device. That is, the power supply method of the present invention is a power supply method for a computer device having a wake-up function by remote control, and determines whether or not to use the wake-up function when the computer device is in a sleep state. Setting a step; setting whether to stop power supply for performing a wake-up function when the computer device is in a sleep state; and setting whether the computer device is in a sleep state. Determining that the computer device is in a hibernate state and the computer device is in a hibernate state when the computer device is set to not use the wake-up function when the computer device is in a hibernate state. When the power supply for executing the wake-up function is set to It is a power supply method for a computer apparatus according to claim which comprises a step of stopping the power supply to run the microphone-up function, a.

In the present invention, the step of stopping the power supply for executing the wake-up function includes the step of supplying power to a device of the computer device which does not need power supply when the computer device is in a sleep state. It is desirable to perform the operation in synchronization with the stop of the operation. Further, in the power supply method of the present invention, when the computer device returns from the sleep state, the power supply for performing the wake-up function is resumed, and the power supply is not required when the computer device is in the sleep state. It is preferable that the power supply to the device of the computer be restarted in synchronization with the power supply. Here, the devices of the computer device that do not need power supply when the computer device is in the halt state include a CPU, a HDD (Hard Disc Drive), and the like.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on embodiments shown in the accompanying drawings. FIG. 1 is a diagram showing a hardware configuration of a computer system 10 according to the present embodiment. This computer system 10
A computer device provided with, for example, OADG (Open
It is configured as a notebook PC (notebook type personal computer) on which a predetermined OS (operating system) is mounted in conformity with the Architecture Developer's Group) specifications.

In the computer system 10 shown in FIG. 1, a CPU 11 functions as the brain of the entire computer system 10, and executes various programs under the control of the OS. The CPU 11 is an FSB which is a system bus.
(Front Side Bus) 12, PCI (Peripheral Component Interconnect) bus 2 as a high-speed I / O device bus
ISA (Industry S) as a bus for low-speed I / O devices
Each component is interconnected via a three-stage bus called a “tandard architecture” bus 40. This CPU
No. 11 achieves high-speed processing by storing program codes and data in a cache memory. In recent years, 128K has been
A SRAM of about bytes is integrated, but in order to compensate for the shortage of capacity, a dedicated bus BSB (Back Side Bus)
A secondary cache 14 of about 512 Kbytes to 2 Mbytes is placed via the storage 13. In addition, BSB13 is omitted and FS
By connecting the secondary cache 14 to B12 and avoiding a package having a large number of terminals, the cost can be reduced.

The FSB 12 and the PCI bus 20 are connected to a memory /
CPU bridge called PCI chip (host-PC
I bridge 15). This CPU
The bridge 15 has a memory controller function for controlling an access operation to the main memory 16 and the FSB 12.
And a data buffer for absorbing a difference in data transfer speed between the PC and the PCI bus 20.
The main memory 16 is a writable memory used as a read area of the execution program of the CPU 11 or a work area for writing processing data of the execution program. For example, it is composed of a plurality of DRAM chips, for example, 64 MB is provided as standard equipment, and can be expanded to 320 MB. This execution program includes the OS
Drivers for operating hardware and peripheral devices, application programs for specific tasks, and BIO stored in a flash ROM 44 described later
S (Basic Input / Output System)
Etc. are included.

The video subsystem 17 is a subsystem for implementing functions related to video, and includes a video controller. The video controller processes a drawing command from the CPU 11, writes the processed drawing information to a video memory, reads the drawing information from the video memory, and reads the drawing information from a liquid crystal display (LC).
D) 18 to output as drawing data.

The PCI bus 20 is a bus capable of relatively high-speed data transfer, and has a data bus width of 32 bits or 64 bits, a maximum operating frequency of 33 MHz, and 66 MHz.
z, maximum data transfer rate 132MB / s, 528MB / s
It is standardized by the specification of seconds. The PCI bus 20 includes an I / O bridge 21, a card bus controller 22, an audio subsystem 25, a docking station interface (Dock I / F) 26, a miniP
The CI connectors 27 are respectively connected.

The card bus controller 22 is a dedicated controller for directly connecting a bus signal of the PCI bus 20 to an interface connector (card bus) of the card bus slot 23.
, A PC card 24 can be loaded. The docking station interface 26 is hardware for connecting a docking station (not shown) which is a function expansion device of the computer system 10. When the notebook PC is set in the docking station, various hardware elements connected to the internal bus of the docking station are connected to the PCI bus 20 via the docking station interface 26. In addition, the mini PCI connector 27 has a mini PCI (m
iniPCI) device 60 is connected. The miniPCI device 60 is an expansion card (board) that can be added in accordance with the miniPCI specification. This miniPCI is a PCI standard for mobile devices and is listed as an appendix to the PCI Rev.2.2 specification. Functionally full specification PCI
Is equivalent to

The I / O bridge 21 has a bridge function between the PCI bus 20 and the ISA bus 40. Also,
DMA controller function, programmable interrupt controller (PIC) function, programmable interval timer (PIT) function, IDE (Integrated Device Ele)
ctronics) interface function, USB (UniversalSer)
ial Bus) function, SMB (System Management Bus) interface function and real-time clock
(RTC).

The DMA controller function performs data transfer between a peripheral device such as an FDD and the main memory 16 by a CPU.
11 is a function to be executed without intervention. The PIC function is a function for executing a predetermined program (interrupt handler) in response to an interrupt request (IRQ) from a peripheral device. The PIT function is a function for generating a timer signal at a predetermined cycle. The interface realized by the IDE interface function is connected to an IDE hard disk drive (HDD) 31 and a CD.
-The ROM drive 32 has an ATAPI (AT Attachment Pac
ket Interface) is connected. Instead of the CD-ROM drive 32, another type of IDE device such as a DVD (Digital Versatile Disc) drive may be connected. The external storage devices such as the HDD 31 and the CD-ROM drive 32 are stored in a storage location called “media bay” or “device bay” in the notebook PC body, for example. These standard external storage devices are
In some cases, it may be exchangeably and exclusively attached to other devices such as an FDD or a battery pack.

The I / O bridge 21 is provided with a USB port. The USB port is connected to, for example, a USB connector 30 provided on a side wall surface of the notebook PC body.
Is connected to Further, the I / O bridge 21 has S
An EEPROM 33 is connected via the M bus. The EEPROM 33 is a memory for storing information such as a password registered by a user, a supervisor password, and a product serial number, and is nonvolatile and electrically rewritable.

Further, the I / O bridge 21 is connected to a power supply circuit 50. The power supply circuit 50 charges an AC adapter 51, a main battery 52 or a second battery 53 as a battery (secondary battery), and
1 and a battery switching circuit 54 for switching a power supply path from each battery, and a DC / DC for generating a DC constant voltage of 5 V, 3.3 V, etc. used in the computer system 10.
A circuit such as a converter (DC / DC) 55 is provided.

On the other hand, an internal register for managing the power state of the computer system 10 and a management of the power state of the computer system 10 including the operation of the internal register are provided inside the core chip constituting the I / O bridge 21. A logic (state machine) for performing the operation is provided. The logic transmits and receives various signals to and from the power supply circuit 50, and recognizes the actual power supply state from the power supply circuit 50 to the computer system 10 by transmitting and receiving the signals. The power supply circuit 50 controls the power supply to the computer system 10 according to the instruction from the logic.

The ISA bus 40 has a lower data transfer speed than the PCI bus 20 (for example, a bus width of 16).
Bits, maximum data transfer rate 4MB / s). The ISA bus 40 includes an embedded controller 41, a CMOS 43, and a flash ROM connected to a gate array 42.
44, a Super I / O controller 45 is connected. It is also used to connect relatively slow peripherals such as keyboard / mouse controllers. An I / O port 46 is connected to the Super I / O controller 45 to drive an FDD or input / output parallel data (PI) through a parallel port.
O), input / output of serial data through serial port
(SIO).

The embedded controller 41 controls a keyboard (not shown) and is connected to a power supply circuit 50, and a built-in power management controller (PMC).
er) performs a part of the power management function together with the gate array 42.

FIG. 2 is a diagram for explaining the contents of power supply in the present embodiment. In the present embodiment, mi
The niPCI device 60 has a function of receiving a command to define a wake-up from a remote place via a LAN or a telephone line, and turning on the system. That is, it can be said that the miniPCI device 60 has a function as activation control means for controlling activation of the computer system 10. miniPCI device 60
Specifically, Ethernet (registered trademark) (Ethe
rnet (registered trademark)) or a modem (Modem). A voltage of 100 to 240 V AC is supplied from an external commercial AC power supply to the AC adapter 51 shown in FIG.
Is converted to The DC / DC converter 55 converts the input 16V DC voltage to 5V, 3.3V VccMAIN,
It generates a DC constant voltage of 3.3V VccAUX, which is an auxiliary power supply. That is, the DC / DC converter 55 generates a main power supply and an auxiliary power supply. This auxiliary power supply VccAUX is set to P to enable automatic power supply On.
It is supplied to the CI bus 20. Gate array 42
Has an OR gate 42a, an AND gate 42b, an OR gate 42c, and a Vaux Off at Sleep register 42d. An AND gate 70 is provided between the I / O bridge 21 and the DC / DC converter 55.

A control signal used in the above power supply control circuit will be described. <AC Adapter Presence> Computer System 10
A control signal indicating whether or not the AC adapter 51 is connected to the
High level (High Level) when 1 is connected
l, which is indicated by H in the figure, and hereinafter also referred to as H), and when the AC adapter 51 is not connected, a low level (Low L
evel, which is indicated by L in the figure and is also L) is the gate array 4
2 is output. <POWERON> The signal generated from the state of the power switch is P
OWERON. In other words, the power switch is set to On (Power On)
Is output to the gate array 42 and the AND gate 70 when the power switch is Off (Power Off).

<SleepState> SleepState is a signal output from the I / O bridge 21 and is a signal output from the computer system 10.
Is in sleep (hibernation) mode or normal power
Indicates whether the status is On (Normal Power On). SleepState
Is supplied to an AND gate 70. BIOS uses I / O
When a write operation is performed on the Suspend Enable register 21a of the bridge 21, this signal becomes L. When the I / O bridge 21 detects a command to return from the sleep state (Resume Request) in the sleep state, this signal becomes H, and the computer system 10 returns from the sleep state to the normal Power On state (Resume Request). ). <VccMAIN_ON> A device that does not need to be supplied with power in the Power Off state and the sleep state, for example, C
This signal controls On / Off of VccMAIN, which is a power supply supplied to devices such as the PU 11, the HDD 31, and the LCD 18. That is, VccMAIN is turned ON only in the Power On state. This signal is "POWERON"
And "SleepState" are generated as a logical product (AND). Note that VccMAIN_ON is H when VccMAIN is turned on,
It becomes L when VccMAIN is turned off. <VccAUX_ON> WAKE-ON-LAN of miniPCI device 60
This signal controls On / Off of VccAUX which is an auxiliary power supply for the function. This signal is output from the gate array 42 to the DC / DC converter 55. When the output signal is H, VccAUX is On, and when the output signal is L, VccAUX is Off.

Next, the configuration and operation of the gate array 42 will be described. OR gate 42a is connected to AC adapter
Take the logical OR of POWERON. Therefore, AC adapter 5
When 1 is connected or the power switch is turned on, an H signal is output to the AND gate 42b as a logical sum. Conversely, if the AC adapter 51 is not connected and the power switch is off, the L signal is output. Vau
x Off at Sleep register 42d is VccAU
This is an element for making On / Off of X controllable, and its register value is defined as follows. That is, when the register value is 0, V
Turn off ccAUX, and if the register value is 1, Vc
Keep cAUX on. When this register value is 0, the signal inside the gate array becomes L, and when it is 1, it becomes H
Becomes When entering sleep mode, the BIOS
Write to the x Off at Sleep register 42d. The OR gate 42c turns off VccAUX in synchronization with VccMAIN when shifting to the sleep state, and turns off VccAUX in synchronization with VccMAIN when returning from the sleep state.
n. If the Vaux Off at Sleep register 42d is directly connected to the AND gate 42b without passing through the OR gate 42c, VccAUX will be turned off at the moment when the BIOS writes the value "0" to the OR gate 42c. Or, considering the return from the sleep state,
When VccMAIN is turned on and the operation of the CPU 11 or the like is started, the BIOS operates to write '1' to this register, and then VccAUX returns to On. Vaux Offat Sleep register 42 to prevent it
The logical product of the negative logic of d and Sleep State is calculated, the output is set to L only when both are L, and VccAUX_ON is set to L via the AND gate 42b. The AND gate 42b is a means for determining whether or not the auxiliary power can be supplied.
Is that the output of the OR gate 42a is H and the output of the OR gate 42c is H. Thus, even when the output of the OR gate 42a is H, if the output of the OR gate 42c is L, VccAUX can be turned Off. Specifically, even when the system is in the Power On state (the output of the OR gate 42a is H at this time), depending on the condition, that is, the output of the OR gate 42c, VccAUX is set to O.
ff.

Computer system 1 performing the above operation
At 0, the correspondence between each control signal and VccMAIN and VccAUX is shown in FIG. VccMAIN is ON because POWERON
And SleepState are both H (No.
1, 3, 9, 11). This can be regarded as a state in which the user starts and uses the computer system 10. Conversely, when one of POWERRON and SleepState is L, VccMAIN becomes Off (No.
2,4-8,10,12-16). It can be considered that the power switch of the computer system 10 is in the off or sleep state. VccAUX becomes Off when both the AC adapter presence and POWERON are L (Nos. 4, 12, and 16 in FIG. 3). VccAUX is V
When both the aux Off at Sleep register 42d and the SleepState are L, the signal is turned off (Nos. 5 to 8 in FIG. 3). The BIOS can respond to a request to turn VccAUX off when the computer system 10 shifts to the sleep state according to a user's instruction. In all other cases, VccAUX is turned on. VccAUX is output to the PCI bus 20 as shown in FIG. Since VccAUX is supplied to the mini PCI device 60 via the PCI bus 20, the computer system 10 can use the WAKE-ON-LAN function.

In the present embodiment, VccAUX is set to the sleep state.
The feature is that the function to stop the supply of the water is added. This characteristic function is realized by a control method described below in addition to the configuration of the gate array 42 described above. This control method can be roughly divided into the following four procedures. Procedure 1. Setting for obtaining control by BIOS Procedure 2. Mini PCI device 60 immediately before sleep
Investigating the setting of the procedure Step 3. Control of VccAUX power supply Procedure 4. Transition of Computer System 10 to Sleep State Among the above, procedure 1 is executed before OS initialization, whereas steps 2 to 4 are executed when transitioning to the sleep state. Hereinafter, each procedure will be described.

Procedure 1. Settings for control acquisition by BIOS Windows 2000 and Windows 98 / ME
(A registered trademark of Microsoft Corporation in the United States)
In the OS, it is O to put the system into the sleep state.
S. Therefore, the BIOS cannot obtain control immediately before the system shifts to the sleep state. Therefore,
By using an I / O trap method, the BIOS can obtain control immediately before going to sleep. Hereinafter, the method will be described. 1) ACPI BIOS has Advanced Configuration and
Power Interface Specification Rev. 1.0b (hereinafter A
Fixed ACPI Descrip as defined in CPI 1.0b)
In the Action Table (hereinafter referred to as FACP), an I / O address for shifting the system to a sleep state is presented to the OS. This I / O address is owned by the I / O bridge 21 and is called Suspend Enable (SUS_EN). The OS shifts the system to a sleep state by writing a value directly to the I / O address. For this reason, the BIOS cannot participate in the transition of the system state. Therefore, as shown in FIG.
The OS presents a fictitious I / O address to the OS, and
S is prevented from directly going to the sleep state.

2) The BIOS sets the I / O bridge 21 so that control can be obtained when the OS writes to the virtual address. That is, as shown in FIG.
The fictitious address presented in S is registered, and a setting is made so as to monitor writing to the address. This is generally called an I / O trap. Actually the address
When the (fictitious address) is written, SMI H
Control is immediately passed to the BIOS called the "handler".

Procedure 2. MiniPCI just before sleep
Investigation of the setting of the device 60 By the setting of the procedure 1, when the OS attempts to shift the system to the sleep state and writes to the fictitious I / O address, the BIOS can gain control. The processing at this time is performed by the above-mentioned processing called SMI Handler. The processing performed here will be described below. 1) Confirm that the mini PCI device 60 is attached to the system,
Read and confirm the Device ID and Vender ID. At this time, when each value is FFFFh, it is determined that the miniPCI device 60 does not exist. 2) When the miniPCI device 60 exists, the device must be a PCI Bus Power Management Interface Specific.
Check whether or not it complies with the Capability bit of the PCI Status Register on the PCI Config space and Power.
Judge from the existence of Management Register Block. 3) miniPCI device 60 is PCI Bus Power Manageme
Power Management Co., Ltd. on PCI Config Space
Read the value of the ntrol / Status Register (PMCSR). PM
CSR stands for PCI Bus Power Management Interface Speci
It is defined by fication as shown in FIG.

4) At this time, bit08 PME_En (reference numeral 60 in FIG. 2)
Note a). The mini PCI device 60 causes the computer system 10 to wake up from the sleep state.
To do N, PME # must be Asserted. And, as shown in the above table, PME_En
60a must be set to "1". Therefore, by checking the state of this PME_En 60a, B
It is possible to determine whether or not the IOS enables the WAKE-ON-LAN (hereinafter, Wakeup) from the sleep state by the miniPCI device 60. That is, PME_En = 0: Wakeup by the mini PCI device 60 is Di
Set to sable. PME_En = 1: Wakeup by miniPCI device 60 is En
is set to able. Becomes The setting of the PME_En 60a can be set by the user of the computer system 10 via the BIOS. The computer system 10 is connected to a LAN (Local
Area Network) and BIO
S can also be set.

Procedure 3. Control of VccAUX power supply By step 2: Wak by miniPCI device 60
If it is determined that eup is set to Disable, B
IOS is Vaux Off at Sl existing in the gate array 42.
By setting eep register 42d, miniPC
Instructs the I device 60 to turn off the VccAUX power supply. However, the gate array 42 has the Vaux Off at S
Even if the leep register 42d is set, the VccAUX power supply is not turned off immediately, and the operation is waited until the Sleep State signal becomes L.

Procedure 4. Transition of Computer System 10 to Sleep State By the procedure 1, the computer system 10 does not enter the sleep state intended by the OS. After the steps 2 and 3, the BIOS causes the computer system 10 to transition to the sleep state by writing to a predetermined bit of the SuspendEnable register 21 a of the I / O bridge 21.

Next, the operation of the computer system 10 when shifting to the sleep state will be described with reference to the flowchart shown in FIG. When the computer system 10 shifts to the sleep state, the OS operates on the I / O bridge 2
1 is written to the virtual address of the Suspend Enable register 21a (S101). Next, the BIOS
It is determined based on the PME_En 60a whether or not the Wakeup function of the PCI device 60 is set to Enable (S1).
03). S1 when PME_En60a is set to Enable
Go to 05. On the other hand, if it is set to Disable, the process proceeds to S107.

In S105, the BIOS resets the Vaux Off at Sleep register 42d existing in the gate array 42.
Is set to 0, the miniPCI device 60
Of the VccAUX power supply to the power supply. S1
At 07, the BIOS executes the Suspen of the I / O bridge 21.
By writing to a predetermined bit of the d enable register 21a, the computer system 10 is instructed to shift to the sleep state.

When the BIOS suspends the I / O bridge 21
By writing to the Enable register 21a, the SleepState signal changes to L (S109). Slee
When the pState signal changes to L, the VccMAIN_ON changes to L by the AND gate 70. As a result, the DC / DC converter 55 sets VccMAIN to Off (S111). Next, the setting status of the Vaux Off at Sleep register 42d is confirmed (S113). If the value of the Vaux Off at Sleep register 42d is 0, the SleepState signal becomes L
, Both inputs of the OR gate 42c become L, and the output also changes to L (S115).
As a result, VccAUX_ON becomes L through the AND gate 42b.
And the DC / DC converter 55 turns VccAUX off.
(S117). Vaux Off at Sleep register 42d
Is 1, even if the SleepState signal becomes L,
The output of the R gate 42c maintains H, and VccAUX_ON remains H (S119). As a result, VccAUX also remains On (S121).

Next, the operation of the computer system 10 when returning from the sleep state will be described with reference to FIG. Upon detecting the Resume Request from the user, the I / O bridge 21 returns the SleepState signal to H (S20).
1). If the value of Vaux Off at Sleep register 42d is 0
When VccAUX is turned off during the sleep state, the output of the OR gate 42c changes to L, but the output of the OR gate 42c changes to H because the SleepState signal has changed to H. Yes (S20
5). As a result, through the AND gate 42b, VccAUX
_ON becomes H, and the DC / DC converter 55
ccAUX is turned on (S207). If the value of the Vaux Off at Sleep register 42d is 1 and VccAUX is held on during the sleep state, the OR gate 42c is set to H level.
Even if the SleepState signal becomes H, the output does not change. When the SleepState signal becomes H, VccMAIN_ON becomes H by the AND gate 70, and the DC / DC converter 55 sets VccMAIN to On (S209). VccMA
When both IN and VccAUX become On, the return to the normal Power On state is completed, and the BIOS and OS start Resume processing (S211 and S213), and the computer system 10
The return from sleep is completed.

FIG. 9 shows the state of the computer system 10, H / L of SleepState, and On of VccMAIN and VccAUX.
FIG. 3 is a diagram showing / Off in comparison. As shown in FIG. 9, when the computer system 10 shifts to the sleep state,
SleepState changes from H to L. Then, VccMAIN
Turns off, and then the Vaux Off at Sleep register 42
When d is set, VccAUX is turned off. As described above, when transitioning to the sleep state, SleepS
VccMAIN and VccAUX are turned off in synchronization with tate. This means that VccMAIN and VccAUX are synchronized and turned off.
Is meant to be. If Vaux off at Sleep register 42d is not set, VccAUX is O
Maintain n. When returning from the sleep state to the normal Power On state, SleepState changes from L to H. Then, when VccAUX is turned off, first,
VccAUX is turned on first, and then VccMAIN is turned on. Thus, when returning from the sleep state, Sl
VccMAIN and VccAUX are turned on in synchronization with eepState. This means that VccMAIN and VccAUX are synchronized
n. In the present embodiment, as described above, the sleep state, that is, the computer system 1
0 enables On / Off control of VccAUX in synchronization with sleep information about whether or not the sleep state is present. The other power supplies of the computer system 10 are also controlled by this SleepState, and therefore, On / Off of VccAUX.
Is controlled in synchronism with the sleep state, that is, a side effect on the computer system 10, that is, an adverse effect that a predetermined function does not operate is suppressed.

As described above, the computer system 10 according to the present embodiment is
Since the power supply to the miniPCI device 60 can be stopped even when is in the sleep (pause) state,
The power consumption can be reduced. In the present embodiment, the computer system 10 has been described. However, the present invention is not limited to the computer system, and can be applied to electric equipment using a main power supply and an auxiliary power supply. Also, in the present embodiment, the miniPCI device 60 has been described as a means for fulfilling the WAKE-ON-LAN function, but it goes without saying that the present invention can be applied to a device fulfilling the same function as this. . That is, the embodiment described above shows one example of the present invention, and various changes can be made without departing from the gist of the invention.

[0046]

As described above, according to the present invention,
Even if the computer equipped with the miniPCI card or a device corresponding thereto is in a hibernation state, power consumption can be reduced smoothly.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a hardware configuration of a computer system according to an embodiment.

FIG. 2 is a diagram illustrating a configuration of a power supply control circuit according to the present embodiment.

FIG. 3 is a diagram showing the correspondence between each control signal and VccMAIN and VccAUX.

FIG. 4 is a diagram illustrating a situation in which a BIOS presents a fictitious I / O address to an OS.

FIG. 5 is a diagram illustrating an I / O trap.

[Fig. 6] PCI Bus Power Management Interface Speci
It is a figure which shows the definition content of PMCSR by fication.

FIG. 7 is a flowchart showing an operation of the computer system when shifting to a sleep state.

FIG. 8 is a flowchart showing an operation of the computer system when returning from a sleep state.

FIG. 9 is a diagram comparing the state of the computer system with the SleepState signal, and the H / L of VccMAIN and VccAUX.

[Explanation of symbols]

10 ... computer system, 11 ... CPU, 20 ... P
CI (Peripheral Component Interconnect) bus, 21
... I / O bridge, 27 ... miniPCI connector, 41 ...
Embedded controller, 50: power supply circuit, 51: A
C adapter, 55 ... DC / DC converter, 60 ... mini
PCI device

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Takayuki Kato 1623-14 Shimotsuruma, Yamato-shi, Kanagawa Prefecture Inside the Yamato Office of IBM Japan, Ltd. (72) Inventor Kazuo Fujii 1623 Shimotsuruma, Yamato-shi, Kanagawa Prefecture 14 Inside the Yamato Office of IBM Japan, Ltd. (72) Inventor Mitsuhiro Yamazaki 1623, Shimotsuruma, Yamato-shi, Kanagawa Prefecture 1623-14 Shimotsuruma, Yamato City IBM Japan, Ltd. Yamato Office F-term (reference) 5B011 DA02 EA04 LL08 LL10 MA02 MB07

Claims (19)

[Claims] 1. An activation control means for receiving an auxiliary power and controlling the activation of a system according to an external instruction, an auxiliary power generation means for generating the auxiliary power and supplying the auxiliary power to the activation control means, Sleep state output means for outputting sleep information as to whether the system is in a sleep state, and setting information as to whether to supply the auxiliary power to the activation control means when the system is in a sleep state Supply permission / prohibition setting means for holding, based on the pause information from the pause state output means and the setting information retained by the supply permission / prohibition setting means, the auxiliary power generation means to the activation control means A computer device comprising: an auxiliary power supply availability determining unit for determining whether to supply auxiliary power. 2. The auxiliary power supply availability determining means, wherein the sleep state output means outputs sleep information indicating that the system is in a sleep state, and when the system is in a sleep state, the startup control means And determining whether to not supply the auxiliary power to the activation control means when the supply permission / prohibition setting means holds information indicating that the auxiliary power is not supplied. A computer device as described. 3. The computer device, further comprising: main power generation means for generating main power to be supplied to a device mounted in the system; Main power supply availability determination means for determining that the supply of the main power to the device is stopped to the main power generation means when information is output, and a halt indicating that the system is halt When the information indicating that the auxiliary power supply is not supplied to the activation control means when the system is in the inactive state, the information indicating that the auxiliary power supply is not supplied, The computer device according to claim 2, wherein the supply of the auxiliary power from the auxiliary power generation unit is stopped after the supply of the main power from the main power generation unit is stopped. . 4. The auxiliary power supply availability determination means, wherein the sleep state output means outputs sleep information indicating that the system is not in a sleep state, and when the system is in a sleep state, the startup control means 2. The method according to claim 1, wherein when the supply permission / prohibition setting unit holds information indicating that the auxiliary power is not supplied, it is determined that the auxiliary power is supplied to the activation control unit. A computer device according to claim 1. 5. A computer system comprising: a main power generation unit configured to generate a main power supply to be supplied to a device mounted in the system; and a halt indicating that the system is in a halt state from the halt state output unit. Main power supply availability determining means for determining that the supply of the main power to the device is stopped to the main power generation means when the information is output, wherein the system releases the sleep state The sleep state output means outputs the sleep information, and the supply availability setting means holds information indicating that the auxiliary power is not supplied to the activation control means when the system is in the sleep state. The computer according to claim 4, wherein the supply of the main power from the main power generation unit is restarted after the supply of the auxiliary power from the auxiliary power generation unit is restarted. Computer equipment. 6. A main power supply unit for supplying main power, an auxiliary power supply unit for supplying auxiliary power, and a first power consumption unit receiving a main power supplied from the main power supply unit. A second power consuming unit that receives a supply of auxiliary power supplied from the auxiliary power supply unit; and controls a main power supply from the main power supply unit and an auxiliary power supply from the auxiliary power supply unit; Power supply control means for instructing to stop supply of the auxiliary power to the second power consumption means after stopping supply of the main power to the first power consumption means. Computer device characterized by the following. 7. A computer according to claim 1, further comprising a sleep state output unit that outputs sleep information as to whether or not the computer device is in a sleep state, wherein the power control unit is configured to output the sleep information based on the sleep information from the sleep state output unit. The computer device according to claim 6, wherein the main power supply from the main power supply unit and the auxiliary power supply from the auxiliary power supply unit are controlled. 8. An auxiliary power supply stop setting means for setting the supply of the auxiliary power to the second power consuming means to be stopped when the computer device is in a halt state, wherein the power control means comprises: 8. The computer apparatus according to claim 7, wherein the auxiliary power supply from the auxiliary power supply unit is stopped based on sleep information from the sleep state output unit and a setting in the auxiliary power supply stop setting unit. 9. The computer device according to claim 7, wherein the power control unit stops main power supply from the main power supply unit when the computer device is in a sleep state. 10. When the computer device shifts to a hibernation state, the power control unit stops supplying the main power to the first power consuming unit and then supplies the second power consuming unit to the second power consuming unit. 8. The computer apparatus according to claim 7, wherein an instruction to stop the supply of the auxiliary power is given in conjunction with the sleep information from the sleep state output unit. 11. When the computer device returns from a hibernation state, the power supply control unit restarts supply of the auxiliary power supply to the second power consumption unit and then supplies power to the first power consumption unit. 8. The computer apparatus according to claim 7, wherein an instruction to restart the supply of the main power is issued in conjunction with the sleep information from the sleep state output unit. 12. A power supply device for supplying power to a predetermined power consuming means provided in an electric device, wherein the power is supplied to the power consuming means based on an externally supplied power. A power generation unit that generates power; a supply stop setting unit that holds setting information for stopping supply of power to the power consuming unit when the electric device is in a sleep state; and a transition of the electric device to a sleep state. Hibernation state detecting means for detecting whether to perform or returning from the hibernation state, and when the hibernation state detecting means detects whether the electric device shifts to the hibernation state or returns from the hibernation state, the supply stop setting means A power supply control unit for instructing a stop of power supply to the predetermined power consuming means in accordance with the setting information. 13. The power supply device according to claim 12, wherein the predetermined power consuming means performs a function of releasing a sleep state of the electric device by remote control. 14. The power supply control unit, when the function for canceling a hibernation state of the electric device by remote control in the predetermined power consuming means is invalid, the power supply to the predetermined power consuming means. 14. The power supply device according to claim 13, wherein an instruction to stop supply is given. 15. The electric device according to claim 12, wherein the user of the electric device sets that the predetermined power consuming means is effective in releasing the sleep state of the electric device. Power supply. 16. The function for canceling the sleep state of the electric device, wherein the function of the predetermined power consuming means is set based on a use environment of the electric device. A power supply device according to claim 1. 17. A method for supplying power to a computer device having a wake-up function by remote control, the method comprising: setting whether to use the wake-up function when the computer device is in a sleep state. Setting whether or not to stop power supply for performing the wake-up function when the computer device is in a sleep state; and determining whether the computer device is in a sleep state. And when the computer device is set not to use the wake-up function when the computer device is in a sleep state, the computer device is in a sleep state, and the wake-up function is performed when the computer device is in a sleep state. Wake-up when the power supply to execute Power supply method for a computer apparatus characterized in that it comprises a step of stopping the power supply for running ability, the. 18. A step of stopping power supply for performing a wake-up function, comprising: stopping power supply to a device of the computer device that does not need power supply when the computer device is in a sleep state. 18. The method according to claim 17, wherein the synchronization is performed.
A power supply method for a computer device according to claim 1. 19. When the computer device returns from a hibernation state, the power supply for performing a wake-up function is resumed, and the computer device does not need power supply when the computer device is in a hibernation state. 2. The method according to claim 1, wherein the power supply to the device is restarted synchronously.
9. The power supply method for a computer device according to item 8.