JPH03261236A - Reset form scramble code transmission system - Google Patents

Abstract

PURPOSE:To decrease the possibility of entrance to pseudo synchronization even when a transmission signal takes a fixed pattern by preparing two kinds of scramble and de-scramble patterns and varying optionally the scramble and de-scramble patterns. CONSTITUTION:Two kinds of scramble and de-scramble patterns are prepared and a sender side 109 selects any of them according to an output signal of a pattern generating circuit 101. Simultaneously, a signal which of them is to be selected is multiplexed onto an idle bit location of transmission information by a multiplex circuit 103 and sent while being scrambled by the selected scramble pattern. A reception section 116 takes synchronization by a frame synchronization circuit 110 and selection information of a scramble pattern from the transmission section 109 is demultiplexed by using a demultiplex circuit 111 based on the signal and a de-scramble pattern corresponding to the selection information is selected. Then the selection information is descrambled to the demultiplexed demultiplex circuit output. Thus, the possibility of entrance to pseudo synchronization is decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application] The present invention relates to a transmission system using a reset type scrambling code.

[Prior Art] Conventionally, in a transmission system using this type of reset type scrambling code, as shown in FIG.
01, a transmission section 205 composed of a transmission counter circuit 202, a scramble pattern generation circuit 203, and a scramble circuit 204.

There is a transmission system that includes 20 receiving sections each including a frame synchronization circuit 206, a descramble pattern generation circuit 207, and a descramble circuit 208.

[Problems to be Solved by the Invention] In the conventional reset-type scramble code transmission system described above, there is only one type of scrambling pattern. Therefore, when a specific fixed pattern is input as a transmission signal,
There is a possibility that the pattern after scrambling matches the frame pattern, and there is a drawback that once a pseudo-synchronization period is entered, it is impossible to escape from it.

In view of these drawbacks, it is an object of the present invention to provide a reset type scramble code transmission system that can minimize the possibility of entering a pseudo-period.

[Means for Solving the Problems] According to the present invention, there is provided a circuit that generates a predetermined alternating pattern, and a first . means for selectively outputting a second scrambling pattern; a multiplexing circuit that multiplexes selection information indicating which of the second scrambling patterns has been selected into a transmission signal; a frame insertion circuit that inserts the output of the transmission counter circuit into the output of the multiplexing circuit; output and the first output output from the output means. A reset type scrambling code transmission system is obtained which includes a transmitting section including a scrambling circuit which inputs one of the second scrambling patterns and outputs a scrambled signal.

Note that the output means outputs the first output signal based on the output of the transmission counter circuit. The first scrambling pattern generates the second scrambling pattern. a second scramble pattern generation circuit;
Based on the output of the pattern generation circuit, the first. and a selection circuit that selects and outputs one of the second scramble patterns.

Also according to the invention. The transmission signal is the first one. The first scrambling pattern is scrambled based on the second scrambling pattern. 2. A receiving unit that receives a scrambled signal in which selection information representing a type of scrambling pattern is multiplexed, comprising: a frame synchronization circuit; a circuit that separates the selection information from the scrambled signal; Based on the above 1. The first scramble pattern corresponds to the second scramble pattern. means for selectively outputting a second descramble pattern; and means for selectively outputting a second descramble pattern; A reset type scrambling code transmission system is obtained, which has a receiving section including a circuit for descrambling the scrambled signal from which the selection information is separated based on the second descrambling pattern.

The output means outputs the first . The first descramble pattern generates the second descramble pattern. a second descramble pattern generation circuit; and a second descramble pattern generating circuit based on the selection information. The selection circuit selects and outputs one of the second descramble patterns.

According to the present invention, the present invention further includes a transmission counter circuit, a pattern generation circuit that receives an output signal of the transmission counter circuit,
A multiplexing circuit that multiplexes the output signal of the pattern generation circuit and the transmission counter circuit with the transmission signal, and a frame insertion circuit that inserts the output signal of the transmission counter circuit into the output of the multiplexing circuit, Based on the output signal, the first. The first scrambling pattern generates the second scrambling pattern. and a second scramble pattern generation circuit.

a first selecting one output signal of the first scramble pattern generation circuit and the second scramble pattern generation circuit based on the output of the pattern generation circuit;
a selection circuit, and a scrambling circuit that receives the output signals of the frame insertion circuit and the first selection circuit as input; a frame synchronization circuit that receives the signal transmitted from the transmission section; , a demultiplexing circuit that receives the transmission signal and the output signal of the frame synchronization circuit as input and performs demultiplexing; and a first circuit that receives the output signal of the frame synchronization circuit as input. a second descramble pattern generation circuit; a second selection circuit that receives the output signals of the separation circuit; the first descramble pattern generation circuit and the second descramble pattern generation circuit; and the separation circuit. and a circuit for descrambling the output of the output based on the first or second descrambling pattern selected by the second selection circuit. A code transmission method is obtained.

[Operations] In the present invention, two types of scramble patterns and descramble patterns are prepared. On the transmitting side, one is selected according to the output signal of the pattern generation circuit. At the same time, a signal indicating which one has been selected is multiplexed in the empty bit position of the transmission information using a multiplexing circuit, and further scrambled with the selected scrambling pattern and sent out.

In the receiving section, synchronization is achieved by a frame synchronization circuit, and based on the signal, the scrambling pattern selection information from the transmitting section is separated using a separation circuit, and a descrambling pattern corresponding to one selection information is selected.

A descrambling circuit performs descrambling on the output of the separation circuit from which the selection information has been separated using two selected descrambling patterns.

[Embodiment 1] As shown in FIG. 1, the present invention includes a pattern generation circuit 10
1, a transmission counter circuit 102, a multiplex circuit 103,
Frame insertion circuit 104, first and second scrambling pattern generation circuits 105 and 106, and first selection circuit 10
7 and a transmitter 109 including a scramble circuit 108.

Further, as a receiving section, a frame synchronization circuit 110, a first separation circuit 111, a first . It has a descramble pattern generating section including second descramble pattern generating circuits 112 and 113 and a second selecting circuit 114, and a receiving section 116 including a descramble circuit 115.

An example will be shown in which an alternating pattern of 1°, 0'' is sent from the pattern generation circuit 101 in response to a signal from the transmission counter circuit 102.

The first selection circuit 107 is when the pattern is "O".

Selects the output cover turn of the first scramble pattern generation circuit 105, and selects the output cover turn of the second scramble pattern generation circuit 106 when it is 1''.In other words, the output of the pattern generation circuit 101 is This serves as selection information indicating the scrambling pattern.

This selection information is multiplexed onto the transmission signal 117 by the multiplexing circuit 103. A frame insertion circuit 104 inserts the output of the transmission counter circuit 102 for each frame. In this way, the scramble pattern changes alternately on a frame-by-frame basis. Therefore, even if the transmitted signal 117 has a fixed pattern and the scrambled signal happens to match the frame signal in one of the scrambling patterns, the probability that it will match the frame signal consecutively is low because the scrambling patterns are alternately different for each frame. becomes very small.

In the receiving section 116, a frame synchronization circuit 110 performs frame synchronization, and a separation circuit 111 separates selection information in order to determine which scramble pattern the received signal corresponds to. The second selection circuit 114 selects the descramble patterns from the first and second descramble pattern generation circuits 112 and 113 based on the nine-separated selection information. The descrambling circuit 115 descrambles the signal based on the selected descrambling pattern and outputs a signal 118.

[Effects of the Invention] As explained above, the present invention provides two types of scramble and descramble patterns.

By arbitrarily changing the scrambling and descrambling patterns, there is an effect of greatly reducing the occurrence of pseudo synchronization even when the transmission signal has a fixed pattern.

[Brief explanation of drawings]

FIG. 1 shows a block diagram of an embodiment of the present invention. FIG. 2 shows a block diagram of a conventional example. DESCRIPTION OF SYMBOLS 101... Pattern generation circuit, 102... Transmission counter circuit, 103... Multiplex circuit, 104... Frame insertion circuit, 105... First scramble pattern generation circuit, 106... Second Scramble pattern generation circuit, 107... First selection circuit, 108... Scramble circuit, 109... Transmission unit, 110... Frame synchronization circuit, 111... Separation circuit, 112...
First descramble pattern generation circuit, 113...
・Second descramble pattern generation circuit, 114・
. . . second selection circuit, 115 . . . descrambling circuit, 116 . . . receiving section.

Claims (1)

[Scope of Claims] 1) A circuit that generates a predetermined alternating pattern, and means that selectively outputs first and second scramble patterns according to the outputs of the pattern generation circuit and the transmission counter circuit; a multiplexing circuit that multiplexes selection information indicating which of the first and second scrambling patterns is selected into a transmission signal; a frame insertion circuit that inserts the output of the transmission counter circuit into the output of the multiplexing circuit; A reset type scrambling code transmission system comprising a transmitter including a scrambling circuit that receives an output of the frame insertion circuit and one of the first and second scrambling patterns outputted from the output means and outputs a scrambled signal. . 2) In the reset type scrambling code transmission system according to claim 1, the output means generates first and second scrambling patterns based on the output of the transmission counter circuit. A reset type scramble code transmission system comprising a generation circuit and a selection circuit that selects and outputs one of the first and second scramble patterns based on the output of the pattern generation circuit. 3) A receiving unit that scrambles a transmission signal based on first and second scrambling patterns and receives a scrambled signal in which selection information representing the types of the first and second scrambling patterns is multiplexed, a frame synchronization circuit, a circuit for separating the selection information from the scramble signal, and a first scramble pattern corresponding to the first and second scramble patterns based on the separated selection information.
, means for selectively outputting a second descrambling pattern, and a circuit for descrambleing the scramble signal from which the selection information has been separated based on the first and second descrambling patterns selected by the outputting means. A reset type scrambling code transmission system having a receiving section including. 4) In the reset type scrambling code transmission system according to claim 3, the output means includes first and second descramblers that generate the first and second descrambling patterns based on the output of the frame synchronization. a pattern generation circuit, and the first and second patterns based on the selection information.
A reset type scramble code transmission system comprising a selection circuit that selects and outputs one of the descramble patterns. 5) a transmission counter circuit, a pattern generation circuit inputting the output signal of the transmission counter circuit, a multiplexing circuit that multiplexes the output signal of the pattern generation circuit and the transmission counter circuit with the transmission signal, and the multiplexing circuit. a frame insertion circuit for inserting the output signal of the transmission counter circuit into the output of the frame insertion circuit;
First and second scramble pattern generation circuits that generate a second scramble pattern; and one output of the first scramble pattern generation circuit and the second scramble pattern generation circuit based on the output of the pattern generation circuit. a transmitter including a first selection circuit that selects a signal; and a scrambling circuit that receives the output signals of the frame insertion circuit and the first selection circuit as input; the signal transmitted from the transmitter is input; a demultiplexing circuit that receives the transmission signal and the output signal of the frame synchronization circuit as inputs and performs demultiplexing; and first and second circuits that receive the output signal of the frame synchronization circuit as inputs.
a second selection circuit which receives output signals of the separation circuit, the first descramble pattern generation circuit and the second descramble pattern generation circuit; and an output of the separation circuit. and a circuit that performs descrambling based on the first or second descrambling pattern selected by the second selection circuit. method.