JPH0821919B2 - Reset type scramble code transmission system - Google Patents

Description

The present invention relates to a transmission system using a reset scramble code.

[Prior Art] Conventionally, in a transmission system using this type of reset type scramble code, as shown in FIG.
A transmission unit including a 201, a transmission count circuit 202, a scramble pattern generation circuit 203, and a scramble circuit 204.
There is a transmission system including 205, a frame synchronization circuit 206, a descramble pattern generation circuit 207, and a reception unit 209 including a descramble circuit 208.

[Problems to be Solved by the Invention] In the conventional reset type scramble code transmission system described above, there is only one type of scramble pattern. Therefore, when a specific fixed pattern is input as a transmission signal, the scrambled pattern may match the frame pattern, and there is a drawback that the pattern cannot be escaped during the pseudo synchronization period.

In view of such drawbacks, an object of the present invention is to provide a reset scramble code transmission system which can minimize the possibility of entering pseudo synchronization.

[Means for Solving the Problem] According to the present invention, a circuit for generating a predetermined alternating pattern, and a first and a second scramble pattern are selected according to the outputs of the pattern generating circuit and the transmission counter circuit. To output the output of the transmission counter circuit to the output of the multiplex circuit, which multiplexes the transmission signal with selection information indicating which of the first and second scramble patterns is selected. A transmission unit including a frame insertion circuit to be inserted, and a scramble circuit for inputting the output of the frame insertion circuit and one of the first and second scramble patterns output from the output means to output a scramble signal. A reset type scramble code transmission system having the same is obtained.

The output means outputs first and second scramble pattern generation circuits for generating the first and second scramble patterns based on the output of the transmission count circuit, and the output means outputs the pattern generation circuit. And a selection circuit for selecting and outputting one of the first and second scramble patterns.

According to the present invention, further, the reception is performed in which the transmission signal is scrambled based on the first and second scramble patterns and the scramble signal in which the selection information indicating the types of the first and second scramble patterns is multiplexed is received. A frame synchronization circuit, a circuit for separating the selection information from the scramble signal, and first and second scrambling patterns corresponding to the first and second scramble patterns based on the separated selection information. Reception including means for selectively outputting a descramble pattern, and a circuit for descramble the scramble signal in which the selection information is separated based on the first and second descramble patterns selected by the output means A reset type scramble code transmission system having a section is obtained.

The output means generates first and second descrambling pattern generation circuits based on the output of the frame synchronization, and first and second descrambling pattern generation circuits based on the selection information. And a selection circuit for selecting and outputting one of the two descramble patterns.

According to the present invention, further, a transmission counter circuit, a pattern generation circuit that receives an output signal of the transmission counter circuit, and a multiplexing circuit that multiplexes the output signal of the pattern generation circuit and the transmission counter circuit and the transmission signal. And a frame insertion circuit for inserting the output signal of the transmission counter circuit into the output of the multiplexing circuit, and the first and second scrambling patterns for generating the first and second scramble patterns based on the output signal of the transmission counter circuit. A scramble pattern generation circuit, a first selection circuit that selects one of the output signals of the first scramble pattern generation circuit and the second scramble pattern generation circuit based on the output of the pattern generation circuit, and the frame insertion And a scramble circuit that receives the output signal of the first selection circuit as an input; A frame synchronization circuit that receives the signal transmitted from the transmission unit; a separation circuit that performs demultiplexing using the transmission signal and the output signals of the frame synchronization circuit as inputs; and a frame synchronization circuit that receives the output signal of the frame synchronization circuit as an input A first and a second descrambling pattern generation circuit, a second selection circuit which receives the output signals of the separation circuit, the first descrambling pattern generation circuit and the second descrambling pattern generation circuit, and And a receiver configured to perform descrambling based on the first or second descrambling pattern selected by the second selecting circuit with respect to the output of the separating circuit. A scrambling code transmission system is obtained.

[Operation] In the present invention, two types of scramble patterns and descramble patterns are prepared. The transmitting side selects either one according to the output signal of the pattern generation circuit. At the same time, the signal indicating which is selected is multiplexed with the transmission information in the empty bit position by the multiplexing circuit, and further scrambled with the selected scrambling pattern and transmitted.

The receiver synchronizes with the frame synchronization circuit, and based on the signal, the scramble pattern selection information from the transmitter is separated by the separation circuit, and the descramble pattern corresponding to the selection information is selected.

The descrambling circuit uses the selected descrambling pattern to descramble the output of the separation circuit from which the selection information has been separated.

[Embodiment] The present invention is directed to a pattern generation circuit 10 as shown in FIG.
1, a transmission counter circuit 102, a multiplexing circuit 103, a frame insertion circuit 104, a scramble pattern generation section by the first and second scramble pattern generation circuits 105 and 106, and a first selection circuit 107, and a scramble circuit 108. The transmission unit 109 is configured by.

Further, as a receiving section, a frame synchronizing circuit 110, a separating circuit 111, a descramble pattern generating section by the first and second descrambling pattern generating circuits 112 and 113, and a second selecting circuit 114, and a descrambling circuit 115. It has a reception unit 116 configured by.

Pattern generation circuit 1 by the signal from the transmission counter circuit 102
An example when the alternating pattern of "1" and "0" is sent from 01 is shown.

The first selection circuit 107 selects the output pattern of the first scramble pattern generation circuit 105 when the pattern is “0”, and the second scramble pattern generation circuit 106 when the pattern is “1”.
Select the output pattern of. In other words, the output of the pattern generation circuit 101 acts as selection information indicating the first and second scramble patterns. This selection information is multiplexed on the transmission signal 117 by the multiplexing circuit 103. Frame insertion circuit 10
In 4, the output of the transmission counter circuit 102 is inserted for each frame. In this way, the scramble pattern changes alternately on a frame-by-frame basis. Therefore, the transmission signal 117 has a fixed pattern, and even if the scrambled signal in one of the scramble patterns happens to match the frame signal, the scramble pattern is alternately different for each frame, and therefore the probability of consecutive match with the frame signal is high. Becomes very small.

In the receiving unit 116, the frame synchronization circuit 110 establishes frame synchronization, and the separation circuit 111 separates the selection information in order to know which scramble pattern the received signal has. In the second selection circuit 114, the first and second descrambling pattern generation circuits are generated based on the separated selection information.
Select the descramble pattern from 112,113.
The descramble circuit 115 descrambles the signal 118 based on the selected descramble pattern.
Is output.

[Effects of the Invention] As described above, according to the present invention, scrambling and descrambling patterns are prepared, and the scrambling and descrambling patterns are arbitrarily changed so that pseudo synchronization can be entered even when the transmission signal is a fixed pattern. Has the effect of making it extremely low.

[Brief description of drawings]

FIG. 1 shows a block diagram of an embodiment of the present invention. FIG. 2 shows a block diagram of a conventional example. 101 …… Pattern generation circuit, 102 …… Transmission counter circuit, 10
3 …… Multiplex circuit, 104 …… Frame insertion circuit, 105 …… First
Scramble pattern generation circuit, 106 ... Second scramble pattern generation circuit, 107 ... First selection circuit, 108 ...
… Scramble circuit, 109 …… Transmitter, 110 …… Frame synchronization circuit, 111 …… Separation circuit, 112 …… First descramble pattern generation circuit, 113 …… Second descramble pattern generation circuit, 114 …… Second selection circuit, 115 ... descramble circuit, 116 ... reception unit.

Claims (5)

[Claims] 1. A circuit for generating a predetermined alternating pattern, a means for selectively outputting first and second scramble patterns according to outputs of the pattern generating circuit and the transmission counter circuit, and the first circuit. A multiplex circuit for multiplexing selection information indicating which one of the second scramble patterns has been selected into a transmission signal, a frame insertion circuit for inserting the output of the transmission counter circuit into the output of the multiplex circuit, and the frame insertion A reset type scramble code transmission system having a transmitter including a circuit output and one of the first and second scramble patterns output from the output means to output a scramble signal. 2. A reset type scramble code transmission system according to claim 1, wherein said output means generates said first and second scramble patterns based on an output of said transmission counter circuit. Reset type scramble code transmission system comprising: a scramble pattern generating circuit, and a selecting circuit which selects and outputs one of the first and second scramble patterns based on the output of the pattern generating circuit. 3. A receiving unit that scrambles a transmission signal based on first and second scramble patterns and receives a scramble signal in which selection information representing the types of the first and second scramble patterns is multiplexed. A frame synchronization circuit, a circuit for separating the selection information from the scrambled signal, and a first circuit corresponding to the first and second scramble patterns based on the separated selection information.
Means for selectively outputting the first and second descramble patterns, and descramble the scramble signal in which the selection information is separated based on the first and second descramble patterns selected by the output means And a reset type scramble code transmission system having a receiver including a circuit. 4. The reset type scramble code transmission system according to claim 3, wherein the output means generates the first and second descramble patterns based on the output of the frame synchronization. Reset type scramble code transmission system comprising: a descramble pattern generation circuit, and a selection circuit that selects and outputs one of the first and second descramble patterns based on the selection information. 5. A transmission counter circuit, a pattern generation circuit which receives an output signal of the transmission counter circuit as an input, and a multiplexing circuit which multiplexes the output signal of the pattern generation circuit and the transmission counter circuit with a transmission signal. A frame insertion circuit that inserts the output signal of the transmission counter circuit into the output of the multiplexing circuit, and first and second scrambling patterns that generate the first and second scramble patterns based on the output signal of the transmission counter circuit.
A scramble pattern generation circuit, a first selection circuit for selecting one of the output signals of the first scramble pattern generation circuit and the second scramble pattern generation circuit based on the output of the pattern generation circuit, and the frame. A transmission section including an insertion circuit and a scramble circuit that receives the output signal of the first selection circuit; a frame synchronization circuit that receives the signal transmitted from the transmission section; the transmission signal and the frame; A demultiplexing circuit that receives the output signal of the synchronization circuit as an input and performs demultiplexing, a first and second descrambling pattern generation circuit that receives the output signal of the frame synchronization circuit, the demultiplexing circuit and the first descrambling circuit. The output signals of the pattern generation circuit and the second descramble pattern generation circuit are input. And a circuit for descrambling the output of the separation circuit based on the first or second descrambling pattern selected by the second selection circuit. A reset-type scramble code transmission system having: