JPH03260843A - Execution confirming system - Google Patents

Abstract

PURPOSE:To decrease the number of terminals of a comparator and to assure the processing reliability in terms of the real time by outputting the signal that degenerates the whole or a part of the contents of an instruction address register via a signal degenerating means through an external terminal as an execution confirming signal. CONSTITUTION:The execution confirming system of an information processor consists of a microprocessor 31 which is provided with an instruction address register 45, an instruction decoder 44, an instruction execution control part 46, a computing element 48, a general-purpose register 47 which stores the arithmetic results, and an instruction cache 42. Furthermore an external terminal 31a outputting execution confirming signal is provided. Then the contents of the register 45 are outputted through the terminal 31a as an execution confirming signal. Thus it is possible to decrease the number of terminals of a comparator for the reduction in the cost even when a cache is included in a CPU and also to assure the processing reliability in terms of the real time.

Description

DETAILED DESCRIPTION OF THE INVENTION (Summary) Regarding an execution confirmation method for an information processing device that incorporates a plurality of processing devices in order to improve reliability, even if the CPU has a cache, the number of terminals of the comparison circuit The purpose of this design is to reduce the cost by reducing the amount of time required, and also to guarantee the real-time reliability of processing. In a microprocessor having a general-purpose register for storing calculation results and an instruction cache, an external terminal for outputting an execution confirmation signal is provided, and the contents of the instruction address register are outputted from the external terminal as an execution confirmation signal. , or in the microprocessor, the external terminal is provided and a signal degenerating means is provided, and a signal obtained by degenerating all or part of the contents of the instruction address register by the signal degenerating means is transmitted via the external terminal as an execution confirmation signal. In a microprocessor having an instruction address register, an instruction decoder, an execution control unit for controlling instruction execution, an arithmetic unit, a general-purpose register for storing operation results, an instruction cache, and an operand cache, An external terminal for outputting an execution confirmation signal is provided, and a flag, which is one of the calculation results, is outputted from the arithmetic unit to the outside of the processor as an execution confirmation signal via the external terminal, or an instruction address register, an instruction decoder, an execution control unit that controls instruction execution, an arithmetic unit,
In a microprocessor having a general-purpose register for storing calculation results, an instruction cache, and an operand cache, an external terminal for outputting an execution confirmation signal is provided, and a branch instruction is transmitted from the execution control unit to the outside of the processor via the external terminal. The configuration is such that a branch instruction signal indicating whether or not the program sequence has changed due to the execution of the program is output as an execution confirmation signal.

(Industrial Application Field) The present invention relates to an execution confirmation method for an information processing device incorporating a plurality of processing devices in order to improve reliability.

(Prior art) Execution confirmation methods conventionally implemented in information processing devices are as follows:
As shown in Fig. 5, two CPUs (central processing units) 1 and 2 each consisting of a microprocessor, and both
Clock 3 for synchronizing PUI, 2 and both C
It is equipped with a comparison circuit 4 having a data bypass function that inputs control signals, addresses, data, etc. from the PUI 2 and checks whether the processing of both CPUs 2 matches. Data is input via bus 5. When inputting data to the CPU 2, the data is directly transmitted to the CPU 2 side through the comparison circuit 4, but without using the comparison function, using the data bypass function.

As shown in FIG. 6, the CPU 1 or 2 has an external interface 11 that transmits control signals, addresses, data, etc. to the system bus 5 and the comparator circuit 4, and stores instructions input via the external interface 11. and an operand cache 13 that stores operands input via the external interface 11.
an instruction decoder 14 that decodes instructions read from the instruction cache 12; an instruction address register 15 that stores the output from the instruction decoder 14; an execution control unit 16 that executes the instructions decoded by the instruction decoder 14; It includes an arithmetic unit 18 that executes arithmetic operations while inputting and outputting data between the operand cache 13 and the general-purpose register 17 under the control of the control unit 16.

The execution confirmation method in this information processing device is to synchronize the CPU 1 and CPU 2 with the output of the clock 3 to execute the same process, and compare the output results of the execution at the same time using the comparator circuit 4 to determine the re-output result. It checks whether they match or not, and confirms whether the processing is being performed correctly.

[Problem to be solved by the invention]

In the conventional execution confirmation method described above, in order to guarantee the reliability of processing by confirming that the two CPUs 1.2 produce the same processing result, the external bus (
By connecting only the signal line (constituting the signal line) to the comparator circuit 4,
The operations on the bus are compared to see if they match.

Therefore, since the number of signal lines of the address bus and data bus is large, the number of terminals of the comparator circuit 4 is increased, which increases the cost. In addition, in a device where the CPUI 2 is equipped with an instruction cache 12 or an operand cache 13,
Store processing is affected by the time lag for instruction access or operand access to go outside, and the comparator circuit 4 cannot compare the contents of the process in real time, especially when the operand cache is write-back or copy pack. Even the data can take quite a while to come out, slowing down the comparison cycle.

Therefore, due to these configuration factors, even if a highly reliable information processing device is configured with a dual CPU configuration, the system cost is high and the real-time reliability of processing cannot be guaranteed. The problem was that it couldn't be done.

The present invention was developed in view of the above-mentioned problems, and the technical problem set to solve the problem is to reduce the number of terminals of the comparison circuit even when caching is provided in the CPU. The purpose of the present invention is to provide an execution confirmation method that can reduce costs and guarantee real-time reliability of processing.

(Means for Solving the Problems) As a specific means for solving the above problems, the present invention provides, in configuring an execution confirmation method for an information processing device,
As shown in the embodiment diagram of FIG. 1, an instruction address register 45, an instruction decoder 44, an execution control unit 46 that controls instruction execution, an arithmetic unit 48, a general-purpose register 47 that stores operation results, and an instruction The microprocessor 31 having a cache 42 is provided with an external terminal 31a for outputting an execution confirmation signal, and the contents of the instruction address register are output from the external terminal 31a as the execution confirmation signal.

As shown in the embodiment diagram of FIG. 1 or FIG. 2, a signal reduction means 49b or 52 is provided, and all or part of the contents of the instruction address register are It is desirable to output a signal obtained by degenerating the above as an execution confirmation signal through the external terminal 31a.

Further, as shown in the embodiment diagram of FIG. 3, an instruction address register 45, an instruction decoder 44, an execution control unit 46 that controls instruction execution, an arithmetic unit 48, and a general-purpose register 47 that stores operation results. , an instruction cache 42, and an operand cache 43.
In this case, an external terminal 31a for outputting an execution confirmation signal may be provided, and a flag, which is one of the calculation results, may be output from the arithmetic unit 48 to the outside of the processor as the execution confirmation signal via the external terminal 31a. good.

Furthermore, as shown in FIG. 4, an instruction address register 45, an instruction decoder 44, an execution control unit 46 that controls instruction execution, an arithmetic unit 48, a general-purpose register 47 that stores operation results, and an instruction cache 42 and an operand cache 43, an external terminal 31a for outputting an execution confirmation signal is provided, and a program is transmitted from the execution control unit 46 to the outside of the processor via the external terminal 31a by executing a branch instruction. A branch instruction signal indicating whether the sequence has changed may be output as an execution confirmation signal.

[Effect]

With the above configuration, if any of the processes of each microprocessor at the same time has made an error, the present invention directly compares and examines the signals output from each of the external terminals 31a and 32a using a comparison circuit. It detects that there is an error in the processing, and if it is an error, it outputs an error detection signal, and each microprocessor 31, 32 outputs an error detection signal to its external terminal 3.
Error detection signals are input from 1a and 32a to stop the execution of each microprocessor 31 and 32, respectively, and along with the stoppage, the transmission of data, etc. is interrupted. This makes it possible to directly confirm in real time whether each of the microprocessors 31 and 32 is performing processing accurately, thereby ensuring high reliability. Also,
Each microprocessor 31 is
．． Since the processing at 32 can be confirmed, the number of connection terminals is reduced, contributing to cost reduction.

(Example) As an example of the present invention, the following describes a case where an instruction address or its degenerate signal, a flag that is one of the calculation results, or a branch instruction signal is used as a signal output during execution of each microprocessor. This will be illustrated and explained.

A first embodiment is shown in FIG. Here, 31° and 32 are CPUs each consisting of a single-chip microprocessor.
and one is for executing the necessary processing,
The other one is used to execute the same process to confirm the process.

The CPUs 31 and 32 are respectively provided with external terminals 31a and 32a for directly outputting data being processed without going through an external interface 41.
The processing of one device 31 or 32 and the processing of the other device 3 are performed by the data generated at the same time retrieved via 2a.
It is possible to confirm that the processes of 2 or 31 match.

The internal configuration of the CPU 31 (or 32) includes an external interface 41 for inputting control signals, addresses, data, etc. from the system bus 37, an instruction cache 42 for storing instructions input via the external interface 41, and an external interface. 41, an instruction decoder 44 that decodes instructions read from the instruction cache 42, an instruction address register 45 that stores the output from the instruction decoder 44, and an instruction address register 45 that stores the output from the instruction decoder 44. an execution control unit 46 that executes instructions decoded by the decoder 44; an arithmetic unit 48 that executes operations while inputting and outputting data between the operand cache 43 and the general-purpose register 47 under the control of the execution control unit 46; The data generated during processing is directly transferred to a comparison device 34 for comparison.
It is provided with an external terminal 31a (or 32a) for inputting an error detection signal from the comparison device 34 side, which is output when the comparison result does not match.

The output side of the instruction address register 45 and the external terminal 31a (
or 32a) via an internal bus 49a so that all instruction addresses can be output from the external terminal 31a (or 32a), or connect an exclusive OR circuit 49b as a signal reduction means to the internal bus 49a. By outputting the exclusive OR of data of adjacent bits, it is possible to output data with a reduced number of bits of output data (degenerate data).

The execution control section 46 and the external terminal 31a (or 32a) are connected by a signal line 49c so that the error detection signal inputted by the execution control section 46 can be received as a halt signal, thereby interrupting subsequent processing. be able to do so.

When the CPUs 31 and 32 configured in this manner are checked for consistency, the following procedure is performed.

When the arithmetic unit 48 proceeds with processing based on a command from the execution control unit 46, each CPU 31, 32 receives the contents from the instruction address register 45 at the same time via the internal bus 49a and the external terminal 31a or 32a. to a comparison device (not shown).

The comparator does not output a signal when the contents input from both CPUs 31 and 32 match, and outputs a 1-bit error detection signal to each CPU 31 and 32 when they do not match.
Send to.

Each CPU 31.32 sends the error detection signal to external terminal 3.
Execution control unit 4 via 1a, 32a and signal line 49c
6, and the execution control unit 46 controls the arithmetic unit 48.
stop processing.

Further, when an error detection signal is input, an input/output system interrupting mechanism (not shown) is activated to interrupt input/output of control signals, addresses, data, etc.

In this way, in the first embodiment, each external terminal 31a, 32a
The contents of the instruction address register 45 can be directly retrieved through the CPU 31, and the output data can be compared by the comparator 34.
The correctness of the processing at the same time in step 2 can be confirmed in real time by an external device (comparison device).

Furthermore, by inputting the output from the instruction address register 45 or its degenerate data to an external device, the number of terminals of the external device can be reduced, and the CP
The comparison device outside U can be made into an inexpensive device, and the LS
It is easy to integrate into an integrated circuit, simplify the packaging for incorporation, facilitate printed wiring, reduce overhead costs, and lower the price of highly reliable information processing equipment.

As another aspect of the first embodiment (CPU 31 or 32), as shown in FIG. 2, it is configured to transmit a part of the lower digits of the instruction address.

Lower digit output side of instruction address register 45 and external terminal 3
1a (or 32a) via an internal bus 51,
A part of the lower digits of the instruction address can be outputted from the external terminal 31a (or 32a), or an exclusive OR circuit 52 as a signal reduction means can be connected to the internal bus 51.
The other parts are configured in the same manner as the CPU 31 (or 32).

Generally, program execution proceeds sequentially, so
Comparison of only the lower digits is sufficiently practical, and thereby the number of terminals can be further reduced and internal operations can be easily confirmed by an external device.

As a second embodiment, as shown in FIG.
A signal line 53 for outputting a flag, which is one of the calculation results in , is connected to the external terminal 31a (or 32a), and the other parts are configured in the same manner as the CPU 31 (or 32).

This makes it possible to output various flags during the calculation, allowing an external device to check the internal execution sequence.

As a third embodiment, as shown in FIG. 4, a signal line 54 for outputting a branch signal from the execution control unit 46 is
a (or 32a), and the other parts are configured similarly to the configuration of the CPU 31 (or 32).

As a result, each time the execution control section 46 changes the program sequence to execute a branch instruction, a branch signal is output from the execution control section 46, and the internal operation can be confirmed by an external device.

With these various embodiments of the CPU 31 (or 32), it is possible to check the correctness of processing in real time for both CPUs 31 and 32, and the comparison device used as the checking device can reduce the number of terminals. As a result, manufacturing costs can be reduced.

(Effects of the Invention) As described above, in the present invention, each microprocessor 31.
32 are each provided with external terminals 31a and 32a for directly outputting the data being processed without going through an external interface, and an instruction address or its degenerate signal, flag, branch instruction signal, etc. is provided via the external terminals 31a and 32a. By outputting any of the following, an external device can easily check the correctness of the processing, and if an error is found in the processing, each microprocessor 31, 32 receives the error detection signal. By making it possible to stop the processing in a timely manner and interrupt the transmission of input/output systems such as control signals, addresses, and data,
For each microprocessor 31.32,
It is possible to directly check in real time that processing is being performed accurately, ensuring high reliability.

Further, since the processing in each microprocessor 31, 32 can be confirmed using the minimum necessary data, the number of connection terminals can be minimized, and overhead costs in designing and manufacturing the information processing device can be reduced.

[Brief explanation of drawings]

FIG. 1 is a configuration explanatory diagram of a first embodiment of the present invention; FIG. 2 is a configuration explanatory diagram showing another aspect of the first embodiment; FIG. 3 is a configuration explanatory diagram of a second embodiment; FIG. 4 is an explanatory diagram of the configuration of the third embodiment; FIG. 5 is a configuration diagram showing an execution confirmation method in a conventional information processing device; FIG. 6 is an explanatory diagram of the configuration of a conventional microprocessor. 31.32...Microprocessor (CPU) 31a
, 32a... External terminal 42... Instruction cache 43... Operand cache 44... Instruction decoder 45... Instruction address register 46... Execution control unit 47... General purpose register 48... Operation circuits 49a, 51...internal buses 49b, 52...signal degeneration means (exclusive OR circuit) 4
9c, 53, 54...Signal line katsu 1 example shows the list of %71tll for h1
lJanuary map Figure 2 Matagawa's 4811Fi"q Buried 11 dou Slows Takecocoon Kirin Takehiki 0 mouth IB5 Figure system!+:S

Claims (1)

[Claims] (1) An instruction address register (45), an instruction decoder (44), an execution control unit (46) that controls instruction execution, an arithmetic unit (48), and a general-purpose unit that stores operation results. A microprocessor (31) having a register (47) and an instruction cache (42) is provided with an external terminal (31a) that outputs an execution confirmation signal, and an instruction address register (45) is provided from the external terminal (31a).
) is output as an execution confirmation signal. (2) A signal degeneration means (49b or 52) is provided, and a signal obtained by degenerating all or part of the contents of the instruction address register (45) by the signal degeneration means (49b or 52) is used as an execution confirmation signal. The external terminal (31a)
2. The execution confirmation method according to claim 1, wherein the execution confirmation method is outputted via. (3) an instruction address register (45), an instruction decoder (44), an execution control unit (46) that controls instruction execution, an arithmetic unit (48), and a general-purpose register (47) that stores operation results; Microprocessor (31) having an instruction cache (42) and an operand cache (43)
, an external terminal (31a) outputs an execution confirmation signal.
), and outputs a flag, which is one of the calculation results, from the arithmetic unit (48) to the outside of the processor as an execution confirmation signal via the external terminal (31a). (4) an instruction address register (45), an instruction decoder (44), an execution control unit (46) that controls instruction execution, an arithmetic unit (48), and a general-purpose register (47) that stores operation results; Microprocessor (31) having an instruction cache (42) and an operand cache (43)
, an external terminal (31a) outputs an execution confirmation signal.
), and the execution control unit (46) is connected to the execution control unit (46) via the external terminal (31a).
An execution confirmation method characterized in that a branch instruction signal indicating whether or not a program sequence has changed due to execution of a branch instruction is outputted from the processor to the outside as an execution confirmation signal.