JPH03252129A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To detect the end point of etching easily and accurately in the etching of the whole surface at the time of the formation of a sidewall by contributing one part or the whole region of a region except a chip region, from which a specific first thin-film is removed, to the detection of the end point of etching at the time of the etching of the whole surface of a specific second thin-film. CONSTITUTION:In the manufacture of a semiconductor device having a process, in which a first thin-film 10 is formed onto a semiconductor substrate 1 and the first thin-film 10 is patterned and a first thin-film pattern 10P having a stepped section to the periphery is formed, and a process, in which a second thin-film 12 is formed onto the whole surface of the substrate 1 and a sidewall 12S is shaped onto the side face of the first thin-film pattern 10P through the etching of the whole surface of the second thin-film 12, a process, in which the first thin-film 10 on one part or the whole region of a chip outside region 7 is removed at the same time as or apart from a process, in which the first thin-film 10 on a chip region 6 is patterned, is provided, and one part or the whole region of the chip outside region 7, from which the first thin-film 10 is removed, is made to contribute to the detection of the end point of etching at the time of the etching of the whole surface of the second thin-film 12.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Field of Application Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Action Embodiment 1 Process sectional view of the embodiment (Fig. 1) Implementation Schematic plan view of a semiconductor substrate in an example (FIG. 2) Process cross-sectional view in another embodiment (FIG. 3) Effects of the invention [Summary] A method for manufacturing a semiconductor device, particularly a method for forming a sidewall on the side surface of a step. Regarding the improvement, the purpose is to provide a method for manufacturing a semiconductor device in which it is possible to easily and accurately detect the end point of etching in the entire surface etching during sidewall formation, by forming a first thin film on a semiconductor substrate (1),
a step of patterning the first thin film to form a first thin film pattern (10P) having a step with respect to the periphery;
Next, a second thin film (12) is formed on the entire surface of the substrate (1), and the entire surface of the second thin film (12) is etched to form a second thin film pattern (10P) on the side surface of the first thin film pattern (10P). A method for manufacturing a semiconductor device comprising the step of forming a side wall (12S) made of a thin film, and in which the end point of v-ching on the entire surface of the second thin film (12) is determined by an end point detection means. A step of buttering the first thin film (10) on the chip region on the surface of the substrate (1), and a part of the region outside the chip region, either simultaneously or separately from the step of buttering the first thin film (10). or the step of removing the first thin film (10) over the entire area, and removing part or the entire area of the area outside the chip area from which the first thin film (10) has been removed, and removing the second thin film (10) from the first thin film (10). 12) The method includes the step of contributing to the detection of the etching end point during the entire surface etching.

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device, and particularly to an improvement in a method for forming a sidewall on the side surface of a step.

In recent years, with the demand for higher integration of semiconductor devices, self-line technology that enables the formation of various functional parts at high density, and the mitigation of steep steps to prevent wiring breaks and short circuits between wiring. A sidewall formation technology that applies a full-face etching method has been provided as a means for etching, but over-etching during sidewall formation leads to performance deterioration of the semiconductor device, so it is important to accurately detect the etching end point during the above-mentioned full-face etching. In addition, a method for manufacturing a semiconductor device is desired.

[Conventional technology]

Conventionally, for example, a U-shaped separation groove including a sidewall forming process has been formed by a method described below with reference to FIG.

Refer to FIG. 4(a). That is, a silicon nitride (SiJn) film pattern 5 having oxidation resistance is formed on a semiconductor substrate 51 via an underlying oxide film 52.
3A, 53B, etc. are formed, selective oxidation is performed using these 5i3N4Ill patterns 53A, 53B, etc. as a mask to form a field oxide film 54, and then, by ordinary photolithography, for example, the field oxide film 54 is penetrated to reach the inside of the semiconductor substrate 51. A U-shaped groove 55 is formed. In the figure, 56 indicates a chip area, and 57 indicates an area outside the chip area (peripheral area of the substrate), that is, an area outside the chip.

FIG. 5 is a plan view schematically showing the upper surface of the semiconductor substrate 51, in which 56 is a chip region and 57 is an off-chip region.

Refer to FIG. 4(b) Next, a SiO□ film 5 formed by thermal oxidation is formed on the inner surface of the U-shaped groove 55.
A first polysilicon (Si) layer is formed on the entire surface of the substrate, including the inside of the U-shaped groove 55, by a CVO method to a thickness that completely fills the inside of the U-shaped groove 55, for example. Then, etch back is performed to form a poly-Si buried layer 59 in the U-shaped groove 55, and then a second poly-Si buried layer 59 is formed on the entire surface of the substrate.
An i-layer 60 is formed.

Referring to FIG. 4(C), a positive resist film is then formed on the second poly-Si layer 60, the chip region 56 is exposed to light by step-and-repeat method, and the resist film is developed. A resist pattern 61P is formed therein to selectively cover the upper part of the poly-Si buried layer 59. Note that in the conventional method, the off-chip area 57 which is not necessary for pattern formation is not exposed due to restrictions on the exposure equipment and shortening the exposure time, so the resist film 61 remains in this off-chip area 57. do.

Referring to FIG. 4(c), the resist pattern 61P and the resist film 61
After battering the second poly-Si layer 60 using as a mask, the resist pattern 61P and the resist film 61 are removed. Here, the poly-Si buried layer 5 in the chip region 56
A second poly-Si layer pattern 60P is formed above the 0-shaped groove 55 filled with 9, and the second poly-Si layer 60 remains as it is on the off-chip region 57.

Referring to FIG. 4(e), a third poly-Si layer 62 is then formed on the entire surface of the substrate, and the entire surface is etched to form a third poly-Si layer 62 on the steeply stepped side surface of the second poly-Si layer pattern 60P. Poly-Si layer 6
A side wall 62S consisting of 2 is formed. At this time, in this conventional method, as described above, the second polySt layer 60 of the same type as the third polySi layer 62 remains in the off-chip region 57 which occupies a large area and plays a major role in detecting the etching end point. Since the appearance of this region has a structure in which the thickness of the poly-Si layer above is increased, this region is affected by reaction products, changes in the plasma light intensity of the reaction gas, changes in the amount of electroluminescence light, etc. It is not possible to contribute to the end point detection of the entire surface etching of the third poly-Si layer 62, which is detected by a normal end point detection means, and as a result, the end point detection becomes inaccurate, resulting in extreme overetching, and At the same time as the second poly-Si layer pattern 60P becomes extremely thin, the sidewall 62S made of the third poly-Si layer 62 also wears out as indicated by the dotted line 62SS.

Refer to FIG. 4(f). Therefore, in a later step, the second poly-Si layer pattern 6
The SiO□ insulating film 63 formed by thermally oxidizing the 0P and poly-Si side walls/L<62SS becomes thinner, and the wiring (not shown) and the U-shaped groove formed on the upper part of the 0-shaped groove 55 become thinner. A problem arises in that the insulation with respect to the poly-Si buried layer 59 in the insulating film 62 is deteriorated, and the step formed on the side surface of the insulating film 63 becomes steep due to the wear of the side wall 62SS. Therefore, in the above conventional method, the above-mentioned 2. There have been problems in that step breaks due to steep steps are likely to occur, and residues of the wiring material remain in the step portions during wiring formation, making it easy to cause short circuits between the wires.

[Problem to be solved by the invention]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device in which the end point of etching can be easily and accurately detected during full-surface etching during sidewall formation.

[Means to solve the problem]

The above problem includes a step of forming a first thin film on a semiconductor substrate (1) and patterning the first thin film to form a first thin film pattern (10P) having a step with respect to the surroundings; Next, a second thin film (12) is formed on the entire surface of the substrate (1), and the entire surface of the second thin film (12) is etched to form a second thin film pattern (10P) on the side surface of the first thin film pattern (10P). In a method for manufacturing a semiconductor device, which includes a step of forming a sidewall (12S) made of a thin film, and in which the end point of the entire surface etching of the second thin film (12) is determined by end point detection means, the semiconductor substrate (12S) ) A step of buttering the first thin film (10) on the chip region on the surface, and a step of buttering the first thin film (10) on a part or the entire region outside the chip region, either simultaneously or separately from the step of buttering the first thin film (10). of the first thin film (10), and a part or the entire area of the removed area of the first thin film (10) outside the chip area is removed from the second thin film (12). This problem is solved by the method of manufacturing a semiconductor device according to the present invention, which includes a step of contributing to the detection of the end point of etching during full-surface etching.

[For production]

That is, in the method of the present invention, a second thin film is formed on the entire surface of a semiconductor substrate having a first thin film pattern, and the second thin film is etched over the entire surface to form a second thin film on the side surface of the first thin film pattern. In order to easily and accurately detect the end point of the above-mentioned entire surface etching when forming a sidewall consisting of a thin film, when patterning the first thin film, at the same time, an area outside the chip where no chip is formed in the peripheral area of the semiconductor substrate is to be etched. by removing the first thin film of the region (possibly by
A layer of a different material is brought into direct contact with the lower part of the second thin film on this region over a wide area.

As a result, the end point of the entire surface etching of the second thin film is detected by changes in various detected values due to the exposure of the foreign material layer over a wide area, so that the end point can be easily and accurately detected.

〔Example〕

The present invention will be specifically explained below with reference to illustrated embodiments.

1(a) to 1) are process cross-sectional views of an embodiment of the method of the present invention for forming a U-shaped groove isolation region, FIG. 2 is a schematic plan view of a semiconductor substrate in the same embodiment, and FIG. Figures (a) to (e)
) is a process sectional view of another embodiment of the method of the present invention for manufacturing LDD-MO3FET.

Refer to FIG. 1(a) When forming a U-shaped groove isolation region using the method of the present invention, first, as in the conventional method, an element formation region in a chip region 6 on one surface of a semiconductor substrate where a semiconductor chip is formed. A
D and the off-chip area 7 on the periphery of the substrate where no chip is formed are individually covered with an underlying oxide film 2 interposed therebetween.
iJ, film patterns 3A and 3B are formed, and these 5isN
Selective oxidation (10
GO3) selectively deposits a thickness of 0.6μ on the chip area 6.
A field oxide film 4 having a thickness of approximately 3 μm is formed, and then a U film having a depth of approximately 3 μm, for example, whose bottom portion reaches inside the semiconductor substrate 1, is formed on the surface of the field oxide film 4 by ordinary photolithography.
A trench 5 is formed, for example, by thermal oxidation.
The inner surface of the groove 5 has a thickness of approximately 0.1 μm for isolation between elements.
A Sing film 8 is formed, and then a film with a thickness of, for example, 1.5 cm is formed by CVD on the entire surface of the substrate including the inside of the trench 5.
A first poly-Si layer with a thickness of approximately μm is formed, and an etch-back process is performed using, for example, a dry etching method using (CF4+Oz) gas as an etching gas to form the first poly-Si layer in the U-shaped groove 5. A poly-Si buried layer 9 consisting of the following is formed as a residual layer.

In this case, if the thickness of the first poly-Si layer is thin<the first poly-Si layer buried in the trench (poly-Si buried layer 9)
Although a groove is formed in the center, this is not a particular problem.

FIG. 2 is a plan view schematically showing the upper surface of the semiconductor substrate 1, in which 6 indicates a chip region and 7 indicates an off-chip region.

Refer to FIG. 1(b).Next, a film with a thickness of 0.2 cm was coated on the entire surface of the substrate by CVD method.
A second poly-Si layer 10 with a thickness of approximately μm is formed, and then, for example, a positive resist film 11 is coated on the second poly-Si layer 10, and exposure is performed, for example, by step-and-repeat, to form the trenches in the chip region 6. The first exposure is performed on an area other than the area covering the upper part of 5 in a predetermined area (
lla I is the first exposure area), and then, using another mask, a second exposure (llaz is the second exposure area) is performed on, for example, the entire off-chip area 7 excluding the chip area 6. The region 7 may be exposed by a step-and-repeat method.

Referring to FIG. 1(C), development is then performed. Through this development, a resist pattern IIP covering the upper region of the trench 5 with a predetermined width is formed in the upper region of the trench 5 in the unexposed chip region 6, and is exposed. Resist film 11 on other parts of chip region 6 and off-chip region 7 are all dissolved and removed.

Refer to FIG. 1(d). Next, using the resist pattern LIP as a mask, the second poly-Si layer 10 is etched using, for example, a chlorine (CI)-based etching gas or by active ion etching (RIE) processing, and the trench 5 is etched. A second poly-Si layer pattern 10P is formed on top of the poly-Si layer pattern 10P.

At this time, the second poly-Si layer 10 is removed from the off-chip region 7, and the 5isN4 film pattern 3B underneath it is exposed.

After peeling and removing the resist pattern LIP, see FIG.
A third poly-Si layer (12) of about 5 μm is formed. Next, for example, R using CI-based etching gas.
By IE processing, the entire surface of the third poly-Si layer is etched until the end point is detected by an end point detection means such as an emission spectroscopy, and the second poly 51 layer pattern 1 is etched.
A poly-Si sidewall 125 made of a third poly-Si layer is left on the side surface of the 0P.

Note that the above-mentioned emission spectrometry is a method of detecting the end point by a sudden change in the intensity of the emission spectrum having a specific wavelength when the end point is reached, but in the method of this example,
Under the third poly-Si layer 12 on the off-chip region 7, which has a large area, there is a film (3B) of Si3N, which is a material different from Si, in direct contact with the third poly-Si layer 12. At the time when the etching of the Si layer 12 is completed, the change in the emission intensity of the emission spectrum having a specific wavelength of the etching gas or the emission spectrum having a specific wavelength due to the reaction product becomes very large, and the etching end point detection sensitivity is lower than that of the conventional one. This is a significant improvement compared to . Therefore, extreme overetching does not occur during the etching of the entire surface, the thickness of the second poly 51 layer pattern 10P is ensured, and the smoothness of the poly Si side wall 125 is also maintained.

FIG. 1(f) Thereafter, the second polySt layer pattern 10P is applied in the same manner as before.
and thermally oxidize the poly-Si sidewall 125 on the side thereof to form a poly-Si buried layer covering SiO2 film 13,
A U-shaped groove isolation region according to the method of the present invention is completed.

Note that, as described above, according to the method of the present invention, the second poly 5
Since the film thickness of the one-layer pattern 10P and the smoothness of the poly-Si sidewall 12S on the side surface thereof are ensured, the buried layer covering Sing film 13 formed by oxidizing these has a predetermined thickness. In addition, since it has a gentle side surface, the wiring layer (not shown) formed thereon and the polyS
High insulation with the i-buried layer 9 is ensured, and breaks in the wiring, short circuits between the wirings due to wiring layer residue, etc. are prevented.

In the method of the present invention, when forming a side wall made of an insulating film on the side surface of an electrode, for example, a MOSFET with an LDD structure
It also applies when manufacturing.

The method will be described below with reference to examples in Figs. 3(a) to (e).
).

Refer to FIG. 3(a) When manufacturing an LDD structure MOSFET using the method of the present invention, for example, a p-type Si substrate 21
A field oxide film 23 having a thickness of about 0.6 μm and having a channel stopper (not shown) below and defining an element formation region 22 is formed on the chip region 6 by a selective oxidation method. At this time, a field oxide film 2 is formed on the off-chip area 7.
Does not form 3.

(For the arrangement of the chip area 6 and the off-chip area, please refer to the second section.
Refer to the schematic plan view shown in the figure) Refer to FIG. 3(b) Next, a gate oxide film 24 with a thickness of about 0.02 μm is formed by thermal oxidation on the element formation region 22 and the exposed off-chip region 7 of the substrate. Then, a poly-Si layer 25 with a thickness of about 0.4 μm is formed on this substrate by the CVD method, and this poly-Si layer 25 is
On the t-layer 25, a carbon layer with a thickness of about 0.2 μm is deposited using the CVD method.
VD-5t (h film 26 is formed, then this CVD-5
A positive resist pattern 27P for a gate electrode patterning mask is formed on the tO2 film 26. At this time, the resist layer is not left on, for example, the entire area of the off-chip region 7. Here, the same method as in the previous embodiment is used to expose the resist in the off-chip area 7.

Refer to FIG. 3(C) Next, apply CHF to the above resist pattern 27P mask.
, etc. by RIB processing using etching gas.
The VD-5in film 26 is buttered and then CI
Poly-Si is etched by RIE treatment using etching gas.
The layer 25 is patterned to form a poly-Si gate electrode 25G having a CVD-5, jot film 26 thereon. At this time, the CVD-5iO□ film 26 and poly-Si layer 25 on the off-chip area 7 that is not covered with the resist are etched away, and the St substrate 21 surface with the thin gate oxide film 24 on the upper surface is exposed in this area. put out

Next, after removing the resist pattern 27P, using the gate electrode 25G as a mask, n-type impurity ions are selectively implanted into the element forming region 22 at a low concentration. (127 is a low concentration n-type impurity implantation region) Refer to FIG.
A second CCVD-5in film with a thickness of about 5 μm is formed, and then this second CVD-5ift film and gate oxide film 24 are formed.
The entire surface is etched by RIE processing using, for example, CHF until the etching end point is detected by, for example, the end point detection means based on the emission spectrum intensity. In this embodiment, the etched SiO
Since the VD-5i (h film and the Si substrate 21, which is a different material) exist in direct contact with Sing under the gate oxide film 24, the detection of the end point is performed with high sensitivity and accuracy, and is extremely To prevent overetching of the gate electrode 25G, a SiO sidewall 28 is formed on the side surface of the gate electrode 25G, which is made of a second CVD-5iO2 film having a predetermined thickness and has a smooth side surface. The thickness of the CVD-5i01 film 26 on the gate electrode 25G is also ensured.

After referring to FIG. 3(e), using the gate electrode 25G having the 5iO1 sidewall 28 as a mask, n-type impurity ions are implanted at a high concentration into the element formation region 22 by a conventional method.
Heat treatment is performed to activate the high concentration impurity implantation region and the previously formed low concentration n-type impurity implantation region 127, thereby forming an n-type source region 27S and an n-type drain region 27D.
, n'' type source region 29S, n'' type drain region 29
Although not shown in the drawings, an interlayer insulating film is formed on this substrate, and contacts and windows that expose the n-type source region 29S and n-type drain region 29D are formed in this glabellar insulating film, and these contact windows A source wiring, a drain wiring, etc. extending from above onto the interlayer insulating film are formed, and an LDD structure MOSFET using the method of the present invention is completed.

According to this embodiment, as described above, there is no reduction in the thickness of the sidewall 28 during the entire surface etching when forming the sidewall, so that the source and drain offset regions, that is, the n-type source region 27S and
Since the - type drain region 27D is formed to a predetermined length without variation, the characteristics of the LDD-MOSFET are stabilized.

Further, in this embodiment, the CCVD-5in film 26 is not necessarily required.

In addition, in the method of the present invention, the end point detection layer provided in the off-chip area is not limited to the SiJ and Si substrates shown in the above embodiments, but may contain a different element from the film to be etched over the entire surface. As long as it is a layer of matter, the type does not matter.

In addition, the end point detection means is not limited to the method using the emission spectrum intensity, but may also be an optical measurement method, a mass spectrometry method, a detection method using a laser, a method using photoluminescence, or the like.

〔Effect of the invention〕

As explained above, according to the present invention, the detection accuracy of the end point of etching is improved in the entire surface etching during sidewall formation, over-etching is prevented, and a sidewall having a predetermined thickness and a gentle slope shape is formed. Therefore, the present invention is effective in improving the yield and reliability of semiconductor devices by preventing wiring breakage, stabilizing offset length, etc.

[Brief explanation of drawings]

FIGS. 1(a) to (f) are process cross-sectional views of an embodiment of the present invention; FIG. 2 is a schematic plan view of a semiconductor substrate in an embodiment of the present invention; FIGS. 3(a) to (e) 4(a) to (f) are process sectional views of a conventional method, and FIG. 5 is a schematic plan view of a semiconductor substrate in the conventional method. In the figure, 1 is a semiconductor substrate, 2 is an underlying oxide film, 3A is
3B is SiJ, film pattern, 4 is field oxide film, 5 is 0-shaped trench, 6 is chip area, 7 is off-chip area, 8 is 5i02 film for isolation between elements, 9 is poly-Si buried layer, 10 is a second poly-Si layer, and 11 is a positive resist layer. 11a is a first exposure area, 11a2 is a second exposure area, 11P is a positive resist pattern, 125 is a poly-Si sidewall, and 13 is an SiO□ film for covering a poly-Si buried layer. ,5,1; ,57

Claims (1)

[Claims] A step of forming a first thin film on a semiconductor substrate (1) and patterning the first thin film to form a first thin film pattern (10P) having a step with respect to the periphery. Next, a second thin film (12) is formed on the entire surface of the substrate (1), and the entire surface of the second thin film (12) is etched to form a second thin film pattern (10P) on the side surface of the first thin film pattern (10P). A method for manufacturing a semiconductor device comprising the step of forming a sidewall (12S) made of a thin film of the second thin film (12), and in which the end point of the entire surface etching of the second thin film (12) is determined by end point detection means, 1) patterning the first thin film (10) on the chip region in the plane, and patterning the first thin film (10) on a part or the entire region outside the chip region, either simultaneously or separately from the step of patterning the first thin film (10). The first thin film (
10), and a part or the entire region of the first thin film (10) outside the removed chip area is removed at the etching end point when etching the entire surface of the second thin film (12). A method for manufacturing a semiconductor device, comprising a step contributing to detection.