JPH0325029B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an ultra-high speed semiconductor device having a novel structure.

[Background of the invention]

As a new ultra-high-speed element, as shown in Figure 1,
A permable base transistor in which a comb-shaped metal layer is embedded in a semiconductor crystal has been proposed and prototyped (C.O. Bosler, G.D.
Arrays (COBozler and GDAlley); IEEE Trans.Electorn Devices
Devices), ED-27 1128 (1980)). In the figure, 5 is a base region, 1 is a collector, 2 is a metal base, 3 is an emitter, and 6 is a back metal electrode. This type of device is advantageous for increasing speed because the distance traveled by electrons is very short, but because variations in the line width of the embedded metal 2 have a large effect on the operating voltage of the transistor, so-called threshold control is difficult. There is a drawback. Therefore, Kroemer proposed that this metal layer be used not as a control electrode but as an embedded wiring for the base layer of a bipolar transistor. (H. Kramer (H.
Kroemer); Journal of Vaccination Science and Technology (J.Vac.Sci.
Technol.) BI, 126 (1983)). In the case of a bipolar transistor, the threshold voltage is determined by the built-in potential of the pn junction, so variations in the line width of the wiring have little effect. Since the resistance of a metal film is lower than that of a semiconductor, the base resistance can be kept low even if the base width is narrowed, making it possible to increase the speed. However, the only known means for realizing such a device is a permeable base transistor using GaAs, and no method has been developed that can realize Kroemer's proposal. A combination of silicon and silicide has been proposed as a way to achieve this. However, since this method uses heteroepitaxy between a semiconductor and a metal, precise control of manufacturing conditions is required. Since this method has restrictions on temperature, etc., it is desirable to use a highly conductive semiconductor instead of metal in order to facilitate manufacturing. However, the situation was such that the desired conductivity could not be obtained with ordinary semiconductors.

The present invention provides that in a so-called impurity superlattice in which impurities are doped in a superlattice-like manner, when the concentration of the n-type or p-type layer is one order of magnitude or more higher than the concentration of the other layer, the conductivity is higher than that of the bulk crystal. Since it has been found that a new ultrahigh-speed device can be realized by using this multilayer film of impurity-containing layers as a base electrode material.

[Purpose of the invention]

An object of the present invention is to form a semiconductor stack having multiple predetermined impurity-containing layers in contact with a base part as a buried type as a high conductivity layer, thereby greatly reducing base resistance and having excellent high-speed characteristics. The object of the present invention is to provide a transistor with improved characteristics.

[Summary of the invention]

The basic idea of the present invention is as follows. As shown in FIG. 2, a high concentration p-type semiconductor layer 11 and a low concentration n
It was discovered that in a semiconductor multilayer film fabricated to contain alternating type semiconductor layers 12, holes can be confined in a narrow layer in a two-dimensional gas manner, so high mobility can be achieved despite a high carrier concentration. Ta. Therefore, the conductivity of this semiconductor multilayer film can be made higher than that of the bulk. In particular, the film thickness of each layer is 10 Å to 1000 Å, more preferably 50 Å to 500 Å.
When set to Å, the conductivity can be maximized. The difference in impurity concentration between high concentration and low concentration must be one order of magnitude or more. A high concentration layer refers to a layer containing 10 ¹⁷ cm ^-3 or more. There is no particular upper limit, but the limit is usually about 10 ¹⁹ cm ^-3 . Since this multilayer film can be realized using a single semiconductor material, it has the characteristic that it can avoid difficulties in crystal growth due to lattice mismatch, interdiffusion, etc. that accompany the fabrication of heterojunctions. Therefore, even if this semiconductor film is processed, further epitaxial growth can be performed thereon relatively easily, so that a buried structure can be created. The present invention applies these characteristics to bipolar transistors to improve high-speed performance. That is, in an npn transistor with a normal configuration, the base resistance is formed by forming the above-mentioned semiconductor multilayer film in a comb or lattice shape on the p-layer, which is the base region, by selective growth or partial etching after uniform growth. It can be reduced.

Note that FIG. 3 shows the energy band structure in a cross section in the stacking direction of the aforementioned semiconductor multilayer stack. In the figure, 7 indicates the lower end of the conduction band, and 8 indicates the upper end of the valence band. 15 indicates a hole.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described with reference to FIG.

Example 1 First, a chemically cleaned Si100 substrate 21 was introduced into a molecular beam epitaxy apparatus, and under ultra-high vacuum,
A clean Si surface is created by heat treatment (Figure 4a). A molecular beam epitaxy device is one in which the ultimate vacuum is 10 ^-9 Torr or less, and each uses multiple independent molecular beams or atoms as evaporation sources. It is a type of vapor deposition equipment that has a source of radiation. The molecular beam epitaxy apparatus used in this example has an ultimate vacuum degree of
5×10 ^-11 Torr, Si, Ga and
Each has a separate molecular beam source for Sb.

Next, the temperature of the surface-cleaned Si substrate was increased to approximately 700°C.
from the point when the temperature becomes constant, the Si layer 22
begins to grow. At this time, Sb is simultaneously supplied from a molecular beam source so that the conductivity type becomes n type.
This may be P or As. Alternatively, it may be an ionized impurity. The n-type concentration is about 10 ¹⁸ cm ^-3 . When the film thickness reached 1 μm, the temperature of the Sb molecular beam source was lowered and the concentration was 10 ¹⁶
After growing an n-type layer with a width of ^0.3 μm and a width of 0.3 μm, the Sb shutter was closed, and the Ga molecular beam source shutter was opened.
A p-type layer 23 is grown to become a base region. At this time, a B molecular beam or an ion beam may be used instead of Ga. The concentration of this p-type layer is about 10 ¹⁸ cm ^-3 , and after growing to a thickness of 0.2 μm, the shutter of the Ga molecular beam source is closed.

Next, after taking out the sample from the MBE apparatus, a SiO ₂ film 24 with a thickness of about 2300 Å is formed by thermal oxidation method (fourth
Figure b). This SiO ₂ film is processed into a comb shape using a normal photolithography method. Area to remove _SiO2 film
If the thickness is 0.4 μm or less, electron beam lithography is used (Figure 4c). After processing the SiO ₂ film into a comb shape and thoroughly washing the sample, it was introduced into the MBE apparatus again.
After heating and cleaning at 800°C, MBE growth of Si is started. At this time, the substrate temperature was 700℃ and Ga was 1×10 ¹⁸
A p-type layer containing cm ^-3 is grown to a thickness of 300 Å, and then
An n-type layer containing 1×10 ¹⁶ cm ⁻³ of Sb is grown to a thickness of 300 Å.
This operation is repeated five times to form a semiconductor laminate (FIG. 4d). Each layer of the semiconductor laminate thus formed relies on the molecular beam epitaxial method, and the impurity profile of each layer does not have a statistical distribution beyond the degree of thermal diffusion determined by the growth temperature. Again, the substrate prepared in this way was taken out of the MBE equipment and exposed to SiO ₂
The film and the polysilicon layer 32 deposited thereon are etched off to form a Si epitaxial layer 3 having an impurity multilayer film.
1 into a comb-like structure (Fig. 4e). After washing the sample, reintroduce the substrate into the MBE device,
After heating and cleaning, a p-type semiconductor layer 25 is grown to a thickness of about 100 Å at a substrate temperature of about 650° C. again. Although this p-type semiconductor layer is not necessarily necessary, it is provided so that a sufficient barrier can be formed between the n-type semiconductor layer 26 grown thereon and the multilayer semiconductor layer 31.

Next, the dopant Ga is changed to Sb, and an n-type semiconductor layer 26 to be an emitter layer is formed (FIG. 4f). The impurity concentration at this time is 5×10 ¹⁹ cm ^-3 ,
The film thickness is 0.2 μm. After the semiconductor substrate prepared in this manner is taken out from the MBE apparatus, device isolation and electrode formation are performed using the same process as for a normal bipolar transistor, and device fabrication is completed. FIG. 4g shows a cross section perpendicular to the cross sections shown in FIGS. 4a to 4f. 30 is an insulating layer, 27 is an emitter, 28 is a base electrode, and 29 is a collector electrode. At this time, base electrode 2
8 is provided in contact with the semiconductor stack 31 .

The bipolar transistor fabricated in this way has a base resistance approximately 1/3 and a cut-off frequency 1.5 times that of a conventional bipolar transistor, which has the same structure except for the impurity multilayer film mentioned above. As a result, an improvement in high-speed performance was observed.

Note that the shape of the electrode does not necessarily have to be comb-shaped; it may have any shape as long as it has an opening, and various modifications are possible.

〔Effect of the invention〕

According to the present invention, in a silicon bipolar transistor, an increase in base resistance that occurs when the base layer thickness is made thinner can be prevented, and as a result, transistor characteristics, particularly high speed performance, are improved by more than twice.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view of a permable base transistor, Figure 2 is a cross-sectional view showing the structure of an impurity multilayer film, Figure 3 is a diagram showing its band structure, and Figure 4 is a diagram showing the manufacturing process of the semiconductor device of the present invention. FIG. 3 is a cross-sectional view showing the device after completion. 1: Collector area, 2: Metal grid electrode,
3: emitter electrode, 11: p-type layer, 12: n-type layer, 15: hole, 21: silicon substrate, 22: collector region (n-type layer), 23: base layer (p-type),
24: SiO ₂ film, 25: P-type layer, 26: Emitter region (n-type layer), 27: Emitter electrode, 28: Base electrode, 29: Collector electrode, 31: Impurity multilayer film, 32: Polysilicon impurity multilayer film .

Claims (1)

[Scope of Claims] 1. An emitter region, a base region, and a collector region are sequentially stacked, and a semiconductor multilayer film in which semiconductor thin films having mutually opposite conductivity types are stacked in contact with the base region is disposed, and the semiconductor multilayer A semiconductor device in which a base electrode is formed in contact with a film, and the impurity concentrations of the two semiconductor thin films having opposite conductivity types have a concentration difference of one digit or more, and the thickness of the semiconductor thin film is 10 Å to 1000 Å. A semiconductor device characterized by: 2. The semiconductor device according to claim 1, wherein the thin film containing impurities at a high concentration in the semiconductor thin films having conductivity types opposite to each other is of n-conductivity type. 3. The semiconductor device according to claim 1, wherein the thin film containing impurities at a high concentration in the semiconductor thin films having conductivity types opposite to each other is of p conductivity type. 4. The semiconductor device according to claim 1, wherein the semiconductor multilayer film is processed into a comb shape or a lattice shape and is provided in contact with the base region.