JP2576770B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a bipolar transistor which operates at a low temperature of about liquid nitrogen temperature (77 K) and a method of manufacturing the same.

[0002]

2. Description of the Related Art In a low temperature state, there are advantages such as improvement of MOS transistor characteristics and reduction of wiring resistance, and a MOS LSI operating at a low temperature of about liquid nitrogen temperature is being developed. For a bipolar LSI, the reduction of the wiring resistance is extremely effective in improving the operation speed. In addition, in a BiCMOS LSI in which a bipolar transistor and a MOS transistor are formed on the same chip, a demand for low-temperature operation is increasing similarly to the MOS LSI. However, in the conventional bipolar transistor, the current amplification factor _hFE is significantly reduced at a low temperature. This is due to the bandgap narrowing ΔE _ge in the high impurity concentration emitter due to the high impurity concentration effect.
Is larger than the band gap reduction ΔE _gb in the base layer having a low impurity concentration, and the minority carriers injected from the base to the emitter increase as the temperature decreases. h _FE is represented by the following equation (1) (Furukawa Shizujiro, Amamiya Yoshihito: “Silicon-based hetero device”, p.
242, Maruzen Co., Ltd.).

[0003] _{h FE = (W E N E} D nB / W B N B D PE) exp {(ΔE gb -ΔE ge) / kT} ... (1) where, N _E is impurity concentration in the emitter layer, N _B is the impurity concentration in the base layer, D _pE is the diffusion coefficient of holes emitter layer, D _nB is the electron diffusion coefficient in the base layer, W _E is the emitter layer thickness, W _B is the base layer The thickness, k is the Boltzmann coefficient, and T is the absolute temperature. A large drop in h _FE at low temperatures increases the emitter transition time and consequently the cutoff frequency f
_T will be reduced.

Recently, several new-structured bipolar transistors have been proposed to solve this problem. Among them, as a first conventional example, a heterojunction bipolar transistor using a material having a small band gap for a base layer, for example, silicon germanium is used, for example, as an IEEE IEDM Technical Digest.
al Digest) p. 17, 1990.

Further, as a second conventional example, a pseudo heterojunction in which the emitter concentration is lower than the base concentration is described.
Bipolar transistors (HBTs) are, for example, IEE Transactions on Electron
Devices (IEEE Transactions o
n Electron Devices) vol. 3
7, no. 10, p. 2222, 1990. In this case, the band gap reduction ΔE _gb of the heavily doped base layer is larger than the band gap reduction ΔE _{ge of the lightly} doped emitter layer.
_FE is improved.

As a third conventional example, even in a normal transistor structure, the difference in band gap reduction between the emitter layer and the base layer is reduced by increasing the impurity concentration of the base layer so as to approach the impurity concentration of the emitter layer. For example, it is possible to suppress the decrease in _hFE at a low temperature. For example, IEE Transactions on Electron Devices (IEEE Transact)
ions on Electron Devices)
vol. 36, no. 8, p. 1503, 1989. As an example of the third conventional example, FIG. 6 is a cross-sectional view of a bipolar transistor when a base layer having an impurity concentration is formed on a collector layer by a low-temperature epitaxial growth method, and FIG. 6 shows an impurity distribution in a depth direction indicated by an arrow X. FIG.

In FIG. 6, an n ⁺ -type buried layer 2, an n-type epitaxial layer (collector portion of a bipolar transistor) 3 and a field oxide film 4 are formed on a p-type silicon substrate 1. A base layer 15 made of a p-type silicon epitaxial layer selectively grown at a low temperature (450 to 700 ° C.) is formed on the epitaxial layer 3. Here, the low temperature of the low temperature epitaxial is one of the epitaxial layer forming temperatures at which a normal collector portion is formed.
It shows that the temperature is lower than 000 to 1150 ° C.
The base layer 15 has a boron concentration of 2 × 10 ¹⁹ cm ⁻³ and a thickness of 55
nm. When the base layer is formed by ion implantation, the impurity distribution is widened and a low concentration region is formed.
In a low temperature state, a region having a low concentration is easily affected by freeze-out in which the movement of electrons is restricted, and the base resistance increases.

It is reported, for example, in the same document as the above-mentioned third conventional example that when the impurity concentration becomes 3 × 10 ¹⁸ cm ⁻³ or less, the resistance increases due to the freeze-out effect. For this reason, as shown in FIG. 7, it is preferable that the base layer is formed by a low-temperature epitaxial growth method so that the impurity distribution is square. A p ⁺ -type external base layer 7 is provided on both sides of the base layer 15, and an oxide film 8 is provided on the surface of the base layer 15.
And an n ⁺ -type impurity formed on a part of the surface of the base layer 15 by diffusion of n-type impurities from an emitter electrode 10 made of polysilicon having a phosphorus concentration of 1 × 20 ²⁰ cm ⁻³ and a thickness of 200 nm. An emitter layer 11 is formed. The junction depth of the emitter layer 11 is 25 nm. An interlayer insulating film 12 and an aluminum wiring 13 are provided thereon.

In the case of the impurity distribution in the conventional transistor shown in FIG. 7, the n-type impurity concentration (donor concentration) in the emitter layer 11 is 1 × 10 ²⁰ cm ^-3 and the p-type impurity concentration in the base layer 15 is (Acceptor concentration) is 2 × 1
0 ¹⁹ cm ^-3 . The band gap reduction at this time is ΔE _ge = 96 meV in the emitter and ΔE _gb = 9 in the base.
It becomes 5 meV and there is almost no band gap difference. This means that IEE Transactions on Electron Devices (IEEE Transa)
actions on Electron Device
s) ED-34, p. 1580, 1987 and the Digest of International Device Meeting
al Device Meeting) p. 24,19
86.

The foregoing has described the prior art of bipolar transistors studied for low temperature applications. Next, although not for low-temperature use, a prior art bipolar transistor having a structure similar to the present invention (Japanese Patent Laid-Open No. 4-99328).
Will be described with reference to a vertical cross-sectional view of the transistor in FIG. 9 and an impurity profile in FIG. After forming an n ⁺ -type buried layer 2 and an n-type epitaxial layer (collector portion of a bipolar transistor) 3 on a p-type silicon substrate 1, a p-type base layer is formed by ion implantation (or MBE). The base layer has a peak concentration of 2 × 10 ¹⁶ to 1 (FIG. 10 shows the case of ion implantation).
The second base layer 6 having a low impurity concentration of about × 10 ¹⁷ cm ⁻³
A and a first base layer 5A having a high impurity concentration with a peak concentration of about 1 × 10 ^{18 to} 5 × 10 ¹⁸ cm ⁻³ .
Further, a part of the surface of the second base layer 6A has a surface concentration of 1 ×.
N ⁺ -type emitter layer 11A of 10 ²⁰ to 1 × 10 ²¹ cm ^-3
Are formed. Note that 10A is an emitter electrode.

The features of this conventional example are as shown in FIG.
The high impurity concentration emitter layer 11A and the high impurity concentration first layer
Is not in contact with the base layer 15A of the
The point is that the electric field in the depletion layer when a reverse electric field is applied to 1A and the base layer is relaxed, and the generation of hot carriers is suppressed. However, in this conventional example, since the thickness of the base layer is increased by the amount of the second base layer 6A for relaxing the electric field, the base transit time during which electrons pass through the base layer is increased, and the cutoff frequency f _T is reduced. . Further, an electric field is generated between the second base layer 6A and the first base layer 5A due to a concentration difference. Since this electric field acts in the opposite direction to the base travel of the electrons, the base travel time also increases. Further, the impurity concentration of the base layer 6A has a disadvantage that when used at a low temperature, the layer resistance of the intrinsic base immediately below the emitter greatly increases due to the effect of freeze-out.

[0012]

As described above, the transistor of the first conventional example has a high h _FE even at a low temperature.
While indicating the base - will be a sharp drop in f _T in the high current region of the collector current is generated by the influence of heterojunction that exists between the collector, the circuit operating at a high current region, such as BiCMOS circuit Cannot be used. This is the case, for example, with the IEEE IMD Technical Digest (IEEE I
EDM Technical Digest) p. 86
1, 1991).

In a second conventional transistor,
Since the emitter concentration must be lower than that of the conventional transistor, an increase in emitter resistance becomes a problem.

In the third conventional example, when the impurity distribution and the temperature dependence of the _hFE of the transistor are measured, it is found that _hFE decreases as the temperature decreases, as shown in FIG. Was. This is because the p-type impurity concentration (acceptor concentration) compensated in the emitter layer 11 is increased because the impurity concentration in the base layer is increased, and the band gap reduction ΔE _ge in the emitter layer 11 is reduced only by the donor concentration. It is considered that the value is larger than the case where the estimation is made. This is because the band gap reduction is affected by both the donor concentration and the acceptor concentration in the semiconductor. Further, as shown in FIG. 8, f _T of the conventional transistor is reduced at room temperature lower temperature than in (300K) (89K). This is because the emitter transition time is increased due to a decrease in h _FE.

To prevent freeze-out at low temperatures,
The impurity concentration in the base layer must be increased. When the emitter layer is formed in the base layer by impurity diffusion, if the impurity concentration in the base layer is made uniform as in the past, the acceptor concentration contained in the emitter layer increases as the impurity concentration in the base layer increases. Therefore, the reduction of the band gap of the emitter layer becomes larger than estimated by the donor concentration alone. As a result it bandgap reduction difference of the emitter layer and the base layers is large, resulting in a decrease in h _FE with decreasing temperature.

[0016]

According to a first aspect of the present invention, there is provided a semiconductor device having a collector layer formed on a silicon substrate of a first conductivity type via a buried layer of a second conductivity type, and a collector layer formed on the collector layer. A first base layer having a high impurity concentration of a first conductivity type, a second base layer having a low impurity concentration of a first conductivity type formed on the first base layer, and a second base layer having a low impurity concentration; The second base layer is formed to have substantially the same thickness as the second base layer, and
Of the impurity provided at the connection portion of the second base layer and the second base layer
And a second conductivity type emitter layer including a region .

According to a second aspect of the invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a buried layer of a second conductivity type on a silicon substrate of a first conductivity type; and forming an epitaxial layer of a second conductivity type to be a collector layer. Forming a first base layer of a first conductivity type having a high impurity concentration and a second base having a low impurity concentration in sequence on the epitaxial layer; and providing an insulating film on the second base layer. Forming an opening in an emitter formation region by patterning, forming a polysilicon film containing a second conductivity type impurity on the entire surface including the opening, and forming an emitter electrode by patterning; Heat treatment to diffuse impurities from the emitter electrode
An error is formed at the connection between the first and second base layers.
Forming an emitter layer including a pure inclined region and having substantially the same thickness as the second base layer on the second base layer.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1A to 1D are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a first embodiment of the present invention.

As shown in FIG. 1A, arsenic is ion-implanted on a p-type silicon substrate 1 to form an n ⁺ -type buried layer 2 and further contains 2 × 10 ¹⁷ cm ^{-3 of} phosphorus. n-type epitaxial layer (collector of bipolar transistor) 3
Is formed at a growth temperature of 1000 to 1150 ° C. Next, a field oxide film 4 is formed by a selective oxidation method to partition an element region. The manufacturing steps used so far are very generally used. Next, p is selectively applied to the surface of the epitaxial layer.
A high-concentration first base layer 5 and a low-concentration second base layer 6 composed of a silicon epitaxial layer are continuously formed. FIG. 2 shows the growth film thickness and the impurity concentration including the emitter layer formed in a later step.

These silicon epitaxial layers are made of UH
V (Ultra High Vaccum) -CVD
(Chemical vapor deposition
It grows at low temperature of 450-700 degreeC using the n) method. The low temperature in this case indicates that the temperature is lower than the epitaxial layer formation temperature of 1000 to 1150 ° C. for forming a normal collector portion. Further, by controlling the temperature of the wafer, the flow rate of the gas, and the like by using the UHV-CVD method, the silicon epitaxial layer can be selectively formed only at the portion where the silicon surface is exposed.

Next, as shown in FIG.
After passing through a photoresist process on both sides of the base layers 5 and 6, boron is implanted with an energy of 10 to 30 keV and an implantation amount of 1
Ion implantation under the condition of × 10 ^{15 -1} × 10 ¹⁶ cm ^-3
A p ⁺ -type external base layer 7 is formed. Then, about 1 thickness
After forming an oxide film 8 of 00 nm, patterning is performed to form an opening 9 in the emitter formation region.

Next, as shown in FIG. 1C, a polysilicon film containing 5 × 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ of phosphorus or arsenic is grown to a thickness of 100 to 300 nm and patterned to form an emitter electrode 10. Form. Then 700-1000 ° C,
An n ⁺ -type emitter layer 10 having substantially the same thickness as the second base layer 6 is formed in the second base layer 6 by diffusing impurities from the emitter electrode 10 by a high-speed heat treatment for 3 to 20 seconds. The impurity concentration distribution in the direction of arrow X in FIG. 1C is shown in FIG.

As shown in FIG. 1D, an interlayer insulating film 12 is formed on the entire surface, an opening is formed, a base electrode made of aluminum wiring 13 is formed, and a bipolar transistor is completed.

The feature of the transistor of this embodiment formed in this way is that the first base layer 5 has an impurity concentration of 5
At least 10 ¹⁸ cm ⁻³ , the impurity concentration of the second base layer 6 is 1/5 to 1/1 compared to the impurity concentration of the first base layer 5.
0, the emitter layer 11 is formed by impurity diffusion from the emitter electrode 10 formed on the second base layer 6, and the junction depth thereof is equal to the first and second base layers.
And the thickness of the second base layer 6 is substantially the same as that of the second base layer 6 including the inclined region of the impurity provided in the connection portion of FIG.

In this structure, the intrinsic base region immediately below the emitter is formed only by the first base layer 5. However, FIG. 2 does not show the spread of the impurity distribution of the base layer 5 due to the heat treatment during the formation of the emitter layer (the impurity distribution immediately after the growth of the base layer). The heat treatment for forming the emitter layer is performed, for example, by 9
When heating is performed at a high speed of 100 ° C. for 10 seconds, when the concentration of the base layer is 2 × 10 ¹⁹ cm ⁻³ , it spreads by 2 nm on both sides.

The impurity concentration of the first base layer 5 needs to be 3 × 10 ¹⁸ or more so as not to be affected by freeze-out, and is preferably 5 × 10 ¹⁸ cm ⁻³ or more. Further, in order to reduce the influence on the band gap reduction in the emitter layer, the impurity concentration of the second base layer is preferably about 1/5 of that of the first base layer, and when it is 1/10 or less, the base resistance increases. I do.

As described above, in the first embodiment, the acceptor concentration (boron concentration in this embodiment) existing in the n-type emitter layer 11 is reduced while the intrinsic base concentration immediately below the emitter is kept high as in the conventional case. Therefore, the reduction of the band gap in the emitter layer is hardly affected by the acceptor concentration. FIG. 3 shows a measurement result of the temperature dependence of _hFE of the transistor having the impurity distribution of this example. h _FE increases in the range of 300K to 120K,
The high value of about 90 is maintained in the range of 120K to 89K. As a result, a current amplification factor as high as 2.2 times at 89K was obtained as compared with the transistor having the conventional impurity distribution indicated by the broken line. This is because the band gap reduction ΔE _ge of the emitter layer can be reduced by lowering the acceptor concentration in the emitter layer, and the temperature dependence of h _FE is improved. Figure shows the f _T -I _c (collector current) characteristics at 300K and 89K of the bipolar transistor having 4 to the impurity distribution in this embodiment. It is considered that the peak value of f _T increased at 89 K because the emitter transition time was shortened by the increase in h _FE . As a result, f of the conventional transistor shown in FIG.
Compared to _T, f _T peak value of about 1.3 times at 89K was obtained.

As described above, according to the first embodiment, it is understood that the transistor characteristics are clearly improved in a low temperature state near the temperature of liquid nitrogen. Further, in the first embodiment, the intrinsic base region immediately below the emitter layer 11 is formed only of the first base layer 5, and the intrinsic base can be adjusted to a thickness that does not allow punch-through between the emitter and the collector.
Unlike the conventional example shown in FIG. 9, the thickness of the intrinsic base does not increase, and a reverse electric field due to the concentration difference inside the intrinsic base does not occur. Further, the intrinsic base region is hardly affected by freeze-out at low temperatures.

Next, FIG. 5 shows an impurity profile of the second embodiment of the present invention. This is one in which the second base layer 6 is formed of a non-doped epitaxial layer in the first embodiment. Since in this structure capable of very low acceptor in the emitter, improved h _FE at low temperatures becomes equal to or larger than the first embodiment.

[0030]

As described above, according to the present invention, the base layer is composed of the first base layer having a high impurity concentration and the second base layer having a low impurity concentration.
By forming an emitter layer having substantially the same thickness as the second base layer on the second base layer, the current amplification factor h _FE can be improved. There is an effect that the frequency f _T can be improved.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor chip for explaining a first embodiment of the present invention.

FIG. 2 is a diagram showing an impurity concentration distribution in the first embodiment.

FIG. 3 is a diagram showing the temperature dependence of the current amplification factor of the embodiment and the conventional example.

FIG. 4 is a diagram showing f _T -I _c characteristics in the example.

FIG. 5 is a diagram showing an impurity concentration distribution in a second embodiment.

FIG. 6 is a cross-sectional view of an example of a conventional semiconductor device.

FIG. 7 is a diagram showing an impurity concentration distribution of a conventional semiconductor device.

FIG. 8 is a graph showing f _T -I _c characteristics of a conventional semiconductor device.

FIG. 9 is a cross-sectional view of another example of a conventional semiconductor device.

FIG. 10 is a diagram showing an impurity concentration distribution of another example of a conventional semiconductor device.

[Explanation of symbols]

 Reference Signs List 1 silicon substrate 2 buried layer 3, 3A epitaxial layer 4 field oxide film 5, 5A first base layer 6, 6A second base layer 7 external base layer 8 oxide film 9 opening 10, 10A emitter electrode 11, 11A Emitter layer 12 Interlayer insulating film 13 Aluminum wiring 15 Base layer

Claims (2)

(57) [Claims] 1. A collector layer formed on a silicon substrate of a first conductivity type via a buried layer of a second conductivity type, and a first conductive type high impurity concentration first layer formed on the collector layer. a base layer, a second base layer of the first formed in the base layer low impurity concentration of the first conductivity type, at approximately the same thickness as the second formed in the base layer a second base layer And before
An impurity provided at a connection between the first and second base layers;
A second conductivity type emitter layer including an inclined region of the object. 2. A step of forming a second conductivity type buried layer on a first conductivity type silicon substrate and then forming a second conductivity type epitaxial layer serving as a collector layer, and forming a first conductivity type buried layer on the epitaxial layer. Forming a first base layer having a high impurity concentration and a second base layer having a low impurity concentration successively; providing an insulating film on the second base layer and then patterning the opening to form an opening in the emitter formation region; Forming a part,
Forming a polysilicon film containing a second conductivity type impurity on the entire surface including the opening and then patterning to form an emitter electrode; and heat-treating the substrate to diffuse the impurity from the emitter electrode to form the first and second impurities . Of the base layer
The method of manufacturing a semiconductor device which comprises a step of forming a substantially same thickness emitter layer of the second base layer comprises a sloped region of the impurities formed in the connecting portion and the second base layer .