JPH03249878A - Clamp circuit - Google Patents

Abstract

PURPOSE:To reduce the circuit scale by providing a DC level setting circuit on plural signal paths whose gain characteristics are different from each other, respectively, and controlling each DC level setting circuit in accordance with a comparison output of a DC level of a signal passing through one signal path and a reference level. CONSTITUTION:DC level setting circuits 4A, 4B are provided on plural signal paths S1 and S2 whose gain characteristics are different from each other, respectively, a DC level of a signal passing through the signal paths S1, S2 and a reference level are compared by a comparator 6, and in accordance with an output of the comparator 6, each DC level setting circuit 4A, 4B is controlled. In such a way, since control currents of the clamp level setting circuits 4A, 4B of plural signal paths S1, S2 can be formed by one comparator, the circuit scale can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a lamp circuit suitable for use in constructing a comb-shaped filter disposed in, for example, a VTR.

[Summary of the invention]

This invention arranges a DC level setting circuit in each of a plurality of signal paths having different gain characteristics, and compares the DC level of a signal passed through at least one signal path among the plurality of signal paths with a reference level. By controlling each DC level setting circuit according to the comparison output, the circuit scale can be reduced.

[Conventional technology]

For example, when constructing a comb-shaped filter for a VTR, the luminance signal Y from the input terminal 50 is delayed by one line via the IH delay circuit 51, as shown in FIG. The output is connected to two signal paths Sll and S+
Z, and the signal passed through one signal path S passes through the trap circuit 52 and has a frequency f sc ('f sc
: color subcarrier frequency) component and take it out from the output terminal 55, and the signal passed through the other signal path S+Z may be taken out from the output terminal 56 as is. In such a case, for each signal path Sll and 5ill,
It is necessary to provide clamp circuits 53 and 54 that respectively set the DC level of the signal to a predetermined level. Conventionally, in such a case, a clamp circuit configured as a feedback clamp circuit that compares the input signal level with a reference level and controls the DC level of the input signal according to the comparison output is installed in each signal path S and S+Z. 53 and 54
are arranged respectively.

[Problem to be solved by the invention]

However, when the feedback clamp circuits 53 and 54 are arranged in each signal path Sll and Sl in this way, the circuit scale becomes extremely large because the feedback clamp circuit requires a comparator to compare the input signal level and the reference level. The problem arises that it becomes larger.

Therefore, an object of the present invention is to provide a clamp circuit that can reduce the circuit scale when clamp circuits are arranged in a plurality of signal paths.

[Means to solve the problem]

The present invention includes a DC level setting circuit 4A disposed in each of a plurality of signal paths S1 and S2 having different gain characteristics;
4B, and a comparator 6 that compares the DC level of the signal passed through at least one signal path of the plurality of signal paths S and S2 with a reference level, and according to the output of the comparator 6, each DC This is a clamp circuit designed to control level setting circuits 4A and 4B.

[Operation] The trap circuit 3 disposed on the signal path S+ is configured such that the DC level is transferred as is. For this reason,
The DC level of signal path S is equal to the DC level of signal path S2. Therefore, when the output formed by comparing the level of the signal path S1 and the reference level is supplied to the clamp level setting circuits 4A and 4B, the signal path S1 is
Not only the DC level of signal path S2 but also the DC level of signal path S2 is controlled to be equal to the reference level.

In this way, one comparator 6 can form control currents for clamp level setting circuits for multiple signal paths.
The circuit scale can be reduced.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. In this embodiment, the present invention is applied to construct a comb-shaped filter for a VTR. In FIG. 1, a signal (for example, a luminance signal) from an input terminal 1 is input to an I
It is delayed by one line via the H delay circuit 2. The output of the IH delay circuit 2 is divided into two signal paths S and S3.

The signal via the signal path SI is supplied to a trap circuit 3 which removes the frequency rsc component, for example.

Note that this trap circuit 3 needs to be configured so that the DC level is transferred as is. The output of the trap circuit 3 is supplied to a clamp level setting circuit 4A. The output of the clamp level setting circuit 4A is taken out from the output terminal 9A and is supplied to a input terminals of the switch circuit 5.

The signal via the signal path S2 is supplied to the clamp level setting circuit 4B. The output of the clamp level setting circuit 4B is taken out from the output terminal 9B and is supplied to b input terminals of the switch circuit 5.

The output of the switch circuit 5 is supplied to the non-inverting input terminal of the comparator 6. A reference level is supplied from an input terminal 8 to an inverting input terminal of the comparator 6 .

A clamp capacitor 7 is arranged between the output end of the comparator 6 and ground. The output of the comparator 6 is supplied to the clamp level setting circuits 4A and 4B.
Each current source of B is controlled.

The switch circuit 5 is for selecting the signal path to be emphasized from among the signal paths SI and S. If the signal path to be emphasized is determined in advance, this switch time!
5 can be omitted.

When the switch circuit 5 is switched to the a side, the comparator 6 compares the signal level passed through the signal path S with the reference level.

This comparison output controls the current source forming the clamp level setting circuit 4A. As a result, the signal path S,
The DC level of the signal passed through is controlled to be equal to the reference level.

At this time, the output of this comparator 6 is connected to the other signal path S.
2 is supplied to the clamp level setting circuit 4B arranged in
Clamp level setting time! The current sources constituting 4B are controlled. The trap circuit 3 disposed in the signal path S is configured so that the DC level is transferred as is.
The DC level of the signal path Sl and the DC level of the signal path S8 are equal. Therefore, if the output of the comparator 6 formed by comparing the level of the signal path S1 and the reference level is used in this way, not only the DC level of the signal path SI but also the DC level of the signal path S2 will be equal to the reference level. It can be controlled to be equal.

Note that when the switch circuit 5 is switched to the b side, the signal path ls
The DC level of signal z and the reference level are compared by the comparator 6, and the comparison output controls the DC level of the signal path S2, as well as the DC level of the signal path S. Also in this case, both the DC level of the signal path S1 and the DC level of the signal path sz can be set to the reference level.

In this way, in one embodiment of the present invention, one comparator 6 can set the DC level of the signals passed through the two signal paths S1 and S2.

FIG. 2 shows a specific configuration of an embodiment of the present invention. In FIG. 2, an input terminal 11A is connected to the base of a PNP transistor 13A via a resistor 12A, and a connection is made between the base of the transistor 13A and ground.
Transistor 14A is connected. Transistor 13A
collector is grounded. The emitter of transistor 13A is connected to power supply terminal 10 via current source 15A.

At the same time, the emitter of the transistor 13A is connected to the output terminal 9A and to the base of the transistor 16.

Input terminal 11B is connected to the base of PNP transistor 13B via resistor 12B, and transistor 14B is connected between the base of transistor 13B and ground. The collector of transistor 13B is grounded. The emitter of transistor 13B is connected to power supply terminal 10 via current source 15B. At the same time, the emitter of the transistor 13B is connected to the output terminal 9B and the base of the transistor 18.

The emitters of transistors 16 and 17 are commonly connected,
This connection point is connected to the collector of transistor 20. A collector of transistor 16 is connected to power supply terminal 10. The collector of transistor 17 is transistor 19
and the base of transistor 22. The base of transistor 17 is connected to the emitter of transistor 22.

The emitters of transistors 18 and 19 are commonly connected,
This connection point is connected to the collector of transistor 21. The collector of transistor 18 is connected to power supply terminal IO. The collector of the transistor 19 is connected to the power supply terminal 10 via the current source 23, and the collector of the transistor 19 is
7 and the base of transistor 22.

The emitters of transistors 20 and 21 are commonly connected, and the emitters of transistors 20 and 21 are grounded via a resistor 39. The base of transistor 20 is connected to an input terminal 25 for the switch control signal. The base of the transistor 21 is the input terminal 26 for the switch control signal.
connected to.

A collector of transistor 22 is connected to power supply terminal 10 . The emitter of transistor 22 is grounded via current source 24 and connected to the base of transistor 17, the base of transistor 19, and the base of transistor 270.

The emitters of transistors 27 and 28 are connected in common, and this connection point is grounded via current 29. Transistors 30 and 31 are connected between the collector of the transistor 27 and the collector of the transistor 28 and the power supply terminal 10.
．． A load circuit consisting of resistors 32 and 33 and resistors 34 and 35 is connected. The base of transistor 28 is connected to reference level input terminal 8.

Clamp capacitor 7 is connected between the collector of transistor 28 and ground, and the collector of transistor 28 is connected to the base of transistor 36.

A collector of transistor 36 is connected to power supply terminal 10. The emitter of transistor 36 is connected to the collector and base of transistor 38 via resistor 37. The emitter of transistor 38 is grounded. The collector and base of transistor 38 are connected to transistors 14A and 1.
Connected to the base of 4B.

Signal path S connected to input terminal 11A via trap circuit 3
l signals are supplied. This signal is supplied to the base of emitter follower transistor 13A via resistor 12A. A transistor 14A serving as a current source is arranged between the base of the transistor 13A and ground. these,
A clamp level setting circuit 4A is constituted by transistors 13A and 14A.

A signal path S2 from the IH delay circuit 2 is connected to the input terminal 11B.
signal is supplied. This signal is supplied to the base of emitter follower transistor 13B via resistor 12B. A transistor 14B serving as a current source is arranged between the base of the transistor 13B and ground. These transistors 13B and 14B constitute a clamp level setting circuit 4B.

The switch circuit 5 is constructed by a differential circuit consisting of transistors 16 and 17, a differential circuit consisting of transistors 18 and 19, and a differential circuit consisting of transistors 20 and 21.
is configured. This switch circuit 5 is switched in response to switch control signals supplied from input terminals 25 and 26 to the bases of transistors 20 and 21.

The output of this switch circuit 5 is supplied to a transistor 27. A terminal 8 is connected to the base of the transistor 28.
A reference level is supplied from transistor 2
7 and 28 constitute a comparator 6.

The output of comparator 7 is obtained from the collector of transistor 28. The current flowing through the transistor 38 is controlled according to the output of the comparator 7. Then, the currents of the transistors 14A and 14B connected to the transistor 38 in a current mirror are controlled. When the current values of transistors 14A and 14B are controlled, the DC level of the signal supplied to input terminal 11A and input terminal 11B is set accordingly.

〔Effect of the invention〕

According to this invention, one comparator 6 can form control currents for clamp level setting circuits for a plurality of signal paths. Therefore, it is not necessary to provide a comparator for each of the plurality of signal paths, and the circuit scale can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a connection diagram of an embodiment of the invention, and FIG. 3 is a block diagram used to explain a conventional clamp circuit. Explanation of main symbols in the drawings 4A, 4B: Clamp level setting circuit. 6: Comparator.

Claims (1)

[Claims] A DC level setting circuit disposed in each of a plurality of signal paths having different gain characteristics, and a DC level and a reference level of a signal passed through at least one signal path among the plurality of signal paths. and a comparator for comparing the two, and the clamp circuit is configured to control each of the DC level setting circuits according to the output of the comparator.