JPH02207607A - Differential amplifier equipped with gain switching circuit - Google Patents

Abstract

PURPOSE:To decrease the fluctuation of an output direct current level by controlling the turning-on and off of 7th and 8th transistors by switching the voltage of a control terminal and switching a gain. CONSTITUTION:When a voltage higher than a control terminal C2 is impressed to a control terminal C1, 7th and 8th transistors Q7 and Q8 are controlled to be turned off and differential signals to flow to transistors Q9 and Q10 are synthesized. Then, a signal component is canceled and only a direct current component is remained. This direct current is distributed by transistors Q13 and Q14 and resistors R7 and R8 and flows to resistors R5 and R6. When the transistors Q7 and Q8 are turned on, a current I2 of a constant current source CS2 is distributed by transistors Q3 and Q4 and flows to the resistors R5 and R6. Thus, the current of the constant current source CS2 is distributed to be half and flows to the resistors R5 and R6 regardless of the turning-on and off of the transistors Q7 and and Q8 and the change of the output direct current level is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a differential amplifier having a gain switching circuit using current addition.

BACKGROUND ART] FIG. 3 shows a differential amplifier having a conventional gain switching circuit using current addition. In this circuit, transistor Q1,
Each base of C2 is connected to the input terminal 1.2, each emitter is connected to a constant current source C3I having a current of 11 through resistors R1 and R2, and each collector is connected to a constant voltage source C3I through resistors R5 and R6. A differential amplifier circuit is formed which is connected to CC and has an output between the collectors thereof, and in order to switch the gain, a transistor Q3 is connected to each collector of transistors Q1 and C2 via a switch S1.
, C4 are connected, and the transistors Q3, C4 are connected to each other.
A current I2 is applied to the emitters of 4 through resistors R3 and R4, respectively.
The base of transistor Q3 is connected to the base of transistor Q1, and the base of transistor Q4 is connected to the base of transistor Q2.

When changing the gain, the switches S1 and 32 are turned on and off at the same time. In this case, the differential gain Gd, which is the ratio of the input differential voltage ΔVin and the output differential voltage ΔVout, is
The internal emitter resistance of each transistor Q1 to Q4 is re
Then, it changes as shown in the following equation depending on whether the switches S1 and S2 are turned on or off.

Gd off=(R5+R6/(R1+R2+2
re )・・・・・・ (1) Gd on= (R5+R6)/(R1+R2+2
re )+(R5+R6) /(R3+R4+2 r
e)... (2) However, Gd off indicates the gain when the switches S1 and S2 are off, and Gd0n indicates the gain when the switches S1 and S2 are on.

[Problem to be solved by the invention] By the way, in equations (1) and (2), R1=R2=R3
= R4 and R5 = R6, and the input differential voltage ΔVin is 0.
Then, the current flowing through the load resistors R5 and R6 is 11/2 when the switches S1 and S2 are off, and (■1+
12)/2, and the output voltage V1 o when off and on
ff , Vl 0n , V2off , and V2on are expressed as follows.

Vl off =V2 off =Vcc-R5x I
1/2...(3) Vl on=V2 on=Vcc-R5x (I 1→
-I2)/2 ・・・・・・(4
) From the above, it can be seen that the DC level changes by R5XI2/2 depending on whether the switch S1.32 is turned on or off. For this reason, when connecting in multiple stages, it is necessary to ensure a large operable range for the next stage, making it difficult to operate at low voltages.

Furthermore, since the collector-emitter voltage VCE of the transistors Qi, Ql, Q3, and Q4 changes depending on whether the switches S1 and S2 are turned on or off, there is a drawback that the high frequency characteristics change.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a differential amplifier that can reduce fluctuations in the output DC level.

[Means for Solving the Problems] The present invention for achieving the above object has first and second input terminals (1N2) and a base connected to the first input terminal (1N2).
) and a second transistor (Q2) whose base is connected to said second input terminal (2).
a transistor (Q2), and first and second resistors (R1>(R2)) connected between the emitters of the first and second transistors (Ql>(Ql) and connected in series with each other; The first and second resistors (R
1) A first current source (CS1) connected to the connection midpoint of (R2>), a third transistor (Q3) whose base is connected to the first input terminal (1), and a third transistor (Q3) whose base is connected to the first input terminal (1); a fourth transistor (Q4) connected to the second input terminal (2) and the emitters of the third and fourth transistors (Q3) (Q4) and connected in series with each other; The third and fourth resistors (R3
) (R4) and the third and fourth resistors (R3)
The second current source (R4) is connected to the connection midpoint of (R4)
CS2>, and the emitter is connected to the first transistor (Q2
) is connected to the collector of the fifth transistor (Q
5), the emitter is connected to the collector of the second transistor (Q2), and the base is connected to the fifth transistor (Q2).
5) is connected to the base of the sixth transistor (Q
6), a seventh transistor (Q2) whose emitter is connected to the collector of the third transistor (Q3) and whose collector is connected to the collector of the fifth transistor (Q5); 4 transistors (
an eighth transistor (Q8) whose collector is connected to the collector of the sixth transistor (Q6) and whose base is connected to the base of the seventh transistor (Q2); The emitter is the seventh
a ninth transistor (Q9) to which the emitter of the transistor (Q2) is connected; the emitter is connected to the emitter of the eighth transistor (Q8), and the base is connected to the base of the ninth transistor (Q9). a tenth transistor (Q10) whose collector is connected to the collector of the ninth transistor (Q9), and the ninth and tenth transistors (Q9') (Q10
) and the fifth and sixth transistors (C5) respectively connected to the bases of the control terminals (C1) and the fifth and sixth transistors (C5).
(Q6); and bias means (8) for applying bias to the bases of the seventh and eighth transistors (Q?> (C8). an eleventh transistor (Q11) whose emitter is connected to the collector of the fifth transistor (C5); an eleventh transistor (Q11) whose emitter is connected to the collector of the sixth transistor (C6) and whose base is connected to the collector of the sixth transistor (C6); a twelfth transistor <C12) connected to the base of the transistor Q11) and the eleventh and twelfth transistors (Q11) (C1
2) bias means (9) for applying a bias to the bases of the eleventh transistor (Q 11
) and a fifth resistor (R5) connected between the collector of the transistor (R5) and the power supply terminal (5);
a sixth resistor (R6) connected between the collector of C12) and the power supply terminal (5);
5) and the collector of the eleventh transistor (Q11), the first output terminal (3) is disconnected between the sixth resistor (R6) and the collector of the twelfth transistor (C1
2), and the emitter is connected between the collector of the ninth and tenth transistors (Q9) (QIO) via the seventh resistor (R7).
), the collector of which is connected to the collector of the eleventh transistor (Q11>);
transistor (C13), and the emitter is an eighth resistor (C13).
The ninth and tenth transistors (Q
9) (Q10), the collector is connected to the collector of the twelfth transistor (C12), and the base is connected to the collector of the thirteenth transistor (C13).
The fourteenth L transistor (C
14) and the thirteenth and fourteenth transistors (C1
3) Bias means (10) for applying a bias to the bases of (C14), respectively, and the seventh and eighth transistors (Q?) (C8) are turned on and off by switching the voltage of the control terminal (C1). The present invention relates to a differential amplifier characterized in that it is configured to be turned off and its gain is switched.

[Function] Also in the circuit of the present invention, by controlling the seventh and eighth transistors Q7 and C8 to turn on and off, the operation becomes equivalent to turning on and off the conventional switches 31 and S2 shown in FIG. .

Further, the thirteenth and fourteenth transistors Q13 and C14 are connected to the fifth and sixth resistors R5 and R6 and the ninth resistor as load resistances.
and the tenth transistors Q9 and Q10, the second current source C
32 current flows through the fifth and sixth resistors R5 as load resistances.
, R6, and fluctuations in the DC level are suppressed.

[Embodiment] Next, a differential amplifier having a gain switching circuit according to an embodiment of the present invention will be described with reference to FIG.

FIG. 2 shows a portion equivalent to the conventional circuit shown in FIG. 3 extracted from the differential amplifier shown in FIG. 1.

In the circuit shown in FIG. 2, transistors Q5 to Q10 are provided in order to perform an equivalent function to the switching by switches S1 and S2 in the conventional circuit shown in FIG. That is, the first and second input terminals 1.2 for providing the differential input ΔVin, the first and second output terminals 3.4, and the first
~Fourth transistors Q1 to Q4, first to sixth resistors R1 to R6, and first and second constant current sources C31 and C82
In addition to the power supply terminal 5.6 for providing constant voltage, the fifth
~10th transistors Q5~QIO and first and second control terminals CI and C2 are provided.

To explain in detail the connection relationship between each part, the bases of the first and second transistors Ql and C2 are connected to the first and second input terminals 1.2, respectively. The first and second resistors R1 and R2 are connected to the first and second transistors Q1,
They are connected between the emitters of Q2 and in series with each other. A first constant current source C for flowing the first current 11
3I is connected between the connection midpoint of the first and second resistors R1 and R2 and the ground (common power supply line). Third
The bases of the fourth transistors Q3 and Q4 are connected to the first and second input terminals 1.2, respectively. The third and fourth resistors R3 and R4 are connected between the emitters of the third and fourth transistors Q3 and Q4, and are connected in series with each other. a second current I2 for flowing the second current I2;
A constant current source C32 is connected between the connection midpoint of the third and fourth resistors R3 and R4 and the ground.

The emitters of the fifth and sixth transistors Q5 and Q6 constituting the cascode amplifier are connected to the collectors of the first and second transistors Q1 and Q2, respectively. The emitters of the seventh and eighth transistors Q7 and Q8 for forming the cascode amplifier are the third and fourth transistors.
are connected to the collectors of transistors Q3 and Q4, respectively, and their respective collectors are connected to the collectors of fifth and sixth transistors Q5 and Q6. The emitters of the ninth and tenth transistors Q9 and Q10 are the seventh
and the emitters of the eighth transistors Q7 and Q8, each collector is connected to the power supply terminal 6, and each base is connected to the first control terminal C1. The bases of the fifth and sixth transistors Q5 and Q6 are connected to the second control terminal c2 via the line 7 as bias means, and the bases of the seventh and eighth transistors Q7 and Q8 are connected to the line 7 as bias means. 8 to the second control terminal C2. Fifth and sixth resistors R5 and R6 as load resistors
are connected between the power supply terminal 5 that provides a constant voltage Vcc and the collectors of the fifth and sixth transistors Q5 and Q6, respectively, and the first and second output terminals 3.4 for obtaining the differential output Δout are It is connected between the fifth and sixth resistors R5 and R6 and the fifth and sixth transistors Q5 and Q6, respectively.

In the conventional example shown in FIG. 2, Q1 to Q10 are NPN.
type transistor, and R1=R2, R3=R4,
R5=R6 is set.

In the circuit shown in FIG. 2, when the voltage of the first control terminal C1 is set higher than the voltage of the second control terminal 02, the ninth and tenth transistors Q9 and Q1
0 is turned on, and on the contrary the seventh and eighth transistors Q
7, Q8 is turned off, and a state similar to that obtained when switch 81.32 is turned off in the conventional circuit of FIG. 3 is obtained. Conversely, when the voltage of the first control terminal C1 is lowered than the voltage of the second control terminal C2, the seventh and eighth 1-transistors Q7 and Q8 are turned on, and the voltage of the second constant current source C32 is turned on. 5th and 6th current as load resistance
The current flows through the resistors rt5 and R6. As a result, the circuit of FIG. 2 operates in the same manner as the circuit of FIG. 3.

FIG. 1 shows a differential amplifier that reduces changes in output DC voltage due to gain switching. The circuit of FIG. Transistors Q11, Q12, Q13, Q14 and seventh and eighth resistors R7 and R8 are added. Therefore, the parts in FIG. 1 that are substantially the same as those in FIG. 2 are given the same reference numerals, and the explanation thereof will be omitted. Added 11th and 1st
The emitters of the second transistors Q11 and Q12 are connected to the collectors of the fifth and sixth transistors Q5 and Q6, respectively, and the collectors are connected to the fifth and sixth resistors R5 and R6, respectively. Seventh and eighth resistors R7 and R8 are connected between the emitters of the thirteenth and fourteenth transistors Q13 and Q14, and the midpoint of their connection is connected to the collectors of the ninth and tenth transistors Q9 and Q10. has been done. thirteenth and fourteenth transistors Q13,
The collector of Q14 is connected to fifth and sixth resistors R5 and R6. Eleventh and twelfth transistors Q11
, Q12 is connected to a bias voltage V lower than the voltage Vcc of the power supply terminal 5 via a line 9 as a bias means.
It is connected to a bias power supply terminal 6a for supplying B. Thirteenth and fourteenth transistors Q13, Q14
The base of is connected to a bias power supply terminal 6a via a line 10 as bias means.

The first and second output terminals 3.4 are connected to the collectors of the eleventh and twelfth transistors Q11, C12, respectively.

In the circuit shown in FIG. 1, when a voltage higher than the second control terminal C2 is applied to the first control terminal C1, the seventh and eighth transistors Q7 and C8 are turned off as in the circuit shown in FIG. controlled by the switch S in FIG.
The gain is the same as when 1.32 is turned off. At this time, the ninth and tenth transistors Q9 and QIO are turned on, but since their collectors are connected to each other, the differential signals flowing through the transistors Q9 and Q10 are combined, and the signal components are canceled out. Therefore, there is only a DC component. This DC current is divided between the thirteenth and fourteenth transistors Q13 and C14 and the seventh and eighth resistors R7 and R8, and flows to the fifth and sixth resistors R5 and R6. 7th
and the current I flowing into the connection midpoint of the eighth resistors R7 and R8.
2, the current flowing through the seventh and eighth resistors R7 and R8, that is, the thirteenth and fourteenth transistors Q13 and C14.
The emitter current of the 13th and 1st
If the base-emitter voltages of the transistors Q13 and C14 of No. 4 are V BE13 and V BE44, the ratio between 113 and 114 is given by the following equation.

I 13/I 14= (VBE14-VBE13)
/ (R13x 114) +R14/R13...
...(5) Here, V 8E13 = V 8E14,
If R13=R14, I 13/I 14=
1, and 113 and 114 are equal. I 13+
Since I 14 = ■2, 113 and 114 are both I2/
2, and I2 is divided into 1/2. This current 113
．． 114 flows through the fifth and sixth resistors R5 and Rθ, respectively.

When the seventh and eighth transistors Q7 and C8 are on, the current I2 of the second constant current source C32 is divided into I2/2 by the third and fourth transistors Q3 and C4, and
and flows through the sixth resistors R5 and R6.

As a result, the current I2 of the second constant current source cs2 is divided in half and flows to the fifth and sixth resistors R5 and R6, regardless of whether the seventh and eighth transistors Q7 and C8 are on or off. Therefore, there is no change in the output DC level.

Note that, if necessary, between the fifth and sixth resistors R5 and R6 and the eleventh and twelfth transistors Q11 and C12,
and the fifth and sixth resistors R5 and R6 and the thirteenth and fourteenth resistors
An amplifier may be added between the transistors Q13 and C14, and the eleventh and twelfth transistors Q1
1. The bias voltage applied to the base of C12 and the bias voltage applied to the bases of the 13th and 14th transistors Q13 and C14 may be set to different values, and the base bias of the 5th and 6th transistors Q5 and C6 may be set to different values. The voltage and the base bias voltages of the seventh and eighth transistors Q7 and C8 may be set to different values, and the first and second constant current sources C81 and C82 may be connected to a negative power supply.

[Effects of the Invention] As described above, according to the present invention, changes in the output DC level are reduced when switching the gain.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a differential amplifier according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing substantially the same part as FIG. 3 in the circuit of FIG. 1, and FIG. FIG. 2 is a circuit diagram showing a differential amplifier having a gain switching circuit. 1.2...Input terminal, 3.4...Output terminal, 5...
・Power supply terminal, 6a...bias power supply terminal, Q1~Q1
4...Transistor, C8I...First constant current source,
C32...Second constant current source, R1-R8...Resistor,
C1...first control terminal, C2...second control terminal.

Claims (1)

[Claims] First and second input terminals (1) (2); a first transistor (Q1) whose base is connected to said first input terminal (1); and whose base is connected to said first input terminal (1); A second transistor (Q2) connected to the second input terminal (2) and the emitters of the first and second transistors (Q1) (Q2) and connected in series with each other. a first and second resistor (R1) (R2); a first current source (CS1) connected to a midpoint between the first and second resistors (R1) and (R2); a third transistor (Q3) connected to the first input terminal (1); a fourth transistor (Q4) whose base is connected to the second input terminal (2); and third and fourth resistors (R3) (R4) connected between the emitters of the fourth transistors (Q3) (Q4) and connected in series with each other; and the third and fourth resistors (R3). ) (R4); a fifth transistor (Q5) whose emitter is connected to the collector of the first transistor (Q1); a sixth transistor (Q6) whose base is connected to the collector of the second transistor (Q2) and whose base is connected to the base of the fifth transistor (Q5); and whose emitter is connected to the third transistor (Q3). is connected to the collector of the fifth transistor (Q5), and the collector is connected to the collector of the fifth transistor (Q5).
) is connected to the collector of the seventh transistor (Q
7), the emitter is connected to the collector of the fourth transistor (Q4), and the collector is connected to the collector of the sixth transistor (Q6).
an eighth transistor (Q8) whose base is connected to the collector of the seventh transistor (Q7) and whose emitter is connected to the collector of the seventh transistor (Q7);
The emitter of the ninth transistor (Q7) is connected to the emitter of the ninth transistor (Q7).
9), the emitter of which is connected to the emitter of the eighth transistor (Q8), and the base of which is connected to the emitter of the ninth transistor (Q9).
a tenth transistor (Q10) whose collector is connected to the base of the ninth transistor (Q9) and the bases of the ninth and tenth transistors (Q9) (Q10), respectively. bias means (for applying bias to the connected control terminal (C1) and the bases of the fifth and sixth transistors (Q5) and (Q6), respectively;
7) and bias means (for applying bias to the bases of the seventh and eighth transistors (Q7) and (Q8), respectively);
8); an eleventh transistor (Q11) whose emitter is connected to the collector of the fifth transistor (Q5); an eleventh transistor (Q11) whose emitter is connected to the collector of the sixth transistor (Q6) and whose base is connected to the collector of the sixth transistor (Q6); 11 transistors (Q1
1) connected to the base of the twelfth transistor (
Q12) and the eleventh and twelfth transistors (Q11) (Q1
2) bias means (9) for applying a bias to the bases of the transistors 1 and 2), and a fifth resistor (R5) connected between the collector of the eleventh transistor (Q11) and the power supply terminal (5).
and a sixth resistor (R) connected between the collector of the twelfth transistor (Q12) and the power supply terminal (5).
6), the fifth resistor (Q5) and the eleventh transistor (
the first output terminal (3) connected between the collector of the transistor (Q11), the sixth resistor (R6) and the twelfth transistor (
A second output terminal (4) connected between the collector of the transistor Q12) and the collector of the ninth and tenth transistors (Q9) (Q10) whose emitters are connected through a seventh resistor (R7). , and the collector is connected to the eleventh transistor (Q11
) is connected to the collector of the thirteenth transistor (
Q13), the emitter of which is connected to the collectors of the ninth and tenth transistors (Q9) (Q10) via an eighth resistor (R8), and the collector of which is connected to the collector of the twelfth transistor (Q12).
) and whose base is connected to the base of the thirteenth transistor (Q13); and the thirteenth and fourteenth transistors (Q13) (Q1
bias means (10) for applying a bias to the bases of the seventh and eighth transistors (Q7) (Q) by switching the voltage of the control terminal (C1).
8) A differential amplifier characterized in that the differential amplifier is configured such that the amplifier is controlled on and off and the gain is switched.