JP2011086978A - Receiving circuit, signal transmission circuit, integrated circuit, and signal transmission method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a receiving circuit capable of accurately detecting a signal pattern of a data signal on a reception side. <P>SOLUTION: The receiving circuit 12 receives a first data signal S<SB>DATA</SB>and a reference signal S<SB>FIX</SB>used to set a clamp voltage for clamping a detection signal for detecting the first data signal. The receiving circuit 12 includes an amplitude investigation circuit 13 which detects an H-level voltage and an L-level voltage of the reference signal S<SB>FIX</SB>, a clamp circuit 14 which clamps an H-level voltage and an L-level voltage of the detection signal to the clamp voltage, a control circuit 15 which sets the clamp voltage for the clamp circuit 14 based upon the H-level voltage and L-level voltage of the reference signal detected by the amplitude investigation circuit 13, and a data signal generation circuit which generates a second data signal based upon the detection signal clamped by the clamp circuit 14. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a signal transmission circuit that controls signal transmission between LSIs (Large Scale Integration).

  Conventionally, a signal transmission circuit that includes a transmission circuit that transmits a data signal and a reception circuit that receives the data signal and controls signal transmission between LSIs is known.

  In Patent Document 1, in the transmission circuit, when the voltage of the output terminal is equal to or lower than the power supply voltage, the power supply voltage is supplied to the output circuit connected to the output terminal, and when the voltage of the output terminal is equal to or higher than the power supply voltage, A circuit for stopping the supply of the power supply voltage to the output circuit is disclosed. Thus, by keeping the voltage at the output terminal of the transmission circuit constant, the influence on the voltage at the output terminal due to reflection noise generated in the transmission path is suppressed.

  In Patent Document 2, a signal having a reference amplitude is input to an output buffer of a transmission circuit that outputs a signal to a transmission path, and the amplitude of the signal received by the reception circuit is compared with a predetermined reference value. It is disclosed that the amplitude of the signal output from the output buffer circuit of the transmission circuit is adjusted according to the determination result. In this way, the constant current value supplied to the output buffer of the transmission circuit is feedback-controlled, and the amplitude of the signal output from the output buffer is adjusted to the minimum necessary value, thereby reducing the power consumption in the transmission circuit. I am trying.

Japanese Patent Laid-Open No. 9-246940 JP 2008-227696 A

In the signal transmission circuit according to Patent Document 1, since the frequency of the signal transmitted from the transmission circuit differs depending on the signal pattern to be transmitted, the L level and H level of the signal reaching the reception side for each signal pattern are different. Different. This is shown in FIG. Specifically, in the signal pattern A having a low frequency, the amplitude of the received signal (S _C , S _T ) increases, and in the signal pattern B having a high frequency, the received signal (S _C , S _T ) The amplitude is reduced.

Here, as shown in FIG. 7, when the transmitted signal pattern transitions from the signal pattern A having a low frequency to the signal pattern B having a high frequency, the amplitude of the signal pattern A having a low frequency is large in the receiving circuit. _Therefore , when transitioning to the next signal pattern B, the amplitude of the signal pattern B does not reach the thresholds V _thL and V _thH for detecting the L level and the H level, and the signal pattern B is accurately detected. I can't.

Further, when the technique disclosed in Patent Document 2 is applied to such a problem, in order to ensure the amplitude of the signal pattern B, the transmission circuit reduces the amplitude of the previous signal pattern A. It is necessary to adjust the amplitude of the output signal to be small. However, when the amplitude of the signal pattern A is reduced, the potentials at both ends of the signal pattern A reach the thresholds V _thL and V _thH for detecting the L level and the H level as shown in FIG. This time, the signal pattern A cannot be accurately detected.

  The present invention has been made for such a problem, and even when a data signal transmitted from the transmission side includes different frequencies, the signal pattern can be accurately detected on the reception side. An object is to provide a receiving circuit.

  One aspect of the receiving circuit according to the present invention is a receiving circuit that receives a first data signal and a reference signal used to set a clamp voltage for clamping a detection signal for detecting the first data signal. And an amplitude check circuit for detecting the H level voltage and the L level voltage of the reference signal, a clamp circuit for clamping the H level voltage and the L level voltage of the detection signal to the clamp voltage, and the amplitude check circuit. A control circuit for setting the clamp voltage for the clamp circuit based on the H level voltage and the L level voltage of the reference signal; and a second data signal based on the detection signal clamped by the clamp circuit. It has a data signal generation circuit to generate.

  According to another aspect of the signal transmission method of the present invention, a reference used for setting a clamp voltage for clamping a first data signal and a detection signal for detecting the first data signal on the reception side from the transmission side. A signal is received, and an H level voltage and an L level voltage of the reference signal are detected on the reception side, and the detection signal is detected based on the detected H level voltage and L level voltage of the reference signal on the reception side. The H level voltage and the L level voltage are clamped to the clamp voltage, and the second data signal is generated from the detection signal clamped to the clamp voltage on the receiving side.

  According to one aspect of the receiving circuit of the present invention, the signal pattern of the data signal can be accurately detected regardless of the frequency of the data signal transmitted from the transmitting side.

It is a figure which shows the structural example of the receiver circuit concerning embodiment. It is a figure which shows the waveform of the detection signal clamped in the receiver circuit concerning embodiment. It is a figure which shows the structural example of the signal transmission circuit containing the receiving circuit concerning this Embodiment concerning embodiment. It is a figure which shows the waveform of the reference signal _SFIX received with the receiving circuit concerning embodiment. FIG. 6 is a diagram illustrating a determination result signal output from the amplitude check circuit to the control circuit when a reference signal S _FIX is input in the receiving circuit according to the embodiment. It is a figure which shows the waveform of the 1st detection signal clamped in the receiving circuit concerning embodiment, and a 2nd detection signal. It is a figure which shows the structural example of the data signal generation circuit contained in the receiving circuit which concerns on embodiment. In the circuit concerning patent document 1, it is a figure which shows the waveform of the data signal output to a receiving circuit from a transmission circuit via a transmission line. In the circuit concerning patent document 2, it is a figure which shows the waveform of the data signal output to a receiving circuit from a transmission circuit via a transmission line.

Embodiment.
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a diagram illustrating a configuration example of a receiving circuit 12 according to an embodiment of the present invention. As shown in FIG. 1, the receiving circuit 12 receives a first data signal _SDATA from a transmitting circuit (not shown), and receives a second data based on a detection signal appearing at a detection point A to which the first data signal _SDATA is input. A circuit that generates a data signal.

In addition to the first data signal S _DATA , a reference signal S _FIX used for setting a clamp voltage for clamping the detection signal is transmitted from a transmission circuit (not shown). The reference signal S _FIX is input to the receiving circuit 12 via the detection point A in the same manner as the first data signal S _DATA . For example, the reference signal _SFIX can be a pulse signal having the minimum pulse width (fastest frequency) of the first data signal. Specifically, the reference signal _SFIX can be configured as a one-pulse signal.

The reception circuit 12 determines an amplitude investigation circuit 13 that _examines an H level voltage and an L level voltage of the reference signal S _FIX detected at the detection point A, and an H level voltage and an L level voltage of the detection signal that appears at the detection point A. And a clamp voltage for clamping the signal at the detection point A to the clamp circuit 14 based on the H level voltage and the L level voltage of the reference signal S _FIX detected by the amplitude investigation circuit 13. On the other hand, the control circuit 15 has a data signal generation circuit 20 that generates a second data signal from the detection signal clamped by the control circuit 15 and the clamp circuit 14.

Here, the clamp voltage is _{equal to} or higher than thresholds V _thH and V _thL at which the voltage level of the data signal can be detected at the current detection timing for detecting the signal pattern of the detection signal, and the detection timing of the next detection signal. _Are set to be equal to or lower than the maximum voltage that can be _shifted to threshold values V _thH and V _thL of the signal pattern opposite to the current one. Specifically, this clamp voltage can be set to the H level voltage and the L level voltage of the reference signal S _FIX detected by the amplitude investigation circuit 13.

The amplitude investigation circuit 13 and the clamp circuit 14 are selectively connected to the detection point A by the switch SW. In the period in which the reference signal S _FIX is transmitted from the transmission circuit, the amplitude investigation circuit 13 is connected to the detection point A, and in the period in which the first data signal S _DATA is transmitted from the transmission circuit, the clamp circuit 14 is detected. Connected to A.

In the receiving circuit 12 configured in this way, the H level voltage and L of the detection signal (the voltage at the detection point A) based on the H level voltage and the L level voltage of the reference signal S _FIX detected by the amplitude investigation circuit 13. By clamping the level voltage, the amplitude of the detection point A can be kept within a certain range regardless of the frequency of the received data signal _SDATA . This effect will be specifically described with reference to FIG. FIG. 2 is a diagram illustrating a signal pattern of data transmitted from the transmission circuit 11 to the reception circuit 12 and a waveform of a detection signal (voltage at the detection point A) clamped on the reception circuit 12 side.

As shown in FIG. 2, even when the signal pattern of the data signal S _DATA transitions from the low-level signal pattern A at the low frequency to the high-frequency signal pattern B at the high frequency, the detection in the reception circuit 12 is performed. The amplitude of the signal does not exceed the voltage clamped by the clamp circuit 14. Thereby, even when the signal pattern of the data signal S _DATA changes from the signal pattern A to the signal pattern B, the voltage of the detection signal corresponds to the signal pattern B from the L level voltage corresponding to the signal pattern A. The transition can be instantaneously made up to the detection timing for detecting the signal level of the next detection signal up to the H level voltage. Thereby, the detection signal corresponding to the pattern B can be detected accurately.

  Further, in this embodiment, the detection signal of the reception circuit 12 is clamped, and the amplitude of the signal transmitted from the transmission circuit is not adjusted. Therefore, even when the detection signal corresponding to the pattern A is clamped to detect the pattern B, both ends of the pattern A in the detection signal have a sufficient amplitude for detecting the L level of the signal pattern A. Can be secured. Thereby, the detection signal corresponding to the pattern A can also be detected accurately.

FIG. 3 is a diagram illustrating a configuration example of a signal transmission circuit including the receiving circuit illustrated in FIG. The signal transmission circuit 100 includes a transmission circuit 11 that transmits a data signal S _DATA and a reference signal S _FIX to the reception circuit 12 in addition to the reception circuit 12 illustrated in FIG. Note that the receiving circuit 12 shown in FIG. 3 shows the circuit configuration shown in FIG. 1 in more detail.

Signal transmitted from the transmitting circuit 11 shown in FIG. 3, the data signal S _DATA and the reference signal S with the first signal S _T having a signal pattern based on _FIX, second having a complementary signal pattern and the first signal It is transmitted as complementary signals consisting of signal S _C. In the receiving circuit 12, the reference signal S _FIX L level voltage detected from the first detection point A1 for detecting the signal pattern of the first signal S _T, detects the H level voltage, appearing at the first detection point A1 first Set the clamp voltage of 1 detection signal.

Similarly, the receiving circuit 12, the reference signal S _FIX L level voltage detected from the second detection point A2 for detecting the signal pattern of the second signal S _C, detects the H level voltage, the second detection point A2 The clamp voltage of the second detection signal that appears is set. The data signal generation circuit 20 generates a second data signal based on the clamped first detection signal at the first detection point A1 and the clamped second detection point A2. Hereinafter, detailed configurations of the transmission circuit 11 and the reception circuit 12 will be described.

The transmission circuit 11 includes a reference signal generation circuit 16 that generates a reference signal S _FIX , a data register 17 that holds the data signal S _DATA, a reference signal S _FIX that is output from the reference signal generation circuit 16, and an output from the data register 17. A selection circuit 18 that switches and outputs the data signal S _DATA to be output, and a transmission circuit 19 that transmits the output of the selection circuit 18 to the reception circuit 12.

The reference signal generation circuit 16 can be constituted by a one-pulse generation circuit. The transmission circuit 19, a reference signal _{S FIX} and data signal _{S DATA} outputted from the selection circuit 18, is transmitted to a transmission line as a complementary signal. That is, the transmission circuit 19, a reference signal _{S FIX} and the data signal _{S DATA,} and a second signal _{S T} having a signal pattern based on the reference signal _{S FIX} and the data signal _{S DATA,} a complementary signal pattern and the first signal and it sends to the transmission line as a first signal S _C with.

On the other hand, the receiving circuit 12, the first signal clamp voltage setting circuit 121, the second signal clamp voltage setting circuit 122, and a first signal clamp voltage setting circuit 121 receives the second signal _{S T} for receiving a first signal _{S C} And a data signal generation circuit 20 that generates a second data signal based on the first detection signal clamped by the second detection signal and the second detection signal clamped by the second signal clamp voltage setting circuit 122.

The first signal clamp voltage setting circuit 121 and the second signal clamp voltage setting circuit 122 have substantially the same configuration. First signal clamp voltage setting circuit 121, the H level voltage and L level voltage of the reference signal _{S FIX} input as the first signal _{S C} is detected at the first detection point A1, the detected reference signal _{S FIX} of H based on the level voltage and L level voltage to clamp the first detection point A1 of the first signal S _C comprising data signal S _dATA is input to a predetermined clamp voltage.

Similarly, the second signal clamp voltage setting circuit 122 detects the H level voltage and L level voltage of the reference signal S _FIX input as the second signal S _T at the second detection point A2. Then, based on the H-level voltage and L level voltage of the detected reference signal S _FIX, clamping the second detection point A2 of the second signal S _C comprising data signal S _DATA is input to a predetermined clamp voltage.

Hereinafter, a more specific configuration of the clamp voltage setting circuits 121 and 122 will be described using the first signal clamp voltage setting circuit 121 as an example. The first signal clamp voltage setting circuit 121 includes an amplitude investigation circuit 131 that detects the amplitude of the reference signal _SFIX , a clamp circuit 141 that clamps the amplitude of the data signal, and a control circuit 151. Amplitude survey circuit 131, the reference signal received _{S FIX} and a plurality of reference voltages _{V ref1,} V ref2, _..., comparator circuit C1, C2 to be compared with the _{V refn,} ..., and Cn, the comparison of the comparator circuit C1~Cn It has registers F1, F2,..., Fn that hold the results. Determination result signals S 1, S 2,..., Sn, which are outputs of the comparison circuit, are output to the control circuit 151.

The clamp circuit 141 has a first variable voltage V _cL and a second variable voltage V _cH for clamping (fixing) the L level and the H level of the first detection point A1. The voltage values of the first variable voltage V _cL and the second variable voltage V _cH are set by the control circuit 151. Similarly, the second signal clamp voltage setting circuit 122 that receives the second signal is also provided with an amplitude circuit and a clamp circuit having the same circuit configuration as the amplitude investigation circuit 131, the clamp circuit 141, and the control circuit 151 ( Not shown).

  The data signal generation circuit 20 can be configured as a differential amplifier in which the first detection point A1 is connected to one input and the second detection point A2 is connected to the other input. The data signal generation circuit 20 generates a second data signal by amplifying and outputting the voltage difference between the first detection point A1 and the second detection point A2.

Next, the operation of the signal transmission circuit 100 configured as described above will be described with reference to FIG. First, in the transmission circuit 11, the selection circuit 18 selects the output of the reference signal generation circuit 16. As a result, the reference signal S _FIX is transmitted from the output circuit 19 to the receiving circuit 12 via the transmission path. Here, the transmission timing of the reference signal S _FIX from the transmission circuit 11 can be configured to be transmitted during an initial setting period determined in advance between the transmission circuit 11 and the reception circuit 12, for example.

The reference signal _SFIX transmitted from the transmission circuit 11 is shown in FIG. Specifically, the reference signal _SFIX can be configured as a one-pulse signal as shown in FIG. In the receiving circuit 12, during the period in which the reference signal _SFIX is transmitted from the transmitting circuit 11, the amplitude examining circuit 131 is connected to the first detection point A1 by the switch SW. The reference voltages V _ref1 , V _ref2 ,..., V _refn and the received reference signal S _FIX are input to the plurality of comparison circuits C1, C2 _,.

Comparator circuit C1, C2, ..., Cn is the first signal _{S C} that is received with the reference voltage _{V ref} is compared with the amplitude, the H level voltage VsigH and L-level voltage _{V Fix L} of a reference signal _{S FIX} received To detect. The determination result signals S1, S2,..., Sn output from the comparison circuits C1, C2,..., Cn are output to the control circuit 151. FIG. 5 shows a specific example of determination result signals S1, S2,..., Sn output from the comparison circuits C1, C2,.

Determination result signal S1, S2, ..., to Sn, when the reference voltage is _V ref3 _{~V ref7} the pattern appeared in the "0101", the H level voltage and L level voltage of the reference voltage, respectively _V FIXH _{= V ref2} , V _FIXL = V _ref7 . Incidentally, also in the second signal clamp voltage setting circuit 122, and the H-level voltage _{V Fix H} of the transmitted reference signal _{S FIX} by the second signal _{S T,} L level voltage _{V Fix L} is detected.

The control circuit 151 sets a clamp voltage based on the H level voltage V _FIXH and the L level voltage V _FIXL of the reference signal S _FIX detected by the amplitude investigation circuit 131, and the first variable voltage V _cL of the clamp circuit 141, And the second variable voltage V _cH is adjusted. Specifically, the control circuit 151 can set the clamp voltage to the H level voltage V _FIXH and the L level voltage V _FIXL of the reference signal S _FIX .

That is, assuming that the signal amplitude of the reference signal S _FIX detected by the amplitude examining circuit 131 is V _FIXH = V _ref2 and V _FIXL = V _ref7 as shown in FIG. The variable voltage V _cH is adjusted so that the H level of V _DATA is clamped (fixed) to V _ref2 , and the variable voltage V _cL is adjusted so that the L level is clamped to V _ref7 .

  The data signal generation circuit 20 includes the first detection signal at the first detection point A1 clamped by the first signal clamp voltage setting circuit 121 and the second detection point A2 clamped by the second signal clamp voltage setting circuit 122. The second data signal is generated by amplifying the difference between the two detection signals.

  FIG. 6A is a diagram illustrating waveforms of the first detection signal and the second detection signal clamped in the reception circuit 12. The upper solid line in FIG. 6A indicates the waveform of the clamped first detection signal, and the broken line indicates the waveform of the clamped second detection signal. The clamped first detection signal and second detection signal appear symmetrically about the common voltage Vcom. As shown in FIG. 6B, the common voltage Vcom is supplied to the first detection point A1 via the resistor R1, and is also supplied to the second detection point A2 via the resistor R2. The relationship between the resistors R1 and R2 is R1 = R2, and R1 + R2 is set to the differential characteristic impedance of the transmission path between the transmission circuit 11 and the reception circuit 12.

In the circuit according to the background art, since the frequency of the signal pattern included in the data signal is different, the L level and the H level that are reached for each signal pattern are different, and the transmission waveform is disturbed. By clamping the detection signal based on the reference signal S _FIX for setting the clamp voltage on the receiving circuit 12 side, the signal amplitude L at the first detection point A1 and the second detection point A2 as shown in FIG. 6A. The level and H level values can be clamped (fixed) to values at which the fastest signal can be detected. As a result, regardless of the frequency of the data signal pattern, the L level voltage and the H level voltage are constant, so that the transmission waveform can be improved and good signal transmission is possible.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

For example, in the above-described embodiment, the first signal S _T which is a complementary _signal, but had set the clamp voltage to each of the second signal S _C, detecting the amplitude of one of the reference signal S _FIX And based on this signal amplitude, you may set the clamp voltage of 1st detection point A1 and 2nd detection point to the same value. Thereby, the circuit configuration can be reduced as compared with the above-described embodiment.

  Note that the signal transmission circuit and the reception circuit described above can be implemented by being incorporated into an integrated circuit (LSI).

DESCRIPTION OF SYMBOLS 11 Transmission circuit 12 Reception circuit 13, 131 Amplitude investigation circuit 14, 141 Clamp circuit 15, 151 Control circuit 16 Reference signal generation circuit 17 Data register 18 Selection circuit 19 Transmission circuit 20 Data signal generation circuit 100 Signal transmission circuit 121 1st signal clamp Voltage setting circuit 122 Second signal clamp voltage setting circuit

Claims (17)

A receiving circuit for receiving a first data signal and a reference signal used for setting a clamp voltage for clamping a detection signal for detecting the first data signal;
An amplitude investigation circuit for detecting an H level voltage and an L level voltage of the reference signal;
A clamp circuit for clamping the H level voltage and the L level voltage of the detection signal to the clamp voltage;
A control circuit for setting the clamp voltage for the clamp circuit based on the H level voltage and the L level voltage of the reference signal detected by the amplitude investigation circuit;
A receiving circuit including a data signal generation circuit that generates a second data signal based on the detection signal clamped by the clamp circuit. The data signal and the reference signal are received as a first signal having a signal pattern based on the data signal and the reference signal, and a second signal having a signal pattern complementary to the first signal,
The amplitude investigation circuit detects an H level voltage and an L level voltage of the reference signal for each of the first signal and the second signal,
The clamp circuit clamps a first detection signal for detecting the first signal to a predetermined first clamp voltage, and clamps a second detection signal for detecting the second signal to a predetermined second clamp voltage,
The control circuit sets the first clamp voltage and the second clamp voltage based on the H level voltage and the L level voltage of the reference signal detected for each of the first signal and the second signal. The receiving circuit according to claim 1, wherein the receiving circuit is set for a clamp circuit.   The receiving circuit according to claim 1, wherein the reference signal is a pulse signal having a minimum pulse width of the first data signal.   The receiving circuit according to claim 1, wherein the reference signal is a one-pulse signal. 5. The receiving circuit according to claim 1, wherein the control circuit sets the clamp voltage to an H level voltage and an L level voltage of the reference signal detected by the amplitude check circuit. 6. The amplitude investigation circuit and the clamp circuit are selectively connected to detection points for detecting the data signal and the reference signal,
While the receiving circuit is receiving the reference signal, the amplitude investigation circuit is connected to the detection point,
The receiving circuit according to claim 1, wherein the clamp circuit is connected to the detection point while the receiving circuit is receiving the data signal. The amplitude survey circuit has a plurality of comparators to which a reference voltage is input on one side and the reference signal is input on the other side,
The receiving circuit according to claim 1, wherein the control circuit sets the clamp voltage based on determination results of a plurality of the comparators. The clamp circuit is
A first variable power supply that defines an H level of the clamp voltage; a first diode having an anode connected to the detection point and a cathode connected to the first variable power supply;
8. The second variable power supply for defining an L level of the clamp voltage, and a second diode having an anode connected to the second variable power supply and a cathode connected to the detection point. The receiving circuit described in 1. The data signal generation circuit includes:
The receiving circuit according to claim 2, further comprising: a comparator in which the first signal is input to a non-inverting input and the second signal is input to an inverting input, and the second data signal is generated based on an output of the comparator. . A transmission circuit for transmitting a first data signal and a reference signal used to set a clamp voltage for clamping a detection signal for detecting the first data signal;
A signal transmission circuit comprising: the receiving circuit according to claim 1. The transmission circuit includes:
A reference signal generation circuit for generating the reference signal;
A data signal holding circuit for holding the data signal;
A selection circuit for switching and outputting the reference signal or the data signal;
The signal transmission circuit according to claim 10, further comprising: an output circuit that outputs the reference signal or the data signal switched by the selection circuit to the reception circuit.   An integrated circuit comprising the signal transmission circuit according to claim 10. Receiving a reference signal used to set a clamp voltage for clamping a first data signal and a detection signal for detecting the first data signal on the receiving side from the transmitting side;
On the receiving side, the H level voltage and the L level voltage of the reference signal are detected,
On the receiving side, based on the detected H level voltage and L level voltage of the reference signal, the H level voltage and L level voltage of the detection signal are clamped to the clamp voltage,
A signal transmission method for generating a second data signal from the detection signal clamped at the clamp voltage on the receiving side. Receiving the data signal and the reference signal by a first signal having a signal pattern based on the data signal and the reference signal and a second signal having a signal pattern complementary to the first signal;
Detecting an H level voltage and an L level voltage of the reference signal for each of the first signal and the second signal;
Based on the H level voltage and the L level voltage of the reference signal detected with respect to the first signal, the first detection signal for detecting the data signal from the first signal is clamped to the first clamp voltage, and Based on the H level voltage and the L level voltage of the reference signal detected with respect to the second signal, a second detection signal for detecting the data signal from the second signal is clamped to a second clamp voltage,
14. The signal transmission method according to claim 13, wherein the second data signal is generated based on the first signal clamped to the first clamp voltage and the second signal clamped to the second clamp voltage. The signal transmission method according to claim 13 or 14, wherein the H level voltage and the L level voltage of the detection signal are set to the H level voltage and the L level voltage of the reference signal.   The signal transmission method according to claim 13, wherein the reference signal is a pulse signal having a minimum pulse width of the first data signal.   The signal transmission method according to claim 13, wherein the reference signal is a one-pulse signal.

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