JP2016005115A - Serial communication circuit and serial communication device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a serial communication circuit dealing with "two channel bidirectional high speed communication" and "one channel high speed communication/low speed command communication".SOLUTION: A serial communication circuit is constituted of a SER 10 having a serializer 11 for converting the inputted data into first data or second data, and an output driver 12 for outputting the first data and second data to a transmission path, a DES 20 having a first receiver 21 for receiving and outputting the first data, a CDR 22 for extracting a clock from the output data of the first receiver 21, and outputting the first data while converting into the format of the inputted data, and a second receiver 23 for receiving and outputting the second data, a changeover switch 30 arranged between the output end 31 of the output driver 12 and the input end 32 of the first receiver 21, and a controller 40 for generating and outputting a control signal for controlling operation of the SER 10, DES 20 and changeover switch 30.

Description

  The present invention relates to a serial communication circuit and a serial communication device including the serial communication circuit.

  In recent years, a high-speed serial interface has been standardized as an interface for high-speed transmission of large-capacity data. Many of the high-speed interfaces have been put into practical use, and are interfaces for bidirectional communication applicable to various devices.

  For example, a case where a bidirectional communication interface is applied to a multifunction peripheral (MFP) will be described as an example. In the MFP, a high-speed serial interface can be used for bus transmission between CPUs and data transmission between an operation unit display and a controller (control unit). A parallel interface using a parallel bus has been used for bus transmission between CPUs of conventional MFPs and data transmission between an operation unit display and a controller.

  When a high-speed serial interface is used for bus transmission between the CPUs of the MFP, the number of cables (number of signal lines) constituting a data transmission bus (transmission path) can be reduced as compared with a parallel interface. Therefore, the cost can be reduced by reducing the number of signal lines.

  The high-speed serial interface can perform high-speed signal bidirectional communication using two channels.

  In addition, using a high-speed serial interface for data transmission between the operation unit display of the MFP and the controller has another advantage. Data transmission between the operation unit display and the controller is image data transmission with a large amount of data in forward communication of normal communication using one channel. If a high-speed serial interface is used here, even high-capacity image data can be transmitted at high speed. Similar to the bus interface between CPUs, the cost can be reduced by reducing the number of signal lines.

  However, data transmission between the operation unit display and the controller requires not only high-speed data transmission but also transmission of a command (control signal) that is low-speed data (low-speed command transmission). Here, the low-speed command transmission is data transmission different from normal communication, and is communication for transmitting a control signal of an IC chip that transmits data during normal communication. The low-speed command transmission transmits relatively low-speed data in both the forward direction and the reverse direction.

  Full-duplex and half-duplex systems are known as communication systems that perform forward / reverse bidirectional data transmission such as low-speed command transmission.

  The full duplex method is a communication method capable of performing real-time simultaneous communication. The full-duplex method includes a method of performing high-speed bidirectional communication using a plurality of channels and a method of providing a dedicated signal line for low-speed command communication. Comparing the half-duplex method and the full-duplex method, which will be described later, the full-duplex method increases the cost because the number of cables (number of signal lines) constituting the transmission path increases.

  The half-duplex method is a communication method in which communication is performed with a time division (time division). The half-duplex method requires control to switch the operation of the transmission / reception unit between “transmission mode” and “reception mode” at an arbitrary timing. This mode switching control enables bidirectional communication on the same cable.

  Further, as a communication circuit that performs different control based on the half-duplex method, a communication circuit that executes a bidirectional communication method in which both a host (for example, a controller) and a target (for example, an operation unit display) acquire a transmission right is known. (For example, refer to Patent Document 1).

  The communication circuit of Patent Document 1 is a communication circuit that can execute bidirectional communication in which both the target and the host acquire the transmission right. The communication circuit of Patent Literature 1 periodically transmits a control signal for changing the target side from the reception state to the transmission state to the host. As a result, the target side becomes the transmitting side, the host side is set in the receiving state, and data transmission is performed from the target to the host. The communication circuit of Patent Document 1 performs normal communication in only one direction and performs half-duplex communication without using a signal line dedicated to control signals.

  In the conventional communication circuit such as Patent Document 1, it is necessary to create a dedicated communication IC chip according to the application. For example, if it is used for CPU bus communication, it must be capable of high-speed bi-directional communication with 2 channels, but if it is used for communication between the operation unit display and the controller, it performs high-speed normal communication with 1 channel. It is necessary to perform another low-speed command communication. That is, the configuration of the communication IC chip used for CPU bus communication is different from that of the communication IC chip used between the operation unit display and the controller. Therefore, in the conventional communication circuit, it is necessary to create a dedicated communication IC chip in accordance with each use of high-speed normal communication and low-speed command communication.

  In order to provide a dedicated signal line for low-speed command communication, it is necessary to provide a terminal for the dedicated signal line on the communication IC chip, and a cable used for the dedicated signal line is also required. Therefore, the conventional communication apparatus is likely to be costly by creating a dedicated IC chip, and further, the cost is increased by increasing the number of chip terminals and signal lines.

  Accordingly, an object of the present invention is to provide a serial communication circuit that can be used by switching between a full-duplex communication method and a half-duplex communication method according to the mode of the serial communication device to be used.

  The present invention provides a SER unit having a serializer that converts input data into first data or second data, and an output driver that outputs the first data and the second data to a transmission line, and the first data. The first receiver that receives and outputs the data, the CDR that extracts the clock from the output data of the first receiver, converts the first data into the format of the input data, and outputs the second data. A DES unit having a second receiver for receiving and outputting; a changeover switch disposed between an output end of the output driver and an input end of the first receiver; the SER unit, the DES unit, and the changeover And a controller that generates and outputs a control signal for controlling the operation of the switch.

  According to the present invention, the full-duplex communication method and the half-duplex communication method can be switched according to the mode of the serial communication device to be used.

It is a block diagram which shows the Example of the serial communication circuit which concerns on this invention. It is an example of the serial communication apparatus comprised by the said serial communication circuit, and functions as a two-way communication system, Comprising: It is a block diagram which shows the example of forward communication. It is an example of the said serial communication apparatus, Comprising: It is a block diagram which shows the example of reverse communication. It is an example of the said serial communication apparatus, Comprising: It is a block diagram which shows the example of low-speed forward communication. It is an example of the said serial communication apparatus, Comprising: It is a block diagram which shows the example of bidirectional | two-way high speed communication. It is another Example of the serial communication circuit and serial communication apparatus which concern on this invention, Comprising: It is a block diagram which shows the state of the first half of the calibration process of emphasis amount. It is an example of the said serial communication apparatus, Comprising: It is a block diagram which shows the state of the latter half of the calibration process of emphasis amount. It is a flowchart which shows the example of the flow of the calibration process of the said emphasis amount. It is a block diagram which shows the example of the conventional serial communication apparatus.

  Embodiments of a serial communication circuit according to the present invention will be described below with reference to the drawings. The serial communication circuit according to the present invention has a configuration that can cope with switching modes using two communication methods. For example, bidirectional high-speed communication (two-channel bidirectional high-speed communication) that performs bidirectional high-speed communication with two channels and bidirectional communication (one-channel high-speed normal communication / low-speed command) that performs high-speed normal communication and low-speed command communication with one channel (Two-way communication by communication). Therefore, according to the communication circuit according to the present invention, a dedicated signal line for bidirectional communication is not necessary, and the production cost of the communication device can be suppressed as compared with the conventional communication circuit. Further, according to the serial communication circuit of the present invention, the manufacturing cost can be reduced by reducing the number of chip terminals and the number of cables as compared with the conventional one.

  First, in order to clarify the features of the embodiment of the present invention by comparison with the conventional example, a conventional serial communication circuit and a serial communication device including this serial communication circuit will be described first. FIG. 9 is a block diagram showing a configuration of a conventional serial communication device 200. As shown in FIG. 9, a conventional serial communication device 200 includes a SER chip 210 having a serializer function and a DES chip 220 having a deserializer function.

  The serial communication device 200 is configured by connecting the SER chip 210 and the DES chip 220 via the transmission line 230. As will be described later, the SER chip 210 and the DES chip 220 have different configurations. Accordingly, two types of communication IC chips (SER chip 210 and DES chip 220) are used to configure the serial communication device 200. The serial communication device 200 shown in FIG. 9 uses high-speed communication in the forward direction and uses a dedicated signal line for low-speed command transmission.

  When the serial communication device 200 is used for data transmission between the control unit and the operation unit display of the MFP, communication from the control unit to the operation unit display is normal high-speed communication and forward communication. On the other hand, communication from the operation unit display to the control unit is reverse communication. Therefore, the SER chip 210 is disposed on the control unit side, and the DES chip 220 is disposed on the operation unit display side.

  The transmission line 230 is composed of a pair of differential transmission lines and a dedicated signal line.

  The SER chip 210 includes a SER block 211, a DRV block 212, a SER side C_RCV block 213, a SER side C_DRV block 214, and a SER side controller block 215.

  The SER block 211 is a functional block that converts parallel data, which is high-speed data in the forward direction, into serial data.

  The DRV block 212 is a functional block that outputs serial data to the transmission path 230.

  The SER side C_RCV block 213 and the SER side C_DRV block 214 are functional blocks that transmit and receive a low-speed command signal, and are a functional block that combines a serial data transmission block (DRV) and a serial data reception block (RCV). The SER side C_RCV block 213 and the SER side C_DRV block 214 are functional blocks that switch the communication direction of the command signal in accordance with the transmission / reception switching signal from the SER side controller block 215.

  The SER side controller block 215 is a functional block that outputs a transmission / reception switching signal for controlling the communication direction. Based on the transmission / reception switching signal output by the SER side controller block 215, the operation modes of the SER side C_RCV block 213 and the SER side C_DRV block 214 are switched. The SER side controller block 215 outputs a transmission / reception switching signal based on a built-in timer (not shown), a control signal included in data, or the like.

  The DES chip 220 includes an RCV block 221, a CDR block 222, a DES side C_RCV block 223, a DES side C_DRV block 224, and a DES side controller block 225.

  The RCV block 221 is a functional block that receives serial data transmitted via the transmission path 230.

  The CDR block 222 is a functional block that extracts (restores) a clock from the output of the RCV block 221 (RCV output signal, that is, serial data). The CDR block 222 is a functional block that converts serial data into parallel data using the recovered clock.

  The DES side C_RCV block 223 and the DES side C_DRV block 224 are functional blocks that transmit and receive a low-speed command signal, and are a functional block that combines a serial data transmission block (DRV) and a serial data reception block (RCV). The DES side C_RCV block 223 and the DES side C_DRV block 224 are functional blocks that switch the communication direction of command data in accordance with a transmission / reception switching signal from the DES side controller block 225.

  The DES side controller block 225 is a functional block that outputs a transmission / reception switching signal for controlling the communication direction. Based on the transmission / reception switching signal output by the DES side controller block 225, the operation modes of the DES side C_RCV block 223 and the DES side C_DRV block 224 are switched. The DES side controller block 225 outputs a transmission / reception switching signal based on a built-in timer (not shown), a control signal included in data, or the like.

  Next, the operation of the serial communication apparatus 200 having the above configuration will be briefly described. First, an operation during normal communication (forward direction) in the serial communication device 200 will be described. The SER block 211 converts parallel data into serial data. The converted serial data is output by the DRV block 212. The serial data output from the DRV block 212 is transmitted to the DES chip 220 side via the transmission path 230. The transmitted serial data is received by the RCV block 221.

  The received serial data is output from the RCV block 221 to the CDR block 222. The CDR block 222 converts this serial data into parallel data and outputs the parallel data to the DES side controller block 225. The DES controller block 225 outputs the parallel data to an external device (such as an operation unit display). The above is the operation of the conventional serial communication device 200 during normal communication (forward communication).

  Next, low speed command data communication using a dedicated signal line in the serial communication device 200 will be described. The serial communication device 200 uses a dedicated signal line for low-speed command data communication.

  When low-speed data A is transmitted from the DES chip 220 to the SER chip 210 (when a command signal is transmitted from the operation unit display to the control unit), a control signal for switching the communication direction of the low-speed data A is output from the SER side controller block 215. The By this control signal, the SER side C_DRV block 214 of the SER chip 210 enters the sleep state, and the SER side C_RCV enters the active state. A control signal for switching the communication direction of the low-speed data A is also output from the DES side controller block 225. By this control signal, the DES side C_DRV block 224 of the DES chip 220 is in an active state, and the DES side C_RCV block 223 is in a sleep state.

  After the transmission / reception state switching operation is completed, the low-speed data A is transmitted from the DES chip 220 to the SER chip 210 via the dedicated signal line. The SER chip 210 outputs the received low speed data A as low speed data A ′.

  The same applies when low-speed data B is transmitted from the SER chip 210 to the DES chip 220 (when command data is transmitted from the control unit to the operation unit display). That is, a control signal for switching the communication direction is output from the SER side controller block 215. By this control signal, the SER side C_DRV block 214 of the SER chip 210 becomes active, and the SER side C_RCV block 213 enters a sleep state. The DES side controller block 225 also outputs a control signal for switching the communication direction. By this control signal, the DES side C_DRV block 224 of the DES chip 220 enters a sleep state, and the DES side C_RCV block 223 enters an active state.

  After the transmission / reception state switching operation is completed, the low-speed data B is transmitted from the SER chip 210 to the DES chip 220 via the dedicated signal line. The DES chip 220 outputs the received low speed data B as low speed data B ′.

  As described above, the conventional serial communication device 200 is configured by combining the SER chip 210 and the DES chip 220 having different configurations. Therefore, the serial communication device 200 needs to have two communication IC chips having different configurations as one set, and the manufacturing cost of the communication IC chip increases.

  Next, embodiments of the serial communication circuit and the serial communication device according to the present invention will be described. FIG. 1 is a block diagram illustrating a functional configuration of the serial communication circuit 1 according to the present embodiment.

  As shown in FIG. 1, the serial communication circuit 1 includes a SER unit 10, a DES unit 20, a changeover switch 30, a controller unit 40, a differential output terminal 31, and a differential input terminal 32. .

  The serial communication circuit 1 includes the configuration of each unit described above. That is, the serial communication circuit 1 has a configuration corresponding to the configuration included in the SER chip 210 and the DES chip 220 used in the conventional example.

  More specifically, the serial communication circuit 1 includes the functions of the conventional SER block 211 and DRV block 212 in the SER unit 10. In addition, the DES unit 20 has functions of the RCV block 221 and the CDR block 222.

  The SER unit 10 includes a serializer 11 and an output driver 12. The DES unit 20 includes an RCV_F unit 21 that is a first receiver, a CDR unit 22, and an RCV_S unit 23 that is a second receiver.

  The serializer 11 converts parallel data that is high-speed data in the forward direction into serial data (high-speed serial data) that is first data. Further, the serializer 11 converts the low-speed data (control data) in the forward direction into differential data (differential control data) that is second data.

  The serializer 11 includes an output driver function for low-speed data (the function of the SER side C_DRV block 214 in FIG. 9). Therefore, the serial communication circuit 1 can have a smaller chip area than the conventional SER chip 210.

  The serializer 11 has a function of discriminating between high-speed data to be serialized and low-speed data not to be serialized, and selecting whether to operate in the transmission / reception mode. When the serializer 11 operates in the transmission mode, either high speed data or low speed data is output to the output driver 12. If the input data is parallel data, the serializer 11 performs serialization processing to convert the input data to serial data. If the input data is single data, the serializer 11 converts the input data to differential data without performing serialization. . Therefore, command data that is low-speed data is converted from single data to differential data and output without serialization.

  The output driver 12 has a function of outputting data output from the serializer 11 to the transmission line 3 via the differential output terminal 31.

  The RCV_F unit 21 has a function of receiving and outputting first data (serial data) that is serialized high-speed data. The RCV_F unit 21 includes a high frequency compensation equalizer (not shown).

  The CDR unit 22 has a function of extracting (restoring) a clock from output data (RCV output signal, that is, serial data) of the RCV_F unit 21. The CDR unit 22 has a function of converting serial data into parallel data using the extracted clock and outputting the parallel data to the controller unit 40.

  The RCV_S unit 23 has a function of receiving and outputting second data (differential control data) that is low-speed data. Since it is not necessary to equalize the low-speed data, the RCV_S unit 23 does not include a compensation equalizer. A single signal line between the RCV_S unit 23 and the controller unit 40 is configured. Therefore, the RCV_S unit 23 does not convert the data format and outputs the data to the controller unit 40 as it is. Although not shown, it is preferable to provide a switch between the differential input terminal 32 and the RCV_S unit 23 in order to reduce the parasitic capacitance to the differential input terminal 32.

  The changeover switch 30 is disposed between the differential output terminal 31 that is an output end and the input of the RCV_F 21. The changeover switch 30 is a switch that is turned on / off based on a transmission / reception changeover signal output from the controller unit 40. Since the changeover switch 30 is connected to the input end of the RCV_F unit 21, it is necessary to suppress data attenuation during high-speed data communication. Accordingly, a switch having a small load capacity and a small switch size is used as the changeover switch 30.

  The controller unit 40 is a block that outputs a transmission / reception switching signal for controlling the communication direction. The controller unit 40 outputs a signal (transmission / reception switching signal) for switching between transmission and reception based on a built-in timer (not shown), a transmission / reception switching signal included in data, and the like.

  The serial communication circuit 1 having the above configuration includes the functions of the SER chip 210 and the DES chip 220 in the conventional example, and the serial communication circuit 1 further includes a differential output terminal 31 and a differential input terminal 32. With these configurations, the serial communication circuit 1 is configured to support two-channel bidirectional high-speed communication.

  The serial communication circuit 1 includes an RCV_F unit 21 that is a high-speed data receiving unit and an RCV_S unit 23 that is a low-speed data receiving unit, and a differential output terminal 31 and a differential input terminal 32 that are connected to the transmission path 3. Further, a changeover switch 30 is provided. This makes it possible to support bidirectional high-speed communication with two channels without providing a command communication dedicated signal line.

  That is, the serial communication circuit 1 operates in a half-duplex communication system when one channel is used by disposing the changeover switch 30 in Tx-Rx (between the differential output terminal 31 and the differential input terminal 32). By switching the TX mode (transmission mode) and the RX mode (reception mode) with the changeover switch 30 and transmitting / receiving low-speed command data, a signal line dedicated for command communication becomes unnecessary.

  As described above, the serial communication circuit 1 is configured to perform “bidirectional high-speed communication that performs bidirectional high-speed communication with two channels” and “high-speed normal communication with one channel” according to the mode of the communication device configured using the serial communication circuit 1. It can be used for both of “bidirectional communication for performing low-speed command communication”.

  Hereinafter, the serial communication device 100 using the serial communication circuit 1 will be described. 2 to 4 are block diagrams showing the configuration of the serial communication device 100. FIG. 2 to 4 show a case where image data is transmitted from the controller side of the MFP to the operation unit display side, for example, using only one channel, which is referred to as “normal communication for high-speed transmission in the forward direction”. The structure which performs is illustrated.

  As shown in FIG. 2 to FIG. 4, the serial communication device 100 connects the serial communication circuit 1 to both ends of the transmission line 3, the differential output terminal 31 of one serial communication circuit 1, and the other serial communication circuit. One differential input terminal 32 is connected via the transmission line 3.

  In the following description, the functional block in each figure indicated by a solid line indicates a functional block that operates when each communication mode is executed. In addition, functional blocks that do not operate when each communication mode is executed are indicated by broken lines.

  FIG. 2 shows an example of configuring a serial communication device 100 that functions as a bidirectional communication system using a serial communication circuit 1 having a SER function and a DES function. As shown in FIG. 2, in the serial communication circuit 1, the chip X that operates the SER function and the chip Y that operates the DES function are communication chips (serial communication circuit 1) having the same configuration. Communication from chip X to chip Y is forward communication.

  As shown in FIG. 2, in the chip X on the transmission side, only the serializer 11 and the output driver 12 are in an operating state (active state). On the other hand, only the RCV_F unit 21 and the CDR unit 22 of the receiving side chip Y are in the active state.

  As a result, when using the serial communication device 100 and using only one channel and performing forward communication from the control unit side to the operation unit display side, “normal communication” for transmitting image data at high speed can be executed. .

  FIG. 3 shows a case of reverse communication in which the control signal (command data) is transmitted from the operation unit display side of the chip Y to the controller unit 40 of the chip X in the serial communication device 100. In this case, a transmission / reception switching signal is output from the controller unit 40 of the chip X and the chip Y, and the chip X operates as a receiving side and the chip Y operates as a transmitting side.

  As shown in FIG. 3, in the chip Y on the transmission side, only the serializer 11 and the output driver 12 are in an operating state (active state). On the other hand, only the RCV_S unit 23 of the receiving side chip X becomes active. Further, the changeover switch 30 is turned ON for both the chip X and the chip Y. As a result, the low-speed command data input to the chip Y from the operation unit display (not shown) is transmitted from the RCV_S unit 23 of the chip X to the control unit of the MFP via the controller unit 40 of the chip X.

  FIG. 4 is a diagram illustrating a state in which forward low-speed communication is performed in the serial communication device 100 functioning as a bidirectional communication system. In FIG. 4, in the forward low-speed communication of the serial communication device 100, a transmission / reception switching signal is output from the controller unit 40 of the chip X and the chip Y, and the chip X is set as the transmission side and the chip Y is set as the reception side. .

  In this case, in the chip X on the transmission side, the serializer 11 and the output driver 12 are in the operating state (active state), and in the chip Y on the receiving side, the RCV_S unit 23 is in the active state. Further, the changeover switch 30 is turned OFF for both the chip X and the chip Y. As a result, the low-speed command data input to the chip Y from the operation unit display (not shown) is output from the RCV_S unit 23 of the chip X via the controller unit 40 of the chip X. Thereby, a control signal from the control unit side to which the chip X is connected to the operation unit display side to which the chip Y is connected is transmitted by forward communication.

  FIG. 5 is a diagram illustrating a state when bidirectional high-speed communication is performed in the serial communication device 100 functioning as a bidirectional communication system. As shown in FIG. 5, in the serial communication device 100, the transmission path 3 that connects the chip X and the chip Y is configured by two pairs of differential transmission paths.

  Since bidirectional communication is performed via the transmission path 3 that is two pairs of differential transmission paths, both the chip X and the chip Y turn off the changeover switch 30. In addition, both the RCV_S units 23 of the chip X and the chip Y are set in the sleep state, and other configurations are set in the active state. As a result, high-speed data transmission can be performed in a full-duplex communication system in both directions between the chip X and the chip Y.

  Further, when the serial communication device 100 functions as a bidirectional communication system and does not perform high-speed communication (period), reading (reading) and writing (reading) to the internal register of the chip Y by command transmission (period). Light). In this case, the RCV_F unit 21 of the chip X and the chip Y is set in the sleep state, the RCV_S unit 23 is set in the active state, and control data for reading and writing the internal register of the chip Y is transmitted between the chip X and the chip Y. Command communication is performed using the channel.

  In this case, the difference from the command communication between the operation unit display and the controller is that the communication direction of the control data is the same as the communication direction of high-speed transmission, and full-duplex communication using two channels is performed. Of course, only one of the two channels (only one channel) can be used to perform half-duplex communication in the same manner as between the operation unit display and the controller.

  Next, another embodiment of the serial communication circuit and the serial communication device according to the present invention will be described. 6 and 7 are functional block diagrams showing the configuration of the serial communication device 100a configured by the serial communication circuit 1a according to the present embodiment. The same components as those of the serial communication circuit 1 and the serial communication device 100 already described are denoted by the same reference numerals, and detailed description thereof is omitted.

  As shown in FIGS. 6 and 7, the serial communication circuit 1 a further includes an amplitude detection unit 41. The amplitude detection unit 41 is connected between the differential input terminal 32 and the RCV_F unit 21 and the RCV_F unit 21. The amplitude detector 41 is a functional block that detects the signal amplitude value of the first serial data in the input signal to the serial communication circuit 1a. The amplitude detector 41 compares a preset reference voltage with the amplitude value (input amplitude) of the input signal using a comparator, and outputs the comparison result. The detection result by the amplitude detector 41 is output to the controller unit 40. The reference voltage can be arbitrarily set according to the voltage dividing ratio of the series resistance.

  The serial communication device 100a configured using the serial communication circuit 1a can execute an emphasis amount calibration process. Emphasis is a function that compensates in advance for attenuation of high-frequency components that occur in the transmission path 3.

As shown in FIGS. 6 and 7, an equalizer (not shown) included in the receiving side (in the present embodiment, the serial communication circuit 1 a on the chip X side) is a high-frequency component of data received via the transmission path 3. Among them, the high frequency component attenuated in the transmission path 3 can be compensated to some extent. However, if the transmission line 3 becomes long, it cannot be sufficiently compensated only by the equalizer. Therefore, the serial communication circuit 1a is used in combination with an equalizer to execute an emphasis amount correction function. Thereby, a large attenuation in the transmission line 3 can be compensated.

  The output driver 12 included in the serial communication circuit 1a is a current output type DRV that allows easy adjustment of the emphasis amount.

  The emphasis amount calibration process is roughly divided into the first half and the second half. FIG. 6 is a block diagram illustrating the first half of the calibration process for the emphasis amount. FIG. 7 is a block diagram showing the second half of the emphasis amount calibration process.

  As shown in FIG. 6, in the first half of the emphasis amount calibration process, the chip X functions as a transmission side and the chip Y functions as a reception side. Therefore, the serializer 11 and the output driver 12 of the chip X are in the active state, and the RCV_F unit 21, the CDR unit 22, and the amplitude detection unit 41 of the chip Y are in the active state.

  Further, as shown in FIG. 7, in the latter half of the emphasis amount calibration process, the chip X functions as a receiving side and the chip Y functions as a transmitting side. Therefore, the RCV_S unit 23 of the chip X becomes active, and the serializer 11 and the output driver 12 of the chip Y become active.

  Next, an emphasis amount calibration process that can be executed in the serial communication device 100a will be described. FIG. 8 is a flowchart illustrating an example of the flow of the emphasis amount calibration process executed in the serial communication device 100a according to the present embodiment. In FIG. 8, each processing step is expressed as S1, S2, S3.

  When the operation of the serial communication device 100a is started, an emphasis amount setting process (S1) is first executed as an emphasis amount calibration process. At the start of operation of the serial communication device 100a, the emphasis amount is set to a minimum value (min).

  Subsequently, a transmission / reception mode setting process (S2) is executed. In this process, as shown in FIG. 6, the chip X is set to the transmission mode and the chip Y is set to the reception mode. Accordingly, the RCV_F unit 21, the CDR unit 22, the RCV_S unit 23, and the amplitude detection unit 41 on the chip X side are in a dormant state. On the other hand, the serializer 11, the output driver 12, and the RCV_S unit 23 on the chip Y side are in a dormant state.

  After the transmission / reception mode setting process (S2) ends, an arbitrary test pattern is transmitted from the chip X on the transmission side to the chip Y on the reception side during forward communication (S3). This test pattern is a test pattern for emphasis setting, and is a high-speed test pattern.

  Subsequently, the chip Y detects an attenuation amount, an eye opening degree, and the like in the transmission path 3 from the received test pattern in the amplitude detection unit 41 and notifies the controller unit 40 of the chip Y of the detected amount. The controller unit 40 executes determination processing for determining whether or not the amplitude of the test pattern received by the chip Y is a desired amplitude based on the notified detection value. (S4).

  If the determination result is the desired amplitude (Yes in S4), the amplitude detection result is transmitted to the controller unit 40. The transmitted amplitude detection result is held in an internal register of the controller unit 40. Since the configurations of the chip X and the chip Y are the same, the calibration of the emphasis amount of the chip Y can be performed based on the test pattern transmitted from the chip X. As a result, the emphasis amount calibration process on the chip Y side becomes unnecessary.

  If the result of the determination process (S4) is not the desired amplitude (No in S4), the controller unit 40 generates an arbitrary amplitude adjustment signal based on the amplitude detection result. The generated amplitude adjustment signal is held in the register of the chip Y. Subsequently, a transmission / reception mode switching process (S5) is executed.

  By the transmission / reception mode switching process (S5), as shown in FIG. 7, the serializer 11, the output driver 12, the RCV_F unit 21, the CDR unit 22, and the amplitude detection unit 41 on the chip X side are in a dormant state. On the other hand, the RCV_F unit 21, the CDR unit 22, the RCV_S unit 23, and the amplitude detection unit 41 on the chip Y side are in a dormant state. As a result, the chip X is set to the reception mode, and the chip Y is set to the transmission mode.

  Subsequently, the emphasis amount adjustment data (emphasis amount adjustment signal) held in the controller unit 40 of the chip Y is transmitted from the chip Y to the chip X (S6).

  Chip X receives the emphasis amount adjustment data as the low-speed command data. The controller unit 40 on the chip X side outputs an arbitrary signal for increasing the emphasis amount to the output driver 12 based on the received emphasis amount adjustment data. Thereby, the emphasis amount is set.

  The above processing is repeated until the result of the amplitude determination process (S4) of the test pattern transmitted from the transmission side (chip X) to the reception side (chip Y) becomes “Yes”. Adjust while increasing.

  As a result, the amount of emphasis can be changed in accordance with the characteristics of the transmission path 3. It is also possible to detect disconnection of the transmission path 3.

  As described above, the characteristics of the communication apparatus according to the present invention are summarized as shown in Table 1 below. Even if normal communication is only in one direction, SER / DES and a communication direction switching function are installed, and half-duplex communication is performed by turning on / off a switch for switching between forward and reverse communication between input and output terminals. Can do.

(Table 1)


Table 1 defines normal communication as the forward direction.

DESCRIPTION OF SYMBOLS 1 Serial communication circuit 10 SER part 11 Serializer 12 Output driver 20 DES part 21 RCV_F part 22 CDR part 23 RCV_S part 30 Changeover switch 31 Differential output terminal 32 Differential input terminal 40 Controller part 41 Amplitude detection part

Japanese Patent No. 4949816

Claims (4)

A SER unit comprising: a serializer that converts input data into first data or second data; and an output driver that outputs the first data and the second data to a transmission line;
A first receiver that receives and outputs the first data, a CDR that extracts a clock from the output data of the first receiver, converts the first data into a format of the input data, and outputs the CDR; A second receiver for receiving and outputting the second data;
A DES section having
A changeover switch disposed between an output terminal of the output driver and an input terminal of the first receiver;
A controller that generates and outputs a control signal for controlling operations of the SER unit, the DES unit, and the changeover switch;
A serial communication circuit comprising: An amplitude detector that detects a signal amplitude of the first data and outputs a detection result to the controller;
The amplitude detector detects a signal amplitude value of the first data at an input end of the first receiver;
The controller generates an arbitrary control signal according to the signal amplitude value detected by the amplitude detector.
The serial communication circuit according to claim 1. The controller determines whether a clock extracted in the CDR and an arbitrary pattern are the same, and generates the control signal based on a determination result;
The serial communication circuit according to claim 1. A serial communication device that connects a serial communication circuit to both ends of a differential transmission line and performs bidirectional communication by a full-duplex communication method or a half-duplex communication method,
The serial communication circuit is the serial communication circuit according to any one of claims 1 to 3.
A serial communication device characterized by that.