JPH03244159A - Electrostatic induction semiconductor device - Google Patents

Abstract

PURPOSE:To enhance the breakdown strength and the resistance of environment of the title device and to facilitate the manufacture of the device by a method wherein a CVD oxide film is formed on a thick thermal oxide film. CONSTITUTION:A cathode region 10 and gate regions 6 are respectively formed in the surface part of a semiconductor substrate 1 in such a way that the region 10 is interposed between the regions 6, and guard ring regions 7 are formed outside the regions 6 and 10. A thermal oxide film 2 covering these regions 7 is formed thick, a thermal oxide film 8 covering the individual regions 6 and 10 is formed thin and a CVD oxide film 4 is formed on the film 2. As the film 2 is thick, a sufficient breakdown strength is obtained and as the film 4 is formed on the film 2, a device is hardly influenced from the outside and the resistance to the environment of the device is improved.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a static induction semiconductor device.

[Conventional technology]

A conventional electrostatic induction semiconductor device is a surface gate type electrostatic induction cell. FIG. 3 shows the basic configuration of a surface-gate type electrostatic induction SIRISK. This SIRISK has a cathode region (n+ semiconductor region) on one side of a semiconductor substrate 80.
81 and a gate region (p" semiconductor region) 82, and an anode region @ (p" semiconductor region) 83 on the other surface, and a high resistivity region (low impurity concentration) between the cathode region 81 and anode region 83. The high resistivity region 84 is a so-called base region.

A guard ring region (p'' semiconductor region) 85 is provided outside both the cathode region 81 and the gate region 82, which functions to maintain the breakdown voltage above a certain level. A gate electrode G is provided in the gate region 82, and an anode electrode A is provided in the anode region 83.

In this electrostatic induction silice, a signal is applied to the gate electrode G to adjust the height of the potential barrier formed between the gate region 82, thereby controlling the current flowing between the cathode and the anode.

Conventionally, this electrostatic induction cylisk has been manufactured in the following manner.

That is, as shown in FIG. 4(a), the surface of the semiconductor substrate 80 having the n-semiconductor layer 80'' for the high resistivity region on the anode region angle p'semiconductor layer 80' is thermally oxidized by field oxidation. A film 90 is formed, and as shown in FIG.
1, a p-type impurity is introduced, and then the impurity is diffused in a diffusion furnace to form a gate region 82 and a guard ring region 85, as shown in FIG. 4(C). After forming both regions 82 and 85, an n-type impurity is introduced by opening a window 92 in the thermal oxide film 90 for supplying an impurity for forming a cathode region, and then the impurity is diffused in a diffusion furnace. As shown in FIG. 4 (dl), a cathode region 81 is formed.After this, a electrode A is formed on each electrode G to complete the silisk.

[Problem to be solved by the invention]

However, this electrostatic induction risk has problems in that it does not have sufficient withstand voltage and environmental resistance.

The problem with breakdown voltage is mainly due to the fact that the thermal oxide film 90 is not thick (about 0.8 nm). The thermal oxide film 90 has the role of allowing the guard ring region 85 to properly exhibit its breakdown voltage holding function. According to the results obtained from the inventors' studies, the thermal oxide film 9
It has been found that the thicker the thermal oxide film 90, the smaller the interface state between the semiconductor substrate 80 and the thermal oxide film 90, and the higher the breakdown voltage.
mouth or more) and the production of cyrisk becomes difficult. one is,
This is because when the thermal oxide film 90 becomes thicker, the window width precision of the window 92 deteriorates, and the resulting SiRisk has larger variations in characteristics. Another reason is that the reliability of the cathode electrode becomes low.

The width of the window 92 is usually about 2 .mu.m, but if the thickness of the thermal oxide film 9 is 1 .mu.m or more, the aspect ratio is too large and wire breakage is very likely to occur. As described above, if the thermal oxide film is larger than 1μ1, manufacturing becomes extremely difficult.

On the other hand, in order to improve environmental resistance, it is sufficient to stack a CVD oxide film on top of a thermal oxide film that covers the guard ring area near the edge of the chip. If oxide films are stacked, the withstand voltage will drop significantly.

In view of the above circumstances, this invention has excellent pressure resistance and environmental resistance,
An object of the present invention is to provide an electrostatic induction semiconductor device that is easy to manufacture.

[Means to solve the problem]

In order to solve the above problems, the electrostatic induction semiconductor device according to the present invention has a cathode region 10 and a gate region 6 on the surface portion of the semiconductor substrate 1, as shown in FIG.
However, gate regions 6 are formed so as to sandwich a cathode region 10, and a guard ring region 7 is formed outside both the regions 6 and 10.
The thermal oxide film 2 covering the gate region 6 and the cathode region 10 is thin, and the thermal oxide film 8 covering both the gate region 6 and the cathode region 10 is thin. The configuration is such that CVD oxide films 4 are laminated.

The electrostatic induction semiconductor device of the present invention is not limited to a thyristor configuration but also includes a transistor configuration. However, in the case of a transistor, the cathode is commonly called the source (the anode is commonly called the drain), so in the case of a transistor, the cathode in the claims shall be read as the source.

The thickness of the thermal oxide film covering the guard ring region of the electrostatic induction semiconductor device of the present invention is set to 1 μm or more, usually in the range of 1 to 2 μm. CV stacked on this thermal oxide film
D (Chemical Vapor Deposits)
(vapor phase growth accompanied by chemical reaction) The thickness of the oxide film is:
Usually, it is set to 0.5 μm or more, for example, in the range of 0.5 to 1.5 μm. The thermal oxide film depends on the material of the semiconductor substrate, but for example, in the case of a silicon semiconductor substrate, it is a SiO□ film.

The semiconductor device according to the present invention can be manufactured, for example, as follows.

That is, as shown in FIG. 1 (dl), as a semiconductor substrate, impurities for forming a gate region and a guard ring region are each diffused to a certain depth A1, and a thermal oxide film 2 having a thick surface and a CVD film laminated thereon are used. Using a semiconductor substrate 1 covered with an oxide film 4, as shown in FIG.
After selectively removing the portion covering the area for forming the cathode region, as shown in FIG. (As shown in g+, impurities for the cathode region are supplied by opening a window 9 in the cathode region formation portion of the thin thermal oxide film 8 formed in the gate region/cathode region formation region by the impurity thermal diffusion treatment. do it like this.

It goes without saying that the electrostatic induction semiconductor device of the present invention is not limited to the configuration illustrated in FIG. 1 (hl) or the manufacturing example described above.

[For production]

The electrostatic induction semiconductor device of the present invention has a sufficient breakdown voltage because the thermal oxide film covering the guard ring region is thick.

A CVD oxide film is laminated on top of the thick thermal oxide film and is hardly affected by the outside world, so it has excellent environmental resistance.

The inventors have discovered that when the thermal oxide film is thick like this, the withstand voltage does not decrease even if CVD films are stacked. This point will be specifically explained with reference to FIG.

In Figure 2, ■ indicates the interface state and breakdown voltage of the semiconductor device in the case of a thermal oxide film with a thickness of 1 μm, and * indicates the interface state and breakdown voltage of the semiconductor device in the case of a thermal oxide film with a thickness of 0.8 nm. (Other configurations are the same for both). The box shows the interface state and breakdown voltage when a 1 μl thick CVD oxide film is stacked on a 1.5 μl thick thermal oxide film, and the ○ indicates a 1 μl thick CVD oxide film stacked on a 0.8 μl thick thermal oxide film. The interface state and breakdown voltage are shown when the films are stacked (other configurations are the same). Comparison of the data shown in (2) and (2) shows that as the thickness of the thermal oxide film increases, the withstand voltage increases significantly. From the comparison of the pigs shown by mouth and O, it can be seen that when the thickness of the thermal oxide film is thick, even if CVD oxide films are stacked, there is no reduction in breakdown voltage.

Furthermore, since the thermal oxide film covering the peripheral areas of the cathode region and gate region is thin, the window for impurity supply can be opened with good width accuracy, and the aspect ratio of the window is not high, so variations in characteristics can be reduced. The reliability of the electrode is also high.

〔Example〕

Embodiments of the electrostatic induction semiconductor device according to the present invention will be described in detail below from the manufacturing stage.

Example 1 First, as shown in FIG. 1 (al), wet oxidation (1100% °C,
320 minutes) to form a thermal oxide film 2 with a thickness of 1.5 μm. Note that the semiconductor substrate 1 can be made, for example, by diffusing p-type impurities into the back surface of an n-silicon semiconductor wafer.

Next, as shown in FIG. 1 (bl), p-type impurities are introduced into the thermal oxide film 2 by opening a window 3 for supplying impurities for forming a gate region and impurities for forming a guard ring region. As shown in FIG. 1 (C1), a shorter diffusion process than before is performed in a diffusion furnace to diffuse p-type impurities to a certain depth 11.

Subsequently, as shown in FIG. 1(d), in order to ensure long-term reliability, a CVD oxide film 4 with a thickness of 1 cm is laminated on the thermal oxide film 2 and annealed. As shown in FIG. 1(e), after selectively removing the parts of the thick thermal oxide film 2 and CVD oxide film 4 that cover the gate region/cathode region forming region (active region R), Diffusion processing (11
50° C. for 1220 minutes) to diffuse p-type impurities to a predetermined depth C2 to form gate regions 6 and guard ring regions 7 as shown in FIG. At this time,
A thin thermal oxide film 8 with a thickness of 0.4 μm is simultaneously formed on the surface of the active region R. In this way, the gate region 6 and the guard ring region 7 are formed by two diffusion processes.

After the formation of the double-headed region 6.7, as shown in FIG. A cathode region 10 is formed between the gate regions 6 by diffusion.After this, a gate electrode G and a cathode electrode are formed, and a final protective film (for example, a CVD oxide film) 12 is laminated. While laminating the resin film 13,
A metal vapor deposited film is laminated on the back surface of the semiconductor substrate 1 to form an anode electrode A.
By forming this, the surface-gate type vertical structure electrostatic induction silicon risk shown in FIG. 1(h) is completed. This cyrisk is
Compared to the conventional model, the breakdown voltage was improved by about 300V.

This invention is not limited to the above embodiments. For example, if the p゛ semiconductor layer 1' of the semiconductor substrate l is an n゛ semiconductor layer, a static induction transistor can be obtained. In addition, another example is one in which the n-type and p-type are reversed in Example 1 above.

〔Effect of the invention〕

The electrostatic induction semiconductor device of the present invention has sufficient breakdown voltage because the thermal oxide film covering the guard ring region is thick, and has environmental resistance because the CVD oxide film is laminated on the thick thermal oxide film. Moreover, since the thermal oxide film covering both the cathode region and the gate region is thin, it has many practical advantages such as less variation in characteristics and high electrode reliability.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing the manufacturing process of an electrostatic induction silice according to an embodiment of the present invention, shown in the order of steps, and FIG. 2 shows the interface states between the semiconductor substrate and thermal oxide film of a semiconductor device A graph showing the relationship between breakdown voltages of semiconductor devices, Figure 3 is a cross-sectional view showing the basic structure of a surface-gate type electrostatic induction cell, and Figure 4 shows the process of manufacturing a conventional electrostatic induction cell. FIG. 3 is a cross-sectional view showing the steps in order. 1... Semiconductor substrate 2... Thick thermal oxide film 4...
・CVD oxide film 6...Gate region 7...Guard ring region 8...Thin thermal oxide film 10...
・Ka-1 2 3 Fig. 2 (V) 00 00 00 00 00 0n (cm-”) Fig.

Claims (1)

[Claims] 1 A cathode region and a gate region are formed on the surface of a semiconductor substrate, with the gate region sandwiching the cathode region, a guard ring region is formed outside both regions, and a thermal oxide film is formed on the surface of the semiconductor substrate. In the electrostatic induction semiconductor device, the thermal oxide film covering the guard ring region is thick, and the thermal oxide film covering both the gate region and the cathode region is thin and covering the guard ring region. A static induction semiconductor device characterized in that a CVD oxide film is laminated on a thermal oxide film.