JPH03242725A - Decimal multiplier circuit - Google Patents

Abstract

PURPOSE:To perform decimal multiplication at a high speed by generating 1-fold to 5-fold values of a multiplicand and performing correction by another arithmetic processing with respect to 6-fold to 9-fold values. CONSTITUTION:1-fold to 5-fold numerical values of the multiplicand are generated and are stored in a register file 5, and digits of a multiplier are successively extracted from the least significant digit, and the multiple value corresponding to the value of each digit is selected from the register file 5 when the value of this digit is equal to or smaller than 5, and the multiple value corresponding to the 10's compliment of the value of each digit is selected from the register file 5 when the value of this digit is equal to or larger than 6. This selected value is subjected to decimal addition processing by a decimal adder 6 while justified to the numerical value of the preceding digit in the case of <= 5 value in the corresponding digit and is subjected to decimal subtraction processing while justified to the numerical value of the preceding digit in the case of >=6 value in the corresponding digit. When the value in the corresponding digit is equal to or larger than 6, such correction is performed at the time of processing of the next digit that one is added to the value of the next digit and the multiple value corresponding to this value is selected from the register file. Thus, quick multiplication is possible.

Description

TECHNICAL FIELD The present invention relates to decimal multiplication circuits, and more particularly to decimal multiplication circuits having decimal adders.

BACKGROUND ART When performing multiplication of decimal numbers, a method is often adopted in which the decimal number is converted into another numerical format that can be handled by an information processing device, for example, into binary number, subjected to arithmetic processing, and then converted back to decimal number.

In the case of such an arithmetic method, conversion processing between decimal numbers and binary numbers takes time, making high-speed processing difficult.

Therefore, in general-purpose large computers that require high speed, a decimal-only arithmetic circuit is installed to perform arithmetic operations without converting to binary numbers.

However, compared to binary arithmetic, decimal arithmetic has drawbacks such as requiring a larger amount of hardware and having greater restrictions on arithmetic units. Many general-purpose large computers are equipped with binary multipliers, but decimal multipliers are not installed due to hardware limitations. For this reason, when performing decimal multiplication, a decimal adder is used.

Decimal multiplication using a conventional decimal adder is performed as follows. That is, each digit from 1 to 9 times the multiplicand is generated using a decimal adder, and these generated values are stored in a register file.

Next, sequentially extract one digit from the lower digit of the multiplication, selectively read the corresponding multiple of the multiplicand from the register file,
The values are weighted (Ni is combined) and added, and the sum is finally calculated to obtain the product.

An example of such conventional technology is Japanese Patent Application Laid-open No. 5582353.
There is a method typified by the publication No. ``Multiplication/Division Calculation Method''.

The above-mentioned conventional decimal multiplication method has the disadvantage that it takes a lot of time because it is necessary to generate each multiple value from 1 to 9 times the multiplicand and store it in the register file. be.

OBJECT OF THE INVENTION Therefore, the present invention has been made to solve the drawbacks of the conventional ones, and its purpose is to provide a 10 multiplier that can be multiplied at high speed without requiring time to generate a multiple value of a multiplicand. The object of the present invention is to provide a base multiplication circuit.

Structure of the Invention The decimal multiplication circuit according to the present invention includes a holding means for generating and holding a numerical value of each integer multiple from 1 to 5 times the multiplicand;
When the value of the extracted digit is 5 or less when the value of the extracted digit is extracted sequentially from the lower digit of the multiplication, a numerical value that is a multiple equal to the value of the digit is selected from the holding means, and when it is 6 or more, the 10's complement of that value is taken. a selection means for selecting from the holding means a numerical value of a multiple equal to the value of the complement; and adding the numerical value selected by the selection means while adjusting the digit to the numerical value of the previous digit when the value of the corresponding digit is 5 or less. However, when the value of the corresponding digit is 6 or more, there is a decimal addition means that subtracts while matching the value of the previous digit, and when the value of the digit is 6 or more, when the value of the next digit is added, 1 is added to the next digit. The method is characterized in that it includes a control means for instructing the selection means to add the value and make the value into a digit value.

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the invention.

In the figure, an operand register 1 is a register that temporarily stores a multiplier and a multiplicand, and also stores the output of the least significant digit of the decimal adder 6 in the most significant digit.

The data register 2 is a register that supplies data to the decimal adder 6 and selectively stores the output of the decimal adder 6 or the data of the register 1.

Complement generation circuit 3 outputs register 1 when flag 7 is “1”.
If the value obtained by adding the value of the lowest digit and the value of flag 7 is 6 or more, the value is converted to a 10's complement, and if it is 5 or less, the value is output as is.

Comparison circuit 4 outputs “1” if the value obtained by adding the value of the lowest digit of register 1 and the value of flag 7 is 6 or more, and outputs “1”.
If it is below, "O" is output.

The register file 5 holds numerical values of integral multiples from 1 to 5 times the multiplicand, and a write address is designated by a write address register 52 having a +1 function. The read address of this register file 5 is specified by the selector 31, and when the output of the comparator 4 is "1", the output of the complement generation circuit 3 is read, and when it is "0", the least significant digit output of the register 1 is read. It is designed to be used as an address.

The decimal adder 6 performs decimal addition and subtraction on both data in the data registers 2 and 51, and the result of this operation is introduced into the data register 2. The register 51 selectively temporarily stores read data of the register file 5 or data of the operand register 1.

Flag 7 is set by the output of comparator 4,
Depending on the output of this flag 7, the decimal adder 6 performs addition and subtraction processing. That is, if flag 7 is "1",
It is assumed that the subtraction process is performed, and if the value is 0'', the addition process is performed.

First, to explain the present invention in detail, numerical values that are integral multiples of 1 to 5 times the multiplicand are created and stored in the register file 5. Then, when the value of each digit is extracted sequentially from the lower digit of the multiplier and is less than 5, a multiple value equal to the value of that digit is selected from register file 5, and when it is 6 or more, 10 of that value is selected.
The complement of is taken, and a multiple value equal to this complement is selected from the register file 5.

If the value of the corresponding digit is 5 or less, the value selected in this way is digit-aligned with the value in the previous digit and added, and if the value of the corresponding digit is 6 or more, the value is digit-aligned with the value in the previous digit. decimal subtraction processing. Then, when the value of this corresponding digit is 6 or more, when processing the next digit, "1" is added to the next digit and a multiple value equal to that value is selected from the register file.

In other words, when the value of a digit is 6 or more, 1 of the value of that digit
This is done by taking the 0's complement, subtracting the corresponding multiple of the multiplicand, and then correcting it by adding 10 times the multiplicand at the next digit processing stage to make it consistent. The method of adding 10 times the multiplicand is possible by adding +1 to the value of that digit, since that digit has 10 times more weight in the processing stage of the next multiplier digit. Flag 7 is for controlling this correction process.

The actual multiplication operation will be explained step by step below. First, the multiplicand is transferred to the register 1 via the data line 101.
is set to The value of register 1 is set in register 2 and register 51 to make the multiplicand 1 to 5 times. The write address register 52 of the register file 5 has address 1 as its initial value, and first the value of register 2 is written to the word of address 1 as the value of 1 times the multiplicand, and at the same time, the decimal adder 6 is written to the word of address 1. 5
Add a value of 1 and store the result in register 2. Here, the value of register 2 is twice the value of the multiplicand, and the write address register 52 is incremented to indicate address 2.

Next, a value twice the multiplicand of register 2 is written to the word at address 2, and the decimal adder 6 generates a value three times the multiplicand and sets it in register 2, as in the previous case. Write address register 52 indicates address 3. Similarly, up to 5 times the multiplicand is created and stored in the register file 5.

Next, a multiplier is set in register 1 via data line 101. Flag 7 is reset as initialization, and register 2 is set to 0. The value of flag 7 and the least significant digit of register 1 are sent to complement generation circuit 3 and comparison circuit 4. These circuits 31, 4, and selector 31 convert the least significant digit of the multiplier into a value indicating the address of the multiple of the multiplicand to be sent to the adder 6. The value read from the register file 5 using the output of the selector 31 as an address is stored in the register 5.
Set to 1.

The value of the comparator circuit 4 is set in the flag 7.

When the value obtained by adding 1 to the lowest digit of register 1 by the value of flag 7 is 6 or more, flag 7 is set to "1". When the value of flag 7 is "0", decimal adder 6 adds the values of register 2 and register 51, and the value of flag 7 becomes 1.
In this case, the value of register 51 is subtracted from register 2.

In this subtraction process, if the result of subtracting the value of register 51 from register 2 is negative, the result becomes a 10's complement number. That is, by adding +1 to the value (9's complement) obtained by subtracting the value of each digit from 9, it becomes a 10's complement. For example, if the subtraction result is -524, 9-5-4.9
-2-7.9-4-5 gives 475 (9's complement), which becomes 476 by +1. This is obtained as the subtraction result.

The output of the decimal adder 6, excluding the least significant digit, is stored in the register 2 in the form of being shifted one digit to the right. Furthermore, the value of register 1 is shifted one digit to the right and stored in the least significant digit. Since the value of register 2 is shifted to the right by one digit, the next multiple of the multiplicand set in register 51 will have a weight of one digit.

By continuing such processing, the product remains in register 2 and register 1. The multiplier of register 1 becomes a gong,
Then, the value of flag 7 becomes "0" and the process ends. In the product of register 2 and register 1, the upper part is stored in register 2 right-justified, and the lower part is stored in register 1 left-justified. The value of register 1 is output to the data line 102, and the value of register 2 is output to the data line 201 to the outside of the multiplication circuit.

Next, we will follow the changes in the contents of each register using specific numerical examples. For example, 524x184-96
418, the values of each register 1, 251 and flag 7 become as shown in FIG.

At timing to, the value of the least significant digit of register 1 is 4, and the value of franc 7 at this time is "0", so the output of comparator circuit 4 remains "0". Therefore,
The selector 31 outputs the value 4 of the least significant digit of the register 1 as it is as the read address of the register file 5.

At timing t1, the value 20 is four times the multiplicand 524.
96 is set in register 51, and the contents of register 1 become 18 shifted to the right. At this time, the comparator 4 detects that the least significant digit 8 of the register 1 is 6 or more, and its output becomes "1".

Therefore, the selector 31 returns 2 (10-8), which is the correction of 10 of 8, which is the output of the complement generation circuit 3.
This is the read address of register file 5. Therefore, at timing t2, 524 x 2-104
8 is selectively read out and set in the register 51.

At this time, data 209 excluding the least significant bit of the addition result at the previous timing tl is stored in register 2 (the least significant bit 6 is stored in register 1),
Moreover, since the output "1" of the comparator 4 is set as the flag 7, the decimal adder 6 subtracts the register 51 from the register 2.

At this time, the result is -839, which is negative, so
As described above, 161, which is the complement of 10, is generated, and 16 excluding the least significant bit is stored in register 2 at timing t3. The least significant bit, 1, is stored in register 1.

Then, since the sum 2 of "1" of the flag 7 at timing t2 and the lowest digit 1 (shifted to the right by one digit) of the register 1 at that time is less than or equal to 5, the complement generation circuit 3
This sum 2 is output as is through the selector 31 and is used as the read address of the register file 5. Therefore, at this time, 524 x 2-1048 is entered manually in the register 51, and at this stage, the correction is performed ten times as much as when the first digit is "8".

In this case, since the output of the comparator circuit 4 is "0", the decimal adder 6 performs the addition, and at timing t4, the lower two digits of register 2 and the upper three digits of register 1 are stored as 96.
418 is retained.

Results of the Invention As described above, according to the present invention, a value of 1 to 5 times the multiplicand is only generated, and a value of 6 to 9 times is corrected by other arithmetic processing. This has the effect of allowing radical multipliers.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram of an embodiment of the present invention, and FIG. 2 is a diagram showing changes in the contents of each register to explain the operation of the embodiment. Explanation of symbols of main parts 1.2.51...Register 3...10's complement generation circuit 4...Comparison circuit 5...Register file 6. ... Decimal adder 7 ... Flag

Claims (1)

[Claims] (1) A holding means that generates and holds numerical values of each integer multiple from 1 to 5 times the multiplicand, and when the value of the extracted digit is 5 or less by sequentially extracting from the lower digit of the multiplication, from the holding means. selection means for selecting a numerical value that is a multiple equal to the value of the digit, taking the 10's complement of the value when it is 6 or more, and selecting from the holding means a numerical value that is a multiple equal to the value of the complement; and the selecting means If the value of the corresponding digit is less than or equal to 5, add the selected value to the value of the previous digit while aligning it, and if the value of the corresponding digit is greater than or equal to 6, subtract it while aligning the value of the previous digit. decimal addition means; and control means for instructing the selection means to add 1 to the next digit when adding the next digit when the value of the digit is 6 or more, and to make that value the value of the digit. A decimal multiplication circuit characterized by: