JPH03241946A - Tri-state signal generating circuit - Google Patents

Abstract

PURPOSE:To detect a period accurately by providing a means limiting an output voltage of a time constant circuit and generating a tri-state signal phase-locked with a 1st input signal in response to the presence of a 2nd signal. CONSTITUTION:The inverse of PG signal is inputted to a limit circuit section 1 and a limit signal of a voltage M is generated and inputted to a PG/FG synthe sis section 2. Moreover, the inverse of FG is inputted to the PG/FG synthesis section 2 and a tri-state signal PG/FG of voltages H, M, L is sent to a period detection circuit built in an IC 2 in response to the limit signal of the voltage M. Thus, the voltage charged at a prescribed time constant is clamped in the generating of the voltage M. Then even when a capacitor is added due to noise countermeasure to a tri-state signal output line, no change takes place in the time constant in the generation of voltages L, M, H. Thus, an accurate period is detected.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention relates to a three-level signal generation circuit, and is particularly suitable for generating three-phase signals that transmit periodic information using rising edges and other information using levels. be.

Conventional technology Conventionally, in motor control circuits, etc., it is based on the start-up cycle of three-value pulses! 11 Information indicating the rotational speed is transmitted, and information indicating the rotational phase is transmitted using a pulse having a different level from other pulses. Fourth
The figure shows an example of conventional appositional generation of three-valued signals, and FIG. 5 is a timing chart thereof.

As shown in FIG. 4, the emitter of the transistor Q1 is grounded, and the collector is divided into three parts via a resistor R2. The first one is connected to the power supply (desired high voltage, hereinafter referred to as H voltage) via the resistor R1, the second one is connected to the collector of the transistor Q2, and the third one is taken out for output.

The emitter of transistor Q2 is also grounded.

Further, when the circuit is built in the integrated circuit IC1 as shown in the figure, the output is connected to the surge resistor R3 (
approximately 1 Kj; l) to the output pin 10. In the circuit, a signal P is connected to the base of the transistor Q1.
The G multiplication signal (a signal obtained by inverting the PG signal indicating the rotational phase of the motor) is input, and the signal FG (a signal obtained by inverting the frequency generator output FG signal indicating the rotational speed of the motor) is input into the Q2 pace. It has a format. Here, the middle voltage (hereinafter referred to as M voltage) is V. R4 to make c/2
, = R2-H.

Next, the operation of FIG. 4 will be explained using the timing chart of FIG. 5 as an example. As shown in the timing chart shown in Fig. 5, when the PG double signal is input and the FG double signal is at H voltage, the output terminal 10 receives a low voltage (KGND, hereinafter referred to as low voltage) regardless of the PG double signal state. Output, FG double signal L? [When the voltage is PG double signal H voltage, the output terminal 1
M voltage (ki vcc/2) is output to o. Also FG
As long as is an L voltage and PG is an L voltage, an H voltage (cow vcc) is output to the output terminal 10.

Problems to be Solved by the Invention Here, when the circuit is built into an IC, a capacitance C is created between the output terminal 10 and the IC 2 that has a built-in period detection circuit as a countermeasure against noise and static electricity. When connected between GND and GND, in the conventional circuit configuration, the output impedance (=R) during the rising period of the H voltage and the output impedance (= R/2') during the rising period of the M voltage are different. , the time constants when the capacitor C is charged are different, and the period detection time when the H voltage is output is delayed by Jt from the period detection time when the M voltage is output. That is, even though the FG with a duty of 50%-50% is input to the base of Q2 in this section, a period delayed by Jt is detected. In the conventional example shown in Fig. 4, R1
- If R2=R, the time constant of the rise period of MN pressure is CR
/2. The time constant of the rising period of the H voltage is CR9, which causes an effect of CR-OR/2=CR/2 as a time difference in period detection.

Here, even in the conventional circuit example, if the circuit side that detects the period (IC2 side in the figure) makes a promise that the period detection will be performed at the falling edge of the output signal, the current sinking ability of Q2 is large. , accurate period detection is possible without time delay. However, as in this case, it is necessary to match the cycle detection side and the three-value output side, so the three-value output circuit and the IC1 containing the output circuit are
The versatility of is lost.

In order to solve the above problems, the present invention makes it possible to accurately detect the cycle of the KM voltage even if a capacitor C is attached to the signal line that outputs the three-value signal for the above reason, and furthermore, the cycle can be detected at the rising edge of the signal. It is an object of the present invention to provide a three-value signal generation circuit that can accurately detect the period of the M voltage whether it is performed at υ or at the falling edge.

Means for Solving the Problems The three-level signal generating circuit of the present invention has a constant time constant that includes the capacity of the output line connected to the output terminal, and charges in synchronization with the input signal shown in FIG. a time constant circuit for starting, and means for limiting the output voltage of the time constant circuit to a predetermined upper limit value in synchronization with a second input signal; This method is characterized in that it does not create a ternary signal that is phase-synchronized with the first input signal.

Effects According to the above configuration, the charging voltage that is charged at a constant time constant is clamped when creating the M voltage, so even if a capacitor is added to the three-value signal output line for noise countermeasures, the L voltage Even if the button is pressed when creating the 2M voltage and H voltage, there is no change in the time constant, making it possible to accurately detect the period. Even if the FG signal period is transmitted to the period detection circuit in a three-value output format, the FG multiplied signal period can be detected accurately, so that the speed control will not be disturbed and the jitter characteristics of the screen will not be adversely affected. Also, recent IC
The influence of noise on the signal line can be reduced by attaching the capacitor C while accurately detecting the cycle.

Embodiment Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is its basic block diagram, FIG. 2 is its circuit example, and FIG. 3 is its timing chart.

1. First, the basic configuration of the present invention will be described with reference to the block diagram shown in FIG. A PG multiplied signal is input to the limit circuit section 1 in the figure, and a limit signal of M voltage is generated and input to the PG/FG synthesis section 2. In the cased PG/FG synthesis part 2, FG
is input, and three hazy value signals PG/FG of the H voltage, the 2M voltage, and the L voltage are transmitted to the period detection circuit built in the IC 2 in accordance with the limit signal of the M voltage.

Further, a detailed explanation will be given using an example of the circuit shown in FIG. The limit circuit section 1 has the following circuit configuration.

The emitter of transistor Q3 is grounded, and the collector is divided into two through resistor R6. One is connected to the base of transistor Q4, and the remaining two diodes Q5 and Q6, which are made up of transistors matched with transistor Q4, are connected in series and connected to vCC via R6. The collector of Q4 is grounded and the emitter of Q4 is divided into three parts. One connects to the collector of transistor Q6, the other connects to vco via R4. The last one is surge resistor R3
It is connected to the output pin 1o of IC3 via. Q
The FG signal is input to the base of the PG multiplied signal Q5.

The same parts as in the conventional example are associated with the same reference numerals.

Here, while referring to the timing chart in Figure 3,
The operation of the present invention will be explained. The output of FG with H voltage becomes L voltage. Also, when PG is at H potential, R5=Re, so the collector potential of Q4 is 5/1vc which is M voltage.
I can't get higher than C. Here, it can be seen that an arbitrary M voltage can be set by changing the resistance values of R6 and R6. Furthermore, when FG is at the L voltage and PG is at the L voltage, the voltage is not limited to the above-mentioned M voltage, so that it rises at the H voltage (=Vcc)'t with a constant time constant. As explained in the "enlarged waveform" in Figure 3, the output impedance of the rising edge section of the M voltage and the rising edge section of the H voltage is equal to R4, so even if the capacitor C is installed, , the time constant of the time constant circuit formed by the capacitor C and the combining section 2 is constant, and the rising slope of the signal is the same. That is, when it is desired to detect the period of the M voltage, accurate period detection is possible even if the H voltage also serves as one pulse of the M voltage. Furthermore, it can be seen that if it is desired to improve the accuracy of period detection, it is sufficient to detect the falling slope period using one period detection circuit in the circuit of the present invention.

As described in detail, the ternary signal generation circuit of the present invention has the following features:
Even if a capacitor is attached to the output line as a noise countermeasure or static electricity countermeasure, accurate period detection can be performed regardless of the rising edge or falling edge of the signal. ! In addition, as an application example of the present invention, the PG double signal FG signal output from the cylinder motor of a VTR is waveform-shaped, and then converted into a three-value signal by the three-value signal generation circuit of the present invention, and the cycle is detected. It can be transmitted to the servo microcontroller containing the circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the basic configuration of an embodiment of the three-value signal generation circuit of the present invention, FIG. 2 is a circuit diagram of the three-value signal generation circuit of the same embodiment, and FIG. 3 is its timing chart. , FIG. 4 is a circuit diagram of a conventional ternary signal generating circuit, and FIG. 5 is its timing chart.

Claims (1)

[Claims] A time constant circuit that has a constant time constant including the capacity of the output line connected to the output terminal and starts charging in synchronization with a first input signal, and a time constant circuit that starts charging in synchronization with a second input signal. and means for limiting the output voltage of the constant circuit to a predetermined upper limit value, and creates a three-value signal phase-synchronized with the first input signal depending on the presence or absence of the second signal. Create circuit.