JP3047417B2 - Tri-level signal generation circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ternary signal generating circuit, and more particularly to a ternary signal generating circuit suitable for generating a three-phase signal transmitting period information by a rising edge and transmitting other information by a level. is there.

2. Description of the Related Art Conventionally, in a motor control circuit or the like, information indicating a rotation speed is transmitted by a cycle of a rising edge of a ternary pulse, and information indicating a rotation phase is transmitted by a pulse having a different level from other pulses. Has been done. FIG. 4 is an example of a conventional circuit for generating a ternary signal, and FIG. 5 is a timing chart thereof.

In Figure 4, the emitter of the transistor Q ₁ is grounded, the collector is 3 Tsuniwaka through the resistor R _2. First first it is connected to the power supply via a resistor R ₁ (hereinafter referred to as H voltage at the high voltage desired), second transistor
Leads to the collector of Q _2, 3 pawl is retrieved for output. The emitter of the transistor Q ₂ is also grounded.
When the circuit is built in the integrated circuit IC1 as shown in the figure, the output is a resistor R ₃ (about 1K) for surge.
Ω) to output pin 10. Base signal PG signal of the transistor Q ₁ (inverted signal of the PG signals indicating the rotational phase of the motor) is inputted in the circuit, Q ₂
A signal FG (a signal obtained by inverting the output FG signal of the frequency generator indicating the rotation speed of the motor) is input to the base of the device. Here, middle voltage (hereinafter referred to as M voltage)
R ₁ = R ₂ = R to make V _CC / 2.

Next, the operation of FIG. 4 will be described using the timing chart of FIG. 5 as an example. Timing as shown in Fig. 5
When a ▼ signal and a ▲ ▼ signal are input, a low voltage (≒ GND, hereinafter referred to as L voltage) is output to the output terminal 10 regardless of the state of the ▲ ▼ signal when the ▲ ▼ signal is at the H voltage. When the ▼ signal is at the L voltage and the ▼ signal is at the H voltage, an M voltage (≒ V _CC / 2) is output to the output terminal 10. The output terminal 10 outputs the H voltage (≒ V _CC ) only when ▼ is the L voltage and ▼ is the L voltage.

Problems to be Solved by the Invention Here, when the circuit is built in an IC, a capacitance C is placed between the output terminal 10 and the IC 2 having a built-in period detecting circuit for noise measures and static electricity measures. When mounted between GNDs, in the conventional circuit configuration, the output impedance (= R) in the rising section of the H voltage and the output impedance (= R / 2) in the rising section of the M voltage are different from each other.
The time constant when the capacitor C is charged is different, and the cycle detection time when outputting the H voltage is delayed by Δt from the cycle detection time when outputting the M voltage. That is, the duty of 50% -50% of the ▲ ▼ in this interval, even though the input to the base of Q _2, will detect a Δt delay period. In the conventional example shown in FIG. 4, if R ₁ = R ₂ = R, the time constant of the rising section of the M voltage is CR / 2, and the time constant of the rising section of the H voltage is CR. CR / 2 = CR / 2
Minute effects occur.

Here, the circuit side in cycles detected in the conventional circuit example (figure IC2 side), if the commitment to perform the timing of the period detected by the falling edge of the output signal, a large current sink capacity Q ₂ ' Therefore, it is possible to accurately detect a cycle without causing a time delay. However, since it is necessary to match the period detection side and the ternary output side as in this case,
The versatility of the ternary output circuit and, hence, the IC 1 incorporating the output circuit is lost.

The present invention solves the above problem, even if the capacitor C is attached to the signal line outputting the ternary signal for the above-described reason,
To provide a ternary signal generating circuit capable of accurately detecting the period of the M voltage and detecting the period of the M voltage accurately even if the period is detected at the rising edge or the falling edge of the signal. It is.

Means for Solving the Problems A ternary signal generation circuit according to the present invention has a constant time constant including the capacity of an output line connected to an output terminal, and starts charging in synchronization with a first input signal. A time constant circuit for outputting a ternary signal comprising a low voltage, a middle voltage, and a high voltage;
Means for limiting the middle voltage of the output voltage of the time constant circuit in synchronization with the input signal of the above, wherein the middle voltages each phase-synchronized with the first input signal in accordance with the presence or absence of the second signal A signal and a high voltage signal are selectively output from the time constant circuit.

Operation According to the above-described configuration, when the charging voltage charged with a constant time constant is generated at the M voltage, the charging voltage is clamped. Therefore, even if a capacitance is added to the ternary signal output line by noise countermeasures or the like, the L voltage, The time constant does not change even when the M voltage and the H voltage are created, and the period can be accurately detected. For example, the PG signal output from the cylinder motor section of the VTR and the F signal are output.
Even if the G signal is waveform-shaped and converted to a ternary output format and transmitted to the period detection circuit, the period of the FG signal can be accurately detected, so speed control is disturbed and the jitter characteristics of the screen are adversely affected. Disappears. In addition, while accurately detecting the effect of signal line noise in recent IC implementation,
By installing the capacitor C, the number can be reduced.

Embodiment An embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a basic block diagram, and FIG.
FIG. 3 is a timing chart showing an example of such a circuit.

First, the basic configuration of the present invention will be described with reference to the block diagram of FIG. In the figure, a limit signal 1 is input to a limit circuit unit 1, a limit signal of M voltage is created, and a PG / FG synthesizing unit 2 is formed.
Is input to Further, PG is input to the PG / FG synthesizing unit 2, and the H voltage, M
The ternary signal PG / FG of the voltage and the L voltage is transmitted to the cycle detection circuit built in the IC2.

Further description will be made in detail using one circuit example of FIG.
The configuration of the limit circuit unit 1 includes the following circuits. The emitter of the transistor Q ₃ are grounded, second collector via a resistor R ₆ Tsuniwakareru. One is a transistor
Leads to the base of Q _4, rest, diodes formed by transistors took transistor Q ₄ and matching
Q ₅ and Q ₆ are connected in series to two and connected to V _CC through R ₅ . The collector of Q ₄ is grounded, and the emitter of Q ₄ is divided into three. One leads to the collector of the transistor Q _5, the other one, through R _4, leads to V _CC.
Last one, via a surge resistor R _3, the output pin 1 of IC3
Connected to 0. The base of Q _3, ▲ ▼ signal, Q
▲ ▼ signal is input to the base of ₅ . The same parts as those in the conventional example are assigned the same reference numerals and related.

Here, the operation of the present invention will be described with reference to the timing chart of FIG. When ▼ is the H voltage, the output of the output terminal 10 becomes the L voltage regardless of the state of the ▲. When ▲ ▼ is H potential,
R ₅ = So R _6, the collector potential of the Q ₄ are, 1 / 2V is M Voltage
_No more than _CC . Here, by changing the resistance value of R ₅ and R _6, it can be seen that it is possible to set an arbitrary M voltage. When ▲ is the L voltage and ▼ is the L voltage, the voltage is not limited to the M voltage.
It rises with a constant time constant up to the H voltage (= V _CC ). As described in the “enlarged waveform” of FIG.
For M voltage rising period and H the voltage rising output impedance equal R ₄ the section of, be attached capacity C, the time constant of the time constant circuit formed by the said capacitor C and the combining unit 2 is constant And the state of the rising slope of the signal is the same. That is, when it is desired to detect the cycle of the M voltage, accurate cycle detection is possible even if the H voltage also serves as one pulse of the M voltage. In addition, when it is desired to improve the accuracy of the cycle detection, it can be seen that in the circuit of the present invention, the cycle of the falling slope may be detected by one cycle detection circuit.

Advantages of the Invention As described above, the ternary signal generation circuit of the present invention can provide accurate irrespective of signal rising and signal falling irrespective of signal rise and fall even if a capacitance is attached to an output line for noise suppression or static electricity suppression. Period detection. In addition, as an application example of the present invention, the PG signal and the FG signal output from the cylinder motor of the VRT are each subjected to waveform shaping, and then converted into a ternary signal by the ternary signal generation circuit of the present invention, and period detection is performed. It can be transmitted to a servo microcomputer including a circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of an embodiment of a ternary signal generation circuit of the present invention, FIG. 2 is a circuit diagram of a ternary signal generation circuit of the embodiment, FIG. FIG. 4 is a circuit diagram of a conventional ternary signal generation circuit, and FIG. 5 is a timing chart thereof. 1 ... Limit circuit section, 2 ... PG / FG synthesis section, IC1 ... IC with built-in ternary output circuit, IC2 ... IC with built-in cycle detection circuit.

Claims (1)

(57) [Claims] The present invention has a constant time constant including the capacity of an output line connected to an output terminal, starts charging in synchronization with a first input signal, and comprises a low voltage, a middle voltage, and a high voltage. A time constant circuit for outputting a value signal; and means for limiting a middle voltage of an output voltage of the time constant circuit in synchronization with a second input signal. A ternary signal generation circuit, wherein the middle voltage signal and the high voltage signal, each of which is phase-synchronized with one input signal, are selectively output from the time constant circuit.