JP3001465B2 - Clock generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a clock generator, and more particularly to a clock generator that controls output buffer timing from an external clock pattern length.

[0002]

2. Description of the Related Art FIG. 1 shows an internal block diagram of a conventional clock generator and a system configuration diagram using the same. In FIG. 1, 1 is a clock generator, 2-
, 2-n are connected to the output buffers inside the clock generator, and 3-1, 3-2, ..., 3-n are connected to the output buffers 2-1, 2-2, ..., 2-n. , 6-2,..., 6-n are output buffers 2-
1 and receiver 3-1, output buffer 2-2 and receiver 3
-2, and the respective pattern lengths between the output buffer 2-n and the receiver 3-n. .., 5-n are signals after the signal 4 has passed through the internal output buffers 22-1, 2-2,..., 2-n.

In the above system, the signal 4 generated in the clock generator 1 is supplied to the receivers 2-1, 2-2,. , 3-n. In the conventional clock generator, when a pattern is connected to each receiver in the shortest time, the pattern lengths are 6-1 and 6-n.
-2, ..., 6-n may have a large gap,
In order to reduce the clock skew difference between the receivers 2-1, 2-2,..., 2-n, it is necessary to match the shorter pattern length with the longer pattern length, which is unnecessary on the PWB. Therefore, it is necessary to draw a clock pattern, which has an adverse effect on other patterns, such as an influence of noise and a space for wiring.

[0004]

The conventional clock generator has a small skew difference between the output buffers, so that if there is a large gap in the pattern lengths to the receivers connected to the output buffers, the clock generators between the respective receivers have a large gap. In order to reduce the difference in skew, unnecessary clock patterns must be drawn on the PWB, which causes other patterns to be affected by noise or to take up wiring space.

An object of the present invention is to provide a clock generator which does not require unnecessary pattern wiring space and can simplify the device configuration.

It is another object of the present invention to provide a clock generator which can minimize the influence of noise on other patterns because there is no unnecessary clock wiring, and has improved reliability.

[0007]

[MEANS FOR SOLVING THE PROBLEMS] To solve the above-mentioned problems.
Therefore, the clock generator of the present invention
The output buffer of the generator
The rise of the reflected waveform at the output end
Each output buffer is detected based on the detection result.
By controlling the output timing.
Skew between each receiver
In clock generator, clock generator
From each receiver end observed at each output buffer end
Pattern length difference is obtained from the rising waveform of the reflected waveform
And the difference voltage based on the comparison result
Delay can be applied to each buffer output waveform
A variable delay buffer, wherein the comparator has a clock
Turns on when the rising edge of the source oscillation signal to the generator is detected
A first transistor, and a signal rising at the receiver end.
A second transistor that is turned on when an up signal is detected;
The time difference between the turning on of the first and second transistors is
Having a peak hold circuit for obtaining the same differential voltage
It is characterized by.

[0008] The variable delay buffer is configured to output the differential voltage.
Compare with multiple reference voltages to determine the level of differential voltage
Different delays are assigned to a plurality of operational amplifiers and the original oscillation signal.
A plurality of delay buffers and the output of the operational amplifier
And a selection circuit for selecting the delay buffer based on
It is characterized by doing.

[0009]

FIG. 2 is a system configuration diagram showing an embodiment of a clock generator according to the present invention. FIG.
Wherein 7 is the clock generator of the present invention,
, 8-n are the same delay output buffer, 9-
, 9-n are receivers connected to each output buffer, 10-1, 10-2, ..., 10-n are variable delay buffers to each output buffer, and 11 is a variable delay buffer from each receiver. This is a comparator for comparing the waveforms of the reflected waves.

On the other hand, a signal 12 is an original oscillation signal, and a signal 13-
, 13-n are variable delay buffers 10
-1, 10-2, ..., the output signal after passing through 10-n,
, 14-n are output signals to the respective receivers after passing through the same delay output buffers 8-1, 8-2, ..., 8-n, and signals 15-1, 15 -2, ..., 1
5-n is a differential voltage signal output from the comparator 11 to each variable delay buffer. Also, 16-1, 16-2,
, 16-n are the same delay output buffers 8-1, 8-2,
, 8-n and the pattern wiring length between the receivers 9-1, 9-2,..., 9-n.

Next, the operation of the clock generator will be described.

The original oscillation signal 1 in the clock generator 7
2 has been generated, and the variable delay buffers 10-1, 10-
,..., 10-n. Note that signals 13-1, 13-2,..., 13-
n has a skew difference of zero at this time.

Next, signals 13-1, 13-2,..., 13
-N is the same delayed output buffer 8-1, 8-2, ..., 8-
n, and output signals 14-1, 14-2,.
−n is input to the receivers 9-1, 9-2,..., 9-n. In this state, the same delay output buffers 8-1, 8-
If the pattern line lengths 16-1, 16-2,..., 16-n are not equal lengths while the delays of 2,..., 8-n are the same, each receiver 9-1, 9-2,. A skew difference occurs at the input end of -n.

The signals arriving at the receivers 9-1, 9-2,..., 9-n are reflected at their input terminals, and
As shown in FIG. 3, the rising waveforms at the output terminals of 1, 8-2,..., 8-n have a step at the intermediate potential for the time Tn. In FIG. 3, the vertical axis indicates the voltage axis, and the horizontal axis indicates the time axis.

According to the Bell Cheron waveform analysis, the time Tn in FIG. 3 depends on each pattern length 16-n. The longer the pattern length, the longer the time Tn. For example, the pattern length 16-1> the pattern length In the case of 16-2, time T1> time T2.

The same delay output buffers 8-1, 8-1,
8-2,..., 8-n,
Comparator 1 compares the difference in pattern length between each driver and receiver.
1 and voltage signals 15-1, 15 corresponding to the difference.
,..., 15-n to the variable delay buffers 10-1, 10
−2,..., 10-n.

Here, the internal circuit of the comparator 11 and the detection of the differential voltage waveform will be described with reference to FIG. The circuits shown in FIG. 4 are provided in the comparator 11 by the number of output buffers.

In FIG. 4, reference numeral 18 denotes a signal appearing on the output buffers 8-1, 8-2,..., 8-n in FIG.

A voltage dividing circuit composed of resistors 19 and 20 is an NPN
Resistors 22 and 2
3 are connected to the bases of the NPN transistors 24, respectively. The emitters of the NPN transistors 21 and 24 are grounded.

The resistors 19 and 20 and the resistors 22 and 23
Are set so that the NPN transistors 21 and 24 are turned on when the signals 12 and 18 are at the high level. The value of the resistor 19 is equal to the value of the resistor 22 and the value of the resistor 20 is equal to the value of the resistor 23. Note that the High level indicates the potential at point a in FIG.

The resistor 25 is connected between the collector of the NPN transistor 21 and the base of the PNP transistor 26, and performs overcurrent control. PNP transistor 26
The emitter is connected to the internal power supply and the collector is
7, is connected to a non-inverting input terminal of an operational amplifier 30 via a diode 29 for preventing reverse current and a capacitor 28.
This circuit is a peak hold circuit that holds the collector terminal potential of the PNP transistor 26 by the time constant of the resistor 27 and the capacitor 28, the reverse current prevention by the diode 29, and the operational amplifier 30 by negative feedback. Reference numeral 15 denotes a differential voltage signal obtained by the peak hold circuit.

FIG. 5 shows a timing chart at points A, B, C, D, E, F and G in FIG.

Next, the detailed operation will be described with reference to FIGS.

The waveforms at the points A and B in FIG. 4 start at the point A where the signal 12 shown in FIG. 2 is directly connected, as shown in FIG. Further, at the point B, the rising timing is further delayed by the time Tn shown in FIG. At points C and D, resistors 19, 2
0 and a voltage divided by the resistors 22 and 23 are applied.

When the NPN transistor 21 is turned on, the point E becomes a low level as shown in FIG.
The PNP transistor 26 turns on.

When the PNP transistor 26 is turned on, a current flows from the emitter to the collector, and the waveform at the point F is increased by the time constant circuit of the resistor 27 and the capacitor 28 as shown in FIG.

When the NPN transistor 24 is turned on, a current flows from the base of the NPN transistor 21 to the collector of the NPN transistor 24.
The type transistor 21 is turned off.

When the NPN transistor 21 turns off,
As shown in FIG. 5, the point E becomes high, the PNP transistor 26 is turned off, and no current flows between the emitter and the collector, so that the waveform at the point F does not rise as shown in FIG.

Since the periphery of the operational amplifier 30 is a peak hold circuit, its output is as shown at point G in FIG.

That is, the NPN transistors 21 and 24
Can be obtained a difference voltage 15 corresponding to the time difference of turning on.

That is, for each pattern length 16-1, 16-2,..., 16-n between each output buffer and each receiver in FIG. 2, a differential voltage for each pattern length can be obtained. And pattern length 16-1>
If the pattern length is 16-2, the pattern length difference voltage of the signal 14-1> the pattern length difference voltage of the signal 14-2.

The variable delay buffers 10-1 and 10- in FIG.
2,..., 10-n assign an appropriate delay to each original oscillation signal for each output by the generated differential voltage signal.

The variable delay buffers 10-1 and 10-1
, 10-n will be described with reference to FIG.

In FIG. 6, operational amplifiers 36 and 37 are voltage comparing circuits. The resistors 32 and 33 generate the reference voltage of the operational amplifier 36, and the resistors 34 and 35 generate the reference voltage of the operational amplifier 37. Note that the reference voltage satisfies the following relationship: operational amplifier 36> operational amplifier 37.

The power supplies of the operational amplifiers 36 and 37 are
The side is connected to the internal power supply voltage, and the − side is grounded.

Reference numerals 38, 39 and 40 denote inverters for inverting the outputs of the operational amplifiers 36 and 37.

Numerals 41, 42 and 43 are NAND gates for inputting the results of the differential voltage judgment of the operational amplifiers 36 and 37.

Reference numerals 44, 45, and 46 denote delay buffers. Output ON / OFF is controlled by delay buffer enable terminals 47, 48, and 49. The output is on when the delay buffer enable terminal is at the ground level and off when it is at the high level.

The delay buffers 44, 45, 46
Each has a different delay value, and the magnitude of the delay is: delay buffer 44 <delay buffer 45 <delay buffer 46.

Next, the operation will be described for each differential voltage.

The differential voltage 15 is applied to operational amplifiers 36 and 37
The operational amplifiers 36, 37
Is at the ground level, only the output of the NAND gate 43 is at the ground level, and the signal 13 is output from the delay buffer 46. This state is before the differential voltage signal is output. In this state, the original oscillation signal 12 is output with the largest delay because the differential voltage is small.

The differential voltage 15 is applied to operational amplifiers 36 and 37
, The outputs of the operational amplifiers 36 and 37 are at the high level, only the output of the NAND gate 41 is at the ground level, and the signal 13 is output from the delay buffer 44. In this case, since the difference voltage is large, the original oscillation signal 12 is output with the smallest delay. When the differential voltage 15 is equal to or lower than the reference voltage of the operational amplifier 36 and equal to or higher than the reference voltage of the operational amplifier 37, the output of the operational amplifier 36 is at the ground level, the output of the operational amplifier 37 is at the high level, only the output of the NAND gate 42 is at the ground level, A signal 13 is output. In this state, the differential voltage 15 is greater than
In the following case, the delay according to the
And output.

As described above, the signals 13-1, 13-2,
, 13-n. That is,
In FIG. 2, pattern length 16-1> pattern length 16-2
Then, the output of the variable delay buffer 10-1 is output earlier than the output of the variable delay buffer 10-2.

In the same delay output buffer of FIG.
,..., 8-n are input and output, and the receivers 9-1, 9-2,.
For n, a signal having no delay difference can be input.

[0045]

As described above, the clock generator according to the present invention includes the comparator for generating the differential voltage from the reflected waveform of the buffer output line, and the variable delay buffer for varying the delay from the differential voltage. Thus, an output delay corresponding to the pattern length to each receiver can be given.

[Brief description of the drawings]

FIG. 1 is an internal block diagram of a conventional clock generator and a system configuration diagram using the same.

FIG. 2 is an internal block diagram of a clock generator according to the present invention and a system configuration diagram using the same.

FIG. 3 is a waveform model diagram at an output buffer end in FIG. 2;

FIG. 4 is an internal circuit diagram of a comparator inside the clock generator of the present invention.

FIG. 5 is an internal waveform timing chart of FIG. 4;

FIG. 6 is an internal circuit diagram of a variable delay buffer inside the clock generator of the present invention.

[Explanation of symbols]

1 Conventional clock generator 2-1 ... 2-n output buffer 3-1 ... 3-n receiver 4 Original oscillation signal 5-1 ... 5-n Clock generator output signal 6-1 ... 6-n Between output buffer and receiver Pattern length 7 Clock generator of the present invention 8-1 ... 8-n Same delay output buffer 9 Receiver 10-1 ... 10-n Variable delay buffer 11 Comparator 12 Original oscillation signal 13-1 ... 13-n Variable delay buffer output signal 14-1 ... 14-n Clock generator output signal 15-1 ... 15-n Differential voltage signal 16-1 ... 16-n Pattern length between output buffer receivers 18 Signal at output buffer end 19,20,22,23 Voltage Voltage resistance 21, 24 NPN transistor 25 Current control resistor 26 PNP transistor 27 Time constant determination resistor 2 Time constant determining capacitor 29 Reverse current preventing diode 30 Operational amplifier 31 Difference voltage signal 32, 33, 34, 35 Reference voltage determining resistor 36, 37 Operational amplifier 38, 39, 40 Inverter 41, 42, 43 NAND circuit 44 Small delay output Buffer with control 45 Buffer with output control during delay 46 Buffer with large delay output control 47, 48, 49 Buffer enable terminal with output control

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 1/10 G01R 31/28

Claims (2)

(57) [Claims] An output buffer of a clock generator,
The pattern length up to the receiver connected to the output
Detected by the rising waveform of the reflected waveform of
Output timing for each output buffer
Control the skew between each receiver.
Clock generators that can be monitored at each output buffer end in the clock generator.
The rising waveform of the reflected waveform from each receiver end
Comparator for obtaining the pattern length difference, and the output voltage of each buffer by the difference voltage based on the comparison result
Variable delay buffer that can delay
Have the comparator to detect the rising edge of the oscillation signal to the clock generator
The first transistor is turned on when the signal rises, and the first transistor is turned on when a signal rising at the receiver end is detected.
A second transistor and a time difference for turning on the first and second transistors;
And a peak hold circuit that obtains a differential voltage according to the clock generator. 2. A variable delay buffer comprising : a plurality of operational amplifiers for comparing the differential voltage with a plurality of reference voltages to determine a level of the differential voltage; a plurality of delay buffers for assigning different delays to the original oscillation signal; The clock generator according to claim 1 , further comprising: a selection circuit that selects the delay buffer based on an output of the operational amplifier.