TWI655839B - Integrated circuit and driving signal generation circuit - Google Patents

Abstract

The present invention provides an integrated circuit and a drive signal generating circuit. The integrated circuit includes a drive signal generating circuit. The drive signal generating circuit includes a signal processing circuit, an output drive circuit, and a compensation signal generating circuit. The signal processing circuit performs signal processing on the first control signal to generate a second control signal. The output driving circuit receives the second control signal and the compensation signal, and generates a driving signal according to the compensation signal. The drive signal is used, for example, to drive the rotor. The compensation signal generating circuit generates a compensation signal according to the first transition point of the first control signal, the second transition point, and the third transition point of the driving signal and the fourth transition point.

Description

Integrated circuit and drive signal generating circuit

The present invention relates to an integrated circuit and a drive signal generating circuit thereof, and more particularly to an integrated circuit capable of avoiding distortion of a drive signal and a drive signal generating circuit therefor.

Generally, after receiving the control signal, the drive circuit performs signal processing on the control signal and then outputs it to drive the device of the next stage. However, when the ambient temperature or humidity changes, or because of the conversion of the control signal, such as raising/lowering the voltage level, etc., it is possible to cause the conduction waveform of the control signal to change, thereby causing distortion of the control signal. .

The present invention provides an integrated circuit and a drive signal generating circuit. The drive signal generating circuit of the integrated circuit can avoid distortion of the drive signal, thereby stably driving the rotor.

The driving signal generating circuit of the present invention comprises a signal processing circuit and an output driver The dynamic circuit and the compensation signal generating circuit. The signal processing circuit receives the first control signal and performs signal processing on the first control signal to generate a second control signal. The output drive circuit is coupled to the signal processing circuit. The output driving circuit receives the second control signal and the compensation signal, and generates a driving signal according to the compensation signal. The compensation signal generating circuit is coupled to the signal processing circuit and the output driving circuit. The compensation signal generating circuit detects the adjacent first transition point and the second transition point of the first control signal in the detection time interval, and detects the adjacent third transition point and the fourth transition point of the driving signal . The compensation signal generating circuit generates a compensation signal according to the first transition point, the second transition point, the third transition point, and the fourth transition point.

The integrated circuit of the present invention includes the above-described drive signal generating circuit. The drive signal generating circuit is configured to generate a drive signal for driving the rotor.

Based on the above, the driving signal generating circuit of the present invention receives the first control signal, performs signal processing on the first control signal to generate a second control signal, and adjusts the phase of the second control signal according to the compensation signal to generate a driving signal. And the driving signal generating circuit generates the compensation signal according to the first control signal and detecting a plurality of transition points of the driving signal. In this way, the integrated circuit has the function of a self-compensation mechanism, so that the driving signal of the driving signal generating circuit can be automatically adjusted back to maintain a stable conducting waveform to avoid distortion of the driving signal.

The above described features and advantages of the invention will be apparent from the following description.

100‧‧‧Drive signal generation circuit

120‧‧‧Signal Processing Circuit

140, 240, 340‧‧‧ output drive circuit

160‧‧‧Compensation signal generation circuit

142, 242, 342‧‧‧ output stage circuits

144‧‧‧Delay circuit

1422‧‧‧First drive switch

1424‧‧‧Second drive switch

244, 344‧‧‧ rising current source

246, 346‧‧‧ falling current source

3422, 3424‧‧‧ buffer

AS‧‧‧compensation signal

EG1~EG4‧‧‧Transition point

TA1, TA3‧‧‧ first time

TA2, TA4‧‧‧ second time

X1, x2, y1~y3, y’3, z4, z’4‧‧‧ time

T1, T2, T3‧‧ ‧ time interval

CS1‧‧‧First control signal

CS2‧‧‧second control signal

DS‧‧‧ drive signal

Rtr‧‧‧ rotor

RGT‧‧‧ integrated circuit

VB‧‧‧reference voltage

VS‧‧‧ grounding voltage

DCS‧‧‧ Delay Control Signal

DCS1‧‧‧First Delay Control Signal

DCS2‧‧‧second delay control signal

D1(1)~D1(m)‧‧‧First retarder

D2(1)~D2(n)‧‧‧second retarder

SW1(0)~SW1(m)‧‧‧ first switch

SW2(0)~SW2(n)‧‧‧second switch

FIG. 1 is a circuit diagram of an integrated circuit according to an embodiment of the invention.

2A-2C are waveform diagrams of control signals and driving signals according to an embodiment of the invention.

FIG. 3A is a schematic diagram of an output driving circuit according to a first embodiment of the present invention.

FIG. 3B is a schematic diagram of an output driving circuit according to the embodiment of FIG. 3A.

4A is a schematic diagram of an output driving circuit according to a second embodiment of the present invention.

4B is a schematic diagram of an output driving circuit according to a third embodiment of the present invention.

Please refer to FIG. 1. FIG. 1 is a schematic circuit diagram of an integrated circuit according to an embodiment of the invention. In the present embodiment, the integrated circuit RGT includes a drive signal generating circuit 100. The drive signal generating circuit 100 is configured to generate the drive signal DS. The drive signal generating circuit 100 includes a signal processing circuit 120, an output drive circuit 140, and a compensation signal generating circuit 160. The signal processing circuit 120 is configured to receive the first control signal CS1, and the signal processing circuit 120 performs signal processing on the first control signal CS1 to generate the second control signal CS2. In this embodiment, the signal processing circuit 120 can Signal processing is performed for the first control signal CS1, and at least one of a surge cancellation operation and a short circuit protection operation is performed. The output driving circuit 140 is coupled to the signal processing circuit 120. The output drive circuit 140 receives the second control signal CS2 and the compensation signal AS. The output driving circuit 140 can generate the driving signal DS by adjusting the phase of the second control signal CS2 according to the compensation signal AS. In the present embodiment, the integrated circuit RGT may be, for example, a vehicle regulator, and generates a drive signal DS to drive an inductive load (for example, a rotor Rtr).

In the present embodiment, the compensation signal generating circuit 160 is coupled to the signal processing circuit 120 and the output driving circuit 140. The compensation signal generating circuit 160 detects the first control signal CS1 and detects the driving signal DS to generate the compensation signal AS. The compensation signal generating circuit 160 can detect the adjacent first transition point and the second transition point in the first control signal CS1 in the detection time interval, and detect in the detection time interval. The adjacent third transition point and the fourth transition point in the drive signal DS. The first transition point and the third transition point may be the same type of transition point, for example, a transition point from a low voltage level to a rising edge of the high voltage level. The second transition point and the fourth transition point may be the same type of transition point, for example, a transition point from a high voltage level to a falling edge of the low voltage level.

The compensation signal generating circuit 160 can generate the compensation signal AS according to calculating the length of time between the transition points. For example, the compensation signal generating circuit 160 may generate the compensation signal AS according to the length of time between the first transition point and the second transition point, and the length of time between the third transition point and the fourth transition point. Alternatively, the compensation signal generating circuit 160 may also be based on the length of time between the first transition point and the third transition point. The short, and the length of time between the second transition point and the fourth transition point, produces a compensation signal AS.

For further explanation, please refer to FIG. 1 and FIG. 2A simultaneously. FIG. 2A is a schematic diagram of waveforms of a control signal and a driving signal according to an embodiment of the invention. In this embodiment, the compensation signal generating circuit 160 can detect the first transition point EG1 in the first control signal CS1 and the second transition state adjacent to the first transition point EG1 in the detection time interval. Point EG2. And the compensation signal generating circuit 160 calculates the first time TA1=x2-x1 according to the time length between the time x1 at which the first transition point EG1 occurs and the time x2 at which the second transition point EG2 occurs, wherein the first time TA1 is equal to the first time The positive pulse width of a control signal CS1. The compensation signal generating circuit 160 further detects the third transition point EG3 of the driving signal DS and the fourth transition point EG4 adjacent to the third transition point EG3. The compensation signal generating circuit 160 calculates a second time TA2=y2-y1 according to the time length between the time y1 at which the third transition point EG3 occurs and the time y2 at which the fourth transition point EG4 occurs, wherein the second time TA2 is equal to the drive The positive pulse width of the signal DS.

In this embodiment, the compensation signal generating circuit 160 can perform a sampling operation between the first transition point EG1 and the second transition point EG2 of the first control signal CS1 through a sampling clock, and generate a corresponding first time TA1. The first count value CA1. Moreover, the compensation signal generating circuit 160 can perform a sampling operation between the third transition point EG3 and the fourth transition point EG4 of the driving signal DS through the sampling clock, and generate a second count value CA2 corresponding to the second time TA2.

In accordance with the above description, the compensation signal generating circuit 160 can be used for the first meter. The numerical value CA1 and the second count value CA2 perform an arithmetic operation, and generate a compensation signal AS in accordance with the result of the arithmetic operation. Specifically, the compensation signal generation circuit 160 can perform the subtraction operation on the first count value CA1 and the second count value CA2, and learn the difference between the first control signal CS1 and the drive signal DS by the difference obtained by the subtraction operation. The difference between the lengths of the pulses. In this way, the compensation signal generating circuit 160 can perform a delay or advance adjustment operation on the transition point of the second control signal CS2 according to the difference between the lengths of the positive pulses of the first control signal CS1 and the driving signal DS, and thereby A compensation signal AS is generated.

In another embodiment of the present invention, the compensation signal generating circuit 160 calculates a time x1 in which the first transition point EG1 occurs in the first control signal CS1 and a time y1 in the drive signal DS where the third transition point EG3 occurs. The length of time, and by which the first time TA3 = y1 - x1 is calculated. Further, the compensation signal generating circuit 160 calculates the time length between the time x2 at which the second transition point EG2 occurs in the first control signal CS1 and the time y2 at which the fourth transition point occurs in the drive signal DS, and thereby calculates the Two times TA4=y2-x2. Moreover, the compensation signal generating circuit 160 can obtain the difference of the positive pulse recompensation between the first control signal CS1 and the driving signal DS by calculating the difference between the first time TA3 and the second time TA4. In this way, the compensation signal generating circuit 160 can adjust the second control signal CS2 according to the difference between the first time TA3 and the second time TA4, and thereby generate the compensation signal AS.

In the embodiment of the present invention, the compensation signal generating circuit 160 may sample between the first transition point EG1 of the first control signal CS1 and the third transition point EG3 of the driving signal DS according to the sampling clock, and obtain a corresponding correspondence. The first time TA3 a count value CA3, and sampling between the second transition point EG2 of the first control signal CS1 and the fourth transition point EG4 of the drive signal DS according to the sampling clock to obtain a second count value CA4 corresponding to the second time TA4. . Thus, by calculating the difference between the first count value CA3 and the second count value CA4, the compensation signal generating circuit 160 can know the difference between the positive pulse width of the first control signal CS1 and the driving signal DS, and thus, the compensation signal The generating circuit 160 can generate the compensation signal AS by adjusting the transition point of the second control signal CS2 according to the difference between the first count value CA3 and the second count value CA4.

On the other hand, when the compensation signal generating circuit 160 determines that the first pulse width of the first control signal CS1 and the driving signal DS are the same, the compensation signal generating circuit 160 can directly generate the compensation signal AS according to the second control signal CS2, and The adjustment operation is not performed for the phase of the second control signal CS2. That is to say, in the case where the length of time of the second time is equal to the length of time of the first time, the compensation signal AS is substantially the same signal as the second control signal CS2.

Regarding the sampling operation described above, the frequency value of the set sampling clock has a correlation with the adjustment accuracy of the driving signal generating circuit 100. For example, if the sampling clock frequency is 5 MHz and the positive clock width of the first control signal CS1 is 4 milliseconds, the adjustment precision of the driving signal generating circuit 100 can reach the first time of the first control signal CS1. 0.005%. It is worth noting that the frequency value of the sampling clock can be selected according to the requirement of the accuracy of the time length calculation, and there is no particular limitation.

Please refer to FIG. 1 , FIG. 2B and FIG. 2C simultaneously. FIG. 2B and FIG. 2C are waveform diagrams of control signals and driving signals according to different embodiments of the present invention. intention. In FIG. 2B, the compensation signal generating circuit 160 determines the signal processing process of the delay control time interval T2 when the detection pulse time interval T1 determines that the positive pulse wave length of the first control signal CS1 is smaller than the positive pulse wave length of the drive signal DS. The compensation signal generating circuit 160 can generate the compensation signal AS based on the above-described determination result. And in the compensation time interval T3, the time of the transition point of the rising edge of the driving signal DS (the third transition point EG3 shown in FIG. 2A) is adjusted, and the time y3 is adjusted from the original time y3, and Thereby, the positive pulse length of the drive signal DS is reduced. The positive pulse length of the drive signal DS can be made substantially the same as the positive pulse length of the first control signal CS1.

In FIG. 2C, the compensation signal generating circuit 160 determines the signal processing process of the delay control time interval T2 when the detection pulse time interval T1 determines that the positive pulse wave length of the first control signal CS1 is greater than the positive pulse wave length of the drive signal DS. The compensation signal generating circuit 160 can generate the compensation signal AS based on the above-described determination result. And in the compensation time interval T3, the time of the transition point of the falling edge of the driving signal DS (the fourth transition point EG4 shown in FIG. 2A) is adjusted, and the time z4 is adjusted from the original time z4, and Thereby, the positive pulse length of the drive signal DS is increased. The positive pulse length of the drive signal DS can be made substantially the same as the positive pulse length of the first control signal CS1.

Please refer to FIG. 3A. FIG. 3A is a schematic diagram of an output driving circuit according to an embodiment of the invention. In the present embodiment, the output drive circuit 140 includes an output stage circuit 142 and a delay circuit 144. The delay circuit 144 receives the second control signal CS2 and adjusts the phase of the second control signal CS2 in accordance with the compensation signal AS to generate the delay control signal DCS. Delay circuit 144 and pass delay control signal DCS It is sent to the output stage circuit 142. The output stage circuit 142 receives the delay control signal DCS and generates a drive signal DS in accordance with the delay control signal DCS.

For details of the operation of the output driving circuit 140, please refer to FIG. 3B, which is a schematic diagram of the output driving circuit 140 according to the embodiment of FIG. 3A. The output stage circuit 142 includes a first drive switch 1422 and a second drive switch 1424. The delay circuit 144 is coupled between the output stage circuit 142 and the signal processing circuit 120 of FIG. The first end of the first driving switch 1422 is coupled to the reference voltage VB. The second end of the first driving switch 1422 is coupled to the first end of the second driving switch 1424. The second end of the second driving switch 1424 is coupled to the ground voltage VS.

In this embodiment, the first driving switch 1422 and the second driving switch 1424 are respectively used to determine the turning point of the rising edge of the driving signal DS (the third turning point EG3 shown in FIG. 2A) and the turning of the falling edge. The occurrence time of the state point (the fourth transition point EG4 as shown in Fig. 2A). Therefore, the phase adjustment operation of the drive signal DS can be performed by adjusting the enable times of the first delay control signal DCS1 and the second delay control signal DCS2.

In addition, the delay circuit 144 includes first delays D1(1) to D1(m), second delays D2(1) to D2(n), first switches SW1(0) to SW1(m), and a second switch. SW2(0)~SW2(n). The first delays D1(1) to D1(m) are coupled in series and coupled between the output stage circuit 142 and the signal processing circuit 120. The input end of the first delay D1(1) is coupled to the input of the delay circuit 144 and receives the second control signal CS2. The output end of the first delay D1 (m) is coupled to the control end of the first driving switch 1422 and is used to output a first delay control signal DCS1. Second retarder D2(1)~D2(n) are coupled in series and coupled between the output stage circuit 142 and the signal processing circuit 120. The input end of the second delay D2 (1) is coupled to the input of the delay circuit 144 and receives the second control signal CS2. The output of the second delay D2(n) is coupled to the control end of the second drive switch 1424 and is used to output a second delay control signal DCS2.

On the other hand, the first switch SW1(0) is coupled between the input end of the first delay D1(1) and the control end of the first drive switch 1422, and the first switch SW1(1)~SW1(m) Then, they are connected in series between the input ends of the first delay devices D1(1) to D1(m) and the control terminals of the first driving switch 1422. The second switch SW2(0) is coupled between the input end of the second delay D2(1) and the control end of the second drive switch 1424, and the second switches SW2(1)~SW2(n) are respectively connected in series The input ends of the second retarders D2(1) to D2(n) and the control terminals of the second drive switches 1424. The first switches SW1(0) to SW1(m) and the second switches SW2(0) to SW2(n) are turned on or off according to the compensation signal AS.

In this embodiment, the number of the first delays D1(1) to D1(m) and the second delays D2(1) to D2(n) may be the same or different, and the first switches SW1(0)~SW1 The number of (m) and the second switches SW2(0) to SW2(n) may be the same or different. In addition, each of the first retarders D1(1) to D1(m) and the second retarders D2(1) to D2(n) can provide the same time delay.

Regarding the operation details of the output driving circuit 140, if the transition point of the rising edge of the driving signal DS (the third transition point EG3 shown in FIG. 2A) is to be adjusted, the first switch SW1 may be selected according to the compensation signal AS. (1)~SW1(m) One of them (taking the first switch SW1(1) as an example) is turned on, and the unselected first switches SW1(0), SW1(2)~SW1(m) are turned off. In this way, the output driving circuit 140 can generate the first delay control signal DCS1 through the first delay D1(1) to delay the second control signal CS2 by a time delay. Here, if the first switch SW1 (3) is selected to be turned on, the output driving circuit 140 can generate the first time by delaying the three delays of the second control signal CS2 through the first delays D1(1) to D1(3). Delay control signal DCS1.

Further, if adjustment is not required for the transition point of the rising edge of the drive signal DS (the third transition point EG3 as shown in FIG. 2A), the first switch SW1(0) may be selectively turned on.

On the other hand, if the transition point of the falling edge of the driving signal DS (the fourth transition point EG4 shown in FIG. 2A) is to be adjusted, the second switch SW2(1) can be selected according to the compensation signal AS~ One of SW2(n) (taking the second switch SW2(1) as an example) to turn on, and the second switch SW2(0), SW2(2)~SW2(n) that are not selected Was disconnected. In this way, the output driving circuit 140 can generate the second delay control signal DCS2 through the second delay D2 (1) to delay the second control signal CS2 by a time delay. Here, if the second switch SW2 (3) is selected to be turned on, the output driving circuit 140 can generate the second by delaying the three delays of the second control signal CS2 through the second delays D2(1) to D2(3). Delay control signal DCS2.

Further, if adjustment is not required for the transition point of the falling edge of the drive signal DS (the fourth transition point EG4 as shown in FIG. 2A), the second switch SW2(0) may be selectively turned on.

4A and FIG. 4B are schematic diagrams showing different embodiments of an output driving circuit according to an embodiment of the invention. In FIG. 4A, output drive circuit 240 includes an output stage circuit 242 and a current source (including rising current source 244 and falling current source 246). The output stage circuit 242 is used to generate the drive signal DS. The output stage circuit 242 of this embodiment may be constructed by one or more buffers coupled in series with each other, wherein the buffer may also be an inverter. The rising current source 244 and the falling current source 246 can be constructed by current source circuits well known to those of ordinary skill in the art. The rising current source 244 is coupled between the output stage circuit 242 and the reference voltage VB. The falling current source 246 is coupled between the output stage circuit 242 and the ground voltage VS. The rising current source 244 and the falling current source 246 receive the compensation signal AS for controlling the phase of the driving signal DS according to the compensation signal AS. For example, the rising current source 244 can increase or decrease the current value of the rising current source 244 according to the compensation signal AS, thereby further adjusting the transition point of the rising edge of the driving signal DS (the third transition point EG3 as shown in FIG. 2A). )time. For another example, the falling current source 246 can increase or decrease the current value of the falling current source 246 according to the compensation signal AS, thereby shortening the transition point of the falling edge of the driving signal DS (the fourth transition point EG4 shown in FIG. 2A). )time.

Further, in FIG. 4B, unlike FIG. 4A, the output stage circuit 342 of the output drive circuit 340 of the present embodiment includes buffers 3422, 3424. The buffer 3422 receives the second control signal CS2. The output of the buffer 3422 is coupled to the input of the buffer 3424. The rising current source 344 is coupled between the buffer 3422 and the reference voltage VB. The falling current source 346 is coupled to the buffer 3424 and the ground voltage VS between. The buffer 3424 is used to generate the drive signal DS. For example, the rising current source 344 can adjust the current value of the rising current source 344 according to the compensation signal AS, thereby adjusting the transition point of the rising edge of the driving signal DS output by the buffer 3422 (third in FIG. 2A). The time of the transition point EG3). Then, the falling current source 346 can adjust the current value of the falling current source 346 according to the compensation signal AS, thereby adjusting the transition point of the falling edge of the driving signal DS output by the buffer 3424 (the fourth transition state as shown in FIG. 2A). Point EG4) time.

In summary, the driving signal generating circuit of the present invention compensates the driving signal by detecting the difference between the pulse width of the received first control signal and the output driving signal. In this way, the integrated circuit has the function of a self-compensation mechanism, so that the driving signal of the driving signal generating circuit can be automatically adjusted back to a stable waveform to avoid distortion of the driving signal.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

Claims (12)

A driving signal generating circuit includes: a signal processing circuit that receives a first control signal and performs a signal processing on the first control signal to generate a second control signal; an output driving circuit coupled to the signal processing The circuit receives the second control signal and a compensation signal, and generates a driving signal according to the compensation signal; and a compensation signal generating circuit coupled to the signal processing circuit and the output driving circuit in a detection time interval Detecting a first transition point and a second transition point adjacent to the first control signal, detecting a third transition point and a fourth transition point adjacent to the driving signal, and The first transition point, the second transition point, the third transition point, and the fourth transition point generate the compensation signal. The driving signal generating circuit of claim 1, wherein the output driving circuit adjusts a phase of the second control signal according to the compensation signal to generate the driving signal, wherein the first transition point is the first a rising edge of the control signal, wherein the second transition point is a falling edge of the first control signal, wherein the third transition point is a rising edge of the driving signal, wherein the fourth transition point is the driving signal Falling edge. The driving signal generating circuit of claim 2, wherein the compensation signal generating circuit calculates a first time between the first transition point and the second transition point, and calculates the third transition point. And a second time between the fourth transition point, and comparing the first time and the second time to generate the compensation signal. The driving signal generating circuit of claim 3, wherein the compensation signal generating circuit obtains a first count value according to a sampling clock and the first time, according to the sampling clock and the second time Obtaining a second count value, and performing a subtraction operation on the first count value and the second count value to obtain an operation result, and providing the compensation signal according to the operation result. The driving signal generating circuit of claim 2, wherein the compensation signal generating circuit calculates a first time between the first transition point and the third transition point, and calculates the second transition point And a second time between the fourth transition point, and comparing the first time and the second time to generate the compensation signal. The driving signal generating circuit of claim 1, wherein the output driving circuit comprises: an output stage circuit comprising a first driving switch coupled in series and a second driving switch for generating the driving signal And a delay circuit coupled between the output stage circuit and the signal processing circuit, adjusting a phase of the second control signal according to the compensation signal to generate a delay control signal, wherein the delay control signal is used to drive the first A drive switch and the second drive switch generate the drive signal. The driving signal generating circuit of claim 6, wherein the delay circuit comprises: a plurality of first delays coupled between the output stage circuit and the signal processing circuit, the first delays being connected in series a plurality of first switches are respectively coupled between the output ends of the first delays and the output stage circuit; a plurality of second delays coupled between the output stage circuit and the signal processing circuit The second delays are coupled to each other in series; and the plurality of second switches are respectively coupled between the output ends of the second delays and the output stage circuit. The driving signal generating circuit of claim 7, wherein the first delays provide the same time delay, wherein the second delays provide the same time delay, wherein the first switches are And being turned on according to the compensation signal, wherein one of the second switches is turned on according to the compensation signal. The driving signal generating circuit of claim 1, wherein the output driving circuit comprises: an output stage circuit that receives the second control signal to generate the driving signal; and a current source coupled to the output stage Between the circuit and the path of the supply voltage, wherein the current source is used to control the phase of the drive signal. The driving signal generating circuit of claim 9, wherein the current source comprises: a rising current source coupled between the output stage circuit and a reference voltage, and receiving the compensation signal for relieving the compensation a signal is used to control a rising edge of the driving signal; and a falling current source is coupled between the output stage circuit and a ground voltage, and receives the compensation signal for controlling a falling edge of the driving signal according to the compensation signal Time point. The driving signal generating circuit of claim 1, wherein the signal processing is at least one of a surge canceling operation and a short circuit protecting operation on the first control signal. An integrated circuit, comprising: a driving signal generating circuit according to any one of claims 1 to 11, wherein the driving signal generating circuit is configured to generate the driving signal for driving a rotor .