JPH03240313A - Output circuit - Google Patents

Abstract

PURPOSE:To prevent the generation of noise while keeping the drive capability of an output transistor(TR) as it is by providing a constant current circuit in an inverter driving the output TR. CONSTITUTION:A TR Q12 provided on an inverter IV-1 applies constant current drive to the rise of a gate potential of a P-channel TR Q9 being an output TR. Moreover, a TR Q11 provided on an inverter IV-2 applies constant current drive to the rise of the gate potential of an N-channel TR Q10 being an output TR. Thus, the speed in a change in the gate voltage of the output TR is reduced, thereby preventing a rapid increase/decrease in the drain current. In this case, the driving speed of the output TR is more or less sacrificed but the driving capability is maintained. Then no noise is generated and malfunction is decreased. Furthermore, a constant current circuit may be provided between the output terminal of an inverter driving the output TR and the gate of the output TR.

Description

[Detailed Description of the Invention] [Summary] Regarding the output circuit, a constant current circuit is installed in the inverter that drives the output transistor in order to prevent the generation of noise and malfunction of the device due to the current during charging and discharging of the load. Alternatively, a constant current circuit may be provided between the output end of the inverter that drives the output transistor and the gate portion of the output transistor.

(Industrial application field) The present invention relates to output circuits for integrated circuits.

[Conventional technology]

Integrated circuits generally output signals to the outside, so they are equipped with fairly large transistors for signal output. In recent years, as devices have become more integrated and faster, the influence of noise generated by the charging and discharging currents of their output transistors has become greater and has become a problem not only in systems equipped with the devices but also inside the devices.

FIG. 3 shows an example of a general output circuit, in which the output section 2 includes a P-channel transistor Q and an N-channel transistor Q, each having a C-1'lOs structure. It consists of
Also, each output transistor Q? The gates of IQIO are respectively connected to the outputs of inverters IV-1, 1 and 2, which are drivers, thereby driving an external load CL connected to the output terminal N of the output section 1.

On the other hand, the input DATA is connected to the inverters 1-3 and IV-4 through one of the NANO gate 2 and the NOR gate 3, respectively, and the inverter IV-3 is connected to the inverter IV-1 and the inverter IV-4. 4 are respectively connected to the inverters 1-2.

Furthermore, a signal that makes the output part 1 high impedance is input to one side of the NOR gate 3, and the NAND gate 2
The above-mentioned Hz signal is inputted to one input via an inverter 4.

In addition, in this circuit, when the human key is "L 11", the DATA
According to the logic, the external load CL connected to the output section 1 is charged and discharged, but when the voltage is °°H'', both transistors Q, , Q, of the output section 1 are cut off and are in a high impedance state. Become.

In such a conventional circuit example, since the inverter transition occurs rapidly, the level change of the output transistors Q9+Q1° also occurs quickly, and there is a problem that charging and discharging of the external load occurs rapidly. Output transistor Qq+Q
Because ro drives a load, its driving capacity is originally large, so this will have an effect.

In addition, in such a circuit, the power supply voltage VC of the transistor
When C is increased, the conductance of the transistor (
gm) increases, that is, the current drive capability increases, so the amplitude of the change becomes even larger, and the instantaneous current also increases.

On the other hand, VS2 shown in the above circuit example indicates VSS in the circuit of the chip 5 as shown in FIG. I will be leaving. Since the lead 7 has a considerable length, its inductance (L) causes the device VssiiEif to change sharply.
i will shake a lot and cause noise.

Also, by increasing the circuit voltage VCC, the circuit operation itself becomes faster, but the noise also increases, so the noise effect becomes more accentuated.

[Problem to be solved by the invention]

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-described drawback of the prior art in that noise occurs during transition in the output transistor of an integrated circuit, and to provide an output circuit that can prevent the generation of noise while maintaining the driving ability of the output transistor. It is something to do.

[Means to solve the problem]

In order to achieve the above object, the present invention employs the following technical configuration.

That is, the output circuit has a constant current circuit in an inverter that drives the output transistor, or a constant current circuit is provided between the output end of the inverter that drives the output transistor and the gate of the output transistor.

In other words, in the present invention, as described above, the main causes of fluctuations in the power supply (VSS) when driving the output transistor are the parasitic inductance of the system power supply line and the inductance of the package leads during charging and discharging of the load. This is because changes in the current in the power supply line act and generate electromotive force. Also, as the voltage VCC increases, the influence of noise increases on the output transistors Q, ,Q,. The fall and rise of the gate voltage become steeper, and the amount of charge and discharge increases, so ■
. .

This is because the amount of change in the current flowing into the current increases.

Based on this knowledge, in order to eliminate the cause of noise generation while maintaining the drive capability of the output transistor, the transistors Q, , Q, in the output transistor section are designed.

The structure is such that the rise or fall of the gate voltage is driven by a constant current source, and the rise or fall speed is changed slowly, for example, to optimize the speed of the rise or fall. The slope of the rise of the current flowing through VSS is t conductive voltage ■. , is configured so that it does not change even if , changes.

[For production]

In the present invention, since a constant current circuit is connected to the gate of each transistor constituting the output transistor section, the rate of change in the rise or fall of the gate voltage is slow, and therefore the change in the current flowing from the load to VSS is slow. Since the slope becomes gentle, the generation of the above-mentioned noise is suppressed, and the slope of the current change does not change even when VCC changes.

Therefore, the driving ability of the output transistor can be maintained, but the driving speed is reduced, but overall, the driving speed is improved by the reduction in noise.

〔Example〕

A specific example and principle of the output circuit according to the present invention will be explained below with reference to FIG.

FIG. 1 shows a specific example of an output circuit suitable for implementing the present invention.

As described above, in the present invention, the slope of the drain current flowing to VSS is made constant, and preferably the power supply voltage VCC
In order to keep the voltage constant even when the gate voltage changes, it is sufficient to make the slope of the rise or fall of the gate voltage constant in each transistor.To do this, it is sufficient to drive the gate voltage with a constant current. Become.

In other words, as shown in Fig. 5, the drain current-drain voltage characteristic of a MOS transistor changes using the gate voltage VSS as a parameter, but it generally operates in a saturated state, so for example, if VCC is 5V, If the gate voltage is increased or decreased around this point, the slope of the drain current can be controlled to be approximately constant.

Therefore, in the present invention, a constant current circuit is provided between the inverter of the drive circuit for the output transistor driven by the inverter and the gate of the output transistor.

The constant current circuit in the present invention may be provided within the inverter circuit, or may be provided between the inverter and the gate of the output transistor.

FIG. 1 shows an example of the former.

That is, the output circuit shown in FIG. 1 is basically the same as the conventional output circuit shown in FIG.
1 or 1■-2 between both transistors Q, and Q, or Q, and Q.

A depletion type transistor Q, and Q lz
are inserted in series, and the gate voltage of the transistor is configured to be the same potential as the source voltage.

The transistors Q + + and Qlz in FIG. 1 are constant current circuits in the present invention.

In the present invention, the transistor Q12 provided in the inverter 1V-1 drives the falling gate potential of the P-channel transistor Q, which is an output transistor, with a constant current, and the transistor Q12 provided in the inverter IV-2 The transistor Q drives the rise of the gate potential of the N-channel transistor QIO, which is an output transistor, with a constant current.

The constant current circuit used in the present invention is not particularly limited, and any circuit known as a constant current drive source can be used. For example, any constant current circuit that has a characteristic that the drain current does not change even if the drain voltage changes can be used.

Another example of the output circuit according to the present invention will be explained with reference to FIG.

Unlike FIG. 1, FIG. 2 shows an example in which a constant current circuit is placed between the inverter and the gate of the output transistor. A depletion type transistor Q Ill+ Q+a is inserted in series between the transistor Q I 31 Q + and the gate voltage of the transistor Q I 31 Q + 4 is a constant current circuit.

Further, in the present invention, an example has been shown in which the output transistor section has a C-MO3 structure, but the present invention is not necessarily limited to this, and in some cases, only the discharge of the external load CL may be used. It may be configured only with the output transistor Q r o on the ground side or GND side that drives the output transistor Q r o .

Further, even if the output transistor is a C-MOS type, it is not necessarily necessary to drive the gate voltage of both output transistors with a constant current, and only one of them may be driven.

As described above, it is preferable to drive at least a constant current to the gate of the output transistor on the ground side.

In other words, it is preferable to apply at least the present invention to a circuit in which it is necessary to reduce the generation of noise by delaying the time for discharging to the ground side.

Depending on the multi-circuit, it is strong against GND noise, but VCC
At least ■ for circuits that are sensitive to side noise, such as sense amplifiers. , it is preferable to apply the present invention to the side.

Further, it is only necessary to appropriately decide which noise the present invention is applied to depending on which noise the input characteristics are susceptible to.

Although the above specific example has been explained with respect to FET transistors, the technical concept of the present invention is not limited to only FET transistors, but is also applicable to cases where bipolar transistors are used.

Since the constant current circuit in the present invention has a negative effect on the driving ability of the transistor, it is desirable that the number of constant current circuits used be as small as possible. Furthermore, in the present invention, by changing the size of these debris transistors, the rise and fall speeds of the gate voltage can be adjusted. Also, when determining the actual size, consider the inductance size and the change in power supply current when charging and discharging the load, and change the W/L so that the internal circuit or other parts of the system do not malfunction. The size can be determined by

As an actual value, when the size of the P-channel output transistor is 200/1.5 and the size of the N-channel output transistor is 100/1.5, the change in gate voltage from O to 5V is about ~6nS. It was confirmed that malfunctions would not occur in normal dip-type packages.

〔effect〕

In the present invention, by slowing down the rate of change of the gate voltage of the output transistor by driving with a constant current, it is possible to prevent the drain current from increasing or decreasing rapidly. A circuit is obtained. In addition, in the present invention, although the driving speed of the output transistor is sacrificed to some extent, the driving capability of the output transistor itself can be maintained, and if the reduction in noise generation due to the delay in the driving speed is taken into account, the overall speed can be improved. , it is thought that the drive performance of the output transistor can be sufficiently brought out when viewed from the outside.

[Brief explanation of drawings]

FIG. 1 is a diagram illustrating a specific example and principle of an output circuit according to the present invention. FIG. 2 is a diagram showing another specific example according to the present invention. FIG. 3 is a diagram showing an example of a conventional output circuit. FIG. 4 is a diagram showing a package mounted with a chip. FIG. 5 is a diagram showing the drain voltage-drain current characteristics of the output transistor. ■... Output transistor section, 2... NAND gate, 3... NOR gate, 4... Inverter, 5... Chip,
6...Package, 7...Lead, 1v-
1~1■-4...Inverter, N...Output transistor section output CL...External load.

Claims (1)

[Scope of Claims] 1. An output circuit characterized by having a constant current circuit within an inverter that drives an output transistor. 2. An output circuit characterized in that a constant current circuit is provided between the output end of an inverter that drives the output transistor and the gate portion of the output transistor.