JPH04284019A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To reduce a current change and to reduce noise quantity to be generated by blocking the flow of a through current and additionally suppressing the peak of a driving current low. CONSTITUTION:A transistor N11/P14 diode-connected and inserted between two transistors P1 and N1/P4 and N2 prevents transistors P2 and P4 in an output step from being simultaneously turned on. Then, transistors P3 and N3 connecting diodes and being inserted between the input point and output point of each transistor in an input step suppresses the peak value of the driving current low at the time of driving.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer circuit for a digital circuit, and particularly to prevention of through current and reduction of drive current.

0002

2. Description of the Related Art Conventionally, various output buffer circuits of this type have been proposed that take measures against through current. For example, in the output buffer circuit disclosed in Japanese Unexamined Patent Publication No. 1-32618, when a through current begins to flow, it is detected as a voltage drop across a resistor, and the current path of the through current is cut off by turning off the transistor. There is. In addition, in the output buffer circuit disclosed in Japanese Patent Application Laid-open No. 63-275223, a resistor is inserted into the inverter at the previous stage that drives the output transistor, and when the inverter is in the feed-through state (input 1/2 VDD), the resistor divides the voltage. This purpose is achieved by setting the potential of the output transistor below Vtp (p-channel threshold) and Vtn (n-channel threshold).

[0003] Similarly, in the output buffer circuits disclosed in Japanese Unexamined Patent Publications No. 1-209813 and No. 1-309414, the output transistor is turned on/off.
The off timing is staggered, and this purpose is achieved using multiple stages of transistors.

0004

[Problem to be solved by the invention] JP-A-1-32618
If a resistor is used as in the output buffer circuit disclosed in the publication, the through current can be suppressed, but the resistance value must be set appropriately according to the transistor characteristics, which is a constraint on circuit design. Ta. Although there are other methods of suppressing the through current, as shown in the above-mentioned prior art document, JP-A-63-275223, etc., all of them require the use of a large number of semiconductor elements, such as the use of logic elements. Further, in all of these conventional techniques, although the through current can be suppressed, the drive current changes greatly, which is a problem described below.

In the conventional output buffer circuit, the gate voltage of the output transistor changes monotonically from H level to L level or from L level to H level, and the change in drive current is caused by switching, as shown by the broken line in FIG. Waiting for the peak of the drive current during operation. The maximum value of the current change during switching is indicated at this peak time, and the higher the peak value, the larger the current change. The larger this current change is, the more likely noise is to occur in the power supply line.

It is an object of the present invention to prevent the flow of through current without increasing the number of semiconductor elements, and to suppress the peak value of the drive current to a low level to reduce the current change and reduce the amount of noise generated. The object of the present invention is to provide an output buffer circuit that makes it possible to

[0007]

[Means for Solving the Problems] The output buffer circuit of the present invention includes a pair of input stages having two transistors having a complementary relationship with each other, and two input stages that are diode-connected.
The device includes a pair of control sections having a transistor inserted between two transistors, and an output stage having two transistors complementary to each other and driven by the output of the control section. Further, in another output buffer circuit of the present invention, the control section further includes a diode-connected transistor inserted between the input point and the output point of each transistor in the output stage.

[0008]

[Operation] In the present invention, the control section has a diode-connected transistor inserted between two transistors in the input stage, which prevents the transistors in the output stage from operating at different timings and turning on at the same time. As a result, the through current can be prevented from flowing.

Further, in the present invention, the control section has a diode-connected transistor inserted between the input point and the output point of each transistor in the input stage, and the drive current is narrowed down by these transistors to reduce the current during switching. The peak value of the drive current can be kept low. As a result, changes in drive current can be suppressed to a small level, and noise generation in the power supply line can be reduced.

Furthermore, in the present invention, a pair of input stages and a pair of control sections are provided, and by appropriately selecting a signal to be input to the terminal of each input stage, it can be used as a bidirectional buffer.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit diagram of an output buffer circuit according to an embodiment of the present invention. This output circuit has input stages 11 and 12.
, control sections 13 and 14, and an output stage 15. Note that although a MOS-FET is used in this embodiment, it will be simply referred to as a transistor herein. Input stages 11 and 12 are transistors P1, N1, and P4.
, N2, each receiving an output data signal. The output stage 15 is composed of transistors P2 and N4, and drives an external load. The control units 13 and 14 are composed of transistors P3, N11, P14, and N3, and prevent the illustrated nodes ND2 and ND12 from being turned on at the same time, and direct a part of the drive current to the transistors P2 and N3 of the output stage 15.
It feeds back to the gate of N4 and functions to keep the steady current low and reduce current consumption.

In the output buffer circuit of FIG. 1, when output data is input to terminals GP and GN of input stages 11 and 12 and falls from H level to L level, transistors P1 and P4 are both turned on. The potentials of nodes ND2 and ND12 rise, transistor P2 of the output stage 15 turns off, and then transistor N4 turns on.
and outputs an L level signal. When the output data changes from L level to H level, input stages 11 and 12
transistors N1 and N2 turn on, and node ND2
And the potential of node ND12 becomes L level. and,
Output transistor N4 turns OFF, then P2 turns OFF.
It becomes N and outputs an H level signal.

Next, the details of the operation of the output buffer circuit shown in FIG. 1 will be explained in separate sections regarding the operation timing, limitations on the amount of change in current (di/dt), and the sizes of transistors P3, N11 and P14, N3. do.

(1) Operation timing In order to shift the operation timing of transistors P2 and N4 of output stage 15, there is a Diode-connected transistors N11 and P
14 are inserted respectively.

When the output data changes from L level to H level, when it exceeds the Vtn of transistor N2, transistor N2 is turned on and the potential of node ND12 begins to fall, but since transistor P14 is connected to a diode, the transistor Narrow down the current from P4. Therefore, the potential of the node ND12 instantly drops to the GND level, and first the transistor N4 of the output stage 15 is turned off.
become.

On the other hand, the output data is V of transistor N1.
When the potential difference between the node ND2 and the node ND3 exceeds Vtn of the transistor N11, the transistor N11 is turned on and the potential of the node ND3 becomes GND level.
11 turns on. Then, the source current from transistor P1 sinks to transistor N1, but since the source current is limited by transistor N11, node ND
2, the potential falls more slowly.

As a result, as shown in FIG.
When the potential of node ND12 (gate voltage of transistor P2) exceeds Vtp of transistor P2 and the potential of node ND12 (gate voltage of transistor N4)
A time lag can be ensured between the time when Vtn falls below Vtn of 4. That is, transistor P2 and transistor N4
Both are in the OFF state for a period of Δt1, and do not become ON at the same time, so no through current is generated.

When the output data changes from H level to L level, the operation is basically the same as in the above case, and as shown in FIG.
As shown in FIG. 2, both the transistor P2 and the transistor N4 are in the OFF state for a period of Δt2, and do not become ON at the same time, so that no through current is generated.

As described above, by limiting the sink current to the transistor N1 and the source current from the transistor P4, the rise time and fall time of the potential of the node ND2 are shortened and the fall time is lengthened, and the potential of the node ND12 is
The rise time of the potential is lengthened and the fall time is shortened. As a result, one transistor in the output stage becomes O
Since the other transistor is turned on after becoming FF, no through current occurs from transistor P2 to N4.

(2) When the control output data of the amount of change in current (di/dt) changes from L level to H level and rises, transistor N1 turns on, so node ND2
The potential of node NDOut falls, and when it exceeds Vtp, transistor P2 is turned on and the potential of node NDOut begins to rise. Then, node NDOut and node ND2
When the potential difference between the output transistor P2 and the output transistor P3 exceeds Vtp (Vt of the transistor P3), the diode-connected transistor P3 enters the saturation region and feeds back a portion of the drive current from the output transistor P2 to the node ND2. As a result, the potential change (falling manner) of the node ND2 per unit time is controlled. In this way, the node NDOut can be raised without using 100% of the drive current of the transistor P2.

FIGS. 4 and 5 show the drive current and the potential of node ND2 (gate voltage of transistor P2) at this time. The solid line is the characteristic of the above embodiment, and the broken line is the characteristic when transistors P3 and N3 are not inserted (conventional method). Node N as shown in Figure 4
The peak value of the current flowing into D2 is the transistor P3, N
It can be seen that it is held down more than when 3 was not inserted. Further, as shown in FIG. 5, it can be seen that the amount of drop in the gate voltage of the transistor P2 is smaller than that in the conventional method.

When the output signal falls from the H level to the L level, the potential of the node ND12 begins to rise and reaches Vt.
When n exceeds, transistor N4 turns on and node NDO
ut begins to fall. Node NDOut and node N
The potential difference with D12 is Vtn (Vt of transistor N3)
When the current is exceeded, transistor N3 becomes saturated, and part of the source current from transistor P4 is transferred to transistor N4.
Sync to. As a result, the potential change of node ND12 (
(how to stand up) is suppressed.

FIGS. 6 and 7 show the drive current and the potential of node ND12 (gate voltage of transistor N4) at this time. The solid line is the characteristic of the above example,
The broken line indicates when transistors P3 and N3 are not inserted (
This is a characteristic of the conventional method). As shown in FIG. 6, it can be seen that the peak value of the drive current flowing into node ND12 is suppressed compared to the conventional method. Further, as shown in FIG. 7, it can be seen that the amount of drop in the gate voltage of the transistor N4 is smaller than that in the conventional method.

As described above, by feeding back a portion of the drive current of the transistor in the output stage 15 to each gate of the transistors P3 and N3, the current change di/dt is alleviated without overactivating the transistor in the output stage 15. be able to.

Furthermore, when the output is at H level, the feedback current sourced from transistor P3 is throttled by transistor N11. Furthermore, when the output is at the L level, the steady current passing through the transistor N3 is throttled by the transistor P14. Therefore, as a result, the constant current consumption can be reduced.

Therefore, fluctuations in the power supply voltage during switch operation become small as shown in FIG. 8.

(3) Size of P3 and N11 and P14 and N3 The size of transistors P3 and N3 defines the amount of feedback current to each gate and node (ND2, ND12) during switching. Further, the smaller one of the transistors P14 and N3 or P3 and N11 defines the steady current. Furthermore, transistor P14
and N3 serve as a current source and a sink source, respectively, and by setting the sink current to be equal to or higher than the source current, changes in the gate voltage can be made constant at an arbitrary level. At this time, the magnitude of the voltage at the gate of transistor N4 exists in the size of transistors P14 and N3,
As shown in FIG. 9, the larger the transistor P14, the higher the value, and the smaller the transistor P14, the lower the value. Due to this characteristic, even if the size of the output transistors P2 and N3 is increased, the current drive capability can be designed to an arbitrary size by setting the gate voltage low.

Furthermore, without changing the size of the transistors in the output stage 15, the transistors P3 and N11 or P14 can be
By adjusting the size of transistor P2 and N3
, N4 can be freely set, so even if the size of the transistor in the output stage 15 is increased to increase the electrostatic withstand voltage, the drive capacity can be set to a predetermined value.

By the way, the above-mentioned embodiment is an example in which attention is paid to both the through current and current change, but when only the through current is focused, the configurations of the control sections 13 and 14 are changed as follows.

FIG. 10 is a circuit diagram of an output buffer circuit of an embodiment focusing only on the through current. In this embodiment, the transistor P of the control section 13 is different from the embodiment of FIG.
3 and the transistor N3 of the control unit 14 are omitted. Of course, since the transistors N11 and P14 are left as they are, the transistor P of the output stage 15
2. The ON/OFF timing of N4 is shifted as in the above embodiment, so that no through current occurs.

FIG. 11 shows a circuit diagram showing an application example of the output buffer circuit of FIG. 1 or 9, and its equivalent circuit diagram. In this application example, the input terminals GP and GN of input stages 11 and 12 are connected, and the output buffer circuit 20 of FIG.
An example is shown in which the same output data is supplied to both.

FIG. 10 shows a circuit diagram in which the output buffer circuit 20 of FIG. 1 is applied to a bidirectional buffer circuit and its equivalent circuit diagram. In the figure, 21, 22, and 25 are inverter circuits, 23 is a NOR circuit, and 24 is a NAND circuit. A control signal is supplied to the G(-) terminal, and an inverted signal of output data D is supplied to the D(-) terminal.

For example, when "0" is supplied to the G(-) terminal, an inverted signal of the output data supplied to the D(-) terminal, that is, output data D, appears at the output of the NOR circuit 23, and
An inverted signal of the output data supplied to the D(-) terminal, that is, output data D also appears at the output of the NAND circuit 24. As a result, the output data D is supplied to the terminals GP and GN of the output buffer circuit 20, and the output data appears at the output terminal OUT by the above-described operation.

Next, when "1" is supplied to the G(-) terminal, regardless of the output data supplied to the D(-) terminal,
“0” appears at the output of the NOR circuit 23, and the NAND circuit 24
"1" appears in the output. Therefore, referring to FIG. 1, since an L level signal is input to the terminal GP, the transistor P1 is turned on, the potential of the node ND2 is at the H level, and the transistor P2 is turned off. Further, since an H level signal is input to the terminal GN, the transistor N2 is turned on, the potential of the node ND12 becomes L level, and the transistor N4 is turned off. In this way, since both transistors P2 and N4 of the output stage 15 are turned off, the impedance becomes substantially infinite. Therefore, at this time, when a signal is supplied to the terminal Y1, it is not taken into the output buffer circuit 20, but is passed through the inverter 25 to the terminal Y1.
taken out from 2.

[0035]

As described above, according to the present invention, the transistor in the output stage can be turned on/off by the diode-connected transistor inserted between the two transistors in the input stage.
Since the timing of the FFs is shifted, the transistors in the output stage are prevented from turning on at the same time, and no through current occurs. Also, the input and output points of each transistor in the input stage are connected as diodes. Since the peak value of the drive current during switching can be suppressed to a low level by the transistor inserted between the two, it is possible to control the current change rate, and as a result, noise can be reduced and current consumption can be reduced. Furthermore, the electrostatic withstand voltage can be easily improved while maintaining a predetermined driving capability.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an output buffer circuit according to an embodiment of the present invention.

FIG. 2 is a characteristic diagram showing the gate voltage of the output transistor at the time of rising.

FIG. 3 is a characteristic diagram showing the gate voltage of the output transistor at the time of falling.

FIG. 4 is a characteristic diagram showing the drive current at rise time.

FIG. 5 is a characteristic diagram showing the gate voltage of the output transistor at the time of rising.

FIG. 6 is a characteristic diagram showing the drive current at the time of falling.

FIG. 7 is a characteristic diagram showing the gate voltage of the output transistor at the time of falling.

FIG. 8 is a characteristic diagram showing fluctuations in power supply voltage.

FIG. 9 is a characteristic diagram showing the relationship between the size of the transistor P14 and the gate voltage of the output stage transistor.

FIG. 10 is a circuit diagram of an output buffer circuit according to another embodiment of the present invention.

FIG. 11 is a circuit diagram showing an application example of the output buffer circuit of the present invention and its equivalent circuit diagram.

FIG. 12 is a circuit diagram showing another application example of the output buffer circuit of the present invention and its equivalent circuit diagram.

[Explanation of symbols]

11, 12: Input stage 13, 14: Control unit 15: Output stage

Claims (2)

[Claims] Claims: 1. A pair of input stages having two transistors complementary to each other; a pair of control units having a diode-connected transistor inserted between the two transistors of the input stage; An output buffer circuit having two transistors having a relationship with each other and an output stage driven by an output of the control section. 2. The control unit further includes a diode-connected transistor inserted between an input point and an output point of each transistor of the output stage.
Output buffer circuit as described.