JPH01115334U - - Google Patents
Info
- Publication number
- JPH01115334U JPH01115334U JP912488U JP912488U JPH01115334U JP H01115334 U JPH01115334 U JP H01115334U JP 912488 U JP912488 U JP 912488U JP 912488 U JP912488 U JP 912488U JP H01115334 U JPH01115334 U JP H01115334U
- Authority
- JP
- Japan
- Prior art keywords
- output
- transistor
- pair
- transistors
- output circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 claims description 3
- 238000007599 discharging Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Description
第１図および第２図が本考案に関し、第１図に
本考案によるＣＭＯＳオンオフ出力回路の一実施
例を関連回路とともに示す回路図、第２図はその
主な信号の波形図である。第３図以降は従来技術
に関し、第３図は従来のＣＭＯＳオンオフ出力回
路の回路図、第４図はその主な信号の波形図であ
る。図において、
１：ノアゲート、２：ナンドゲート、３：イン
バータ、４：負荷、５：負荷がもつキヤパシタン
ス、１０：出力回路、１１：出力トランジスタ対
、１１ｐ：ｐチヤネル形の出力トランジスタない
しは電界効果トランジスタ、１１ｎ：ｎチヤネル
形の出力トランジスタないしは電界効果トランジ
スタ、１２ｐ，１２ｎ：駆動トランジスタ対、１
２ｐｃ，１２ｎｃ：充電路を形成する駆動トラン
ジスタ、１２ｐｄ，１２ｎｄ：放電路を形成する
駆動トランジスタ、１３ｐ，１３ｎ：抵抗、２０
：従来の出力回路、２１，２２：出力トランジス
タ、２３〜２６：トランジスタ、Ｃ：制御信号、
Ｄ：デイジタル信号、Ｅ：電源点ないしはその電
位、Ｉｎ：出力回路の定格電流値、ｉｓ：貫通電
流、Ｓｐ，Ｓｎ：出力回路への入力信号、ｔｎ，
ｔｆ：時刻、τ：遅れ時間、τｃ：充電遅れ時間
、τｄ：放電遅れ時間、Ｖ：電源点ないしはその
電位、Ｖｏ：出力回路のオンオフ出力、ｖｐ，ｖ
ｎ：出力トランジスタのゲート電圧、である。
1 and 2 relate to the present invention. FIG. 1 is a circuit diagram showing an embodiment of a CMOS on/off output circuit according to the present invention together with related circuits, and FIG. 2 is a waveform diagram of its main signals. 3 and subsequent figures relate to the prior art. FIG. 3 is a circuit diagram of a conventional CMOS on/off output circuit, and FIG. 4 is a waveform diagram of its main signals. In the figure, 1: NOR gate, 2: NAND gate, 3: inverter, 4: load, 5: capacitance of load, 10: output circuit, 11: output transistor pair, 11p: p-channel type output transistor or field effect transistor, 11n: n-channel type output transistor or field effect transistor, 12p, 12n: drive transistor pair, 1
2pc, 12nc: Drive transistor that forms a charging path, 12pd, 12nd: Drive transistor that forms a discharge path, 13p, 13n: Resistor, 20
: conventional output circuit, 21, 22: output transistor, 23 to 26: transistor, C: control signal,
D: digital signal, E: power supply point or its potential, In: rated current value of the output circuit, is: through current, Sp, Sn: input signal to the output circuit, tn,
tf: time, τ: delay time, τc: charge delay time, τd: discharge delay time, V: power supply point or its potential, Vo: on/off output of output circuit, vp, v
n: Gate voltage of the output transistor.
Claims (1)
果トランジスタとしてなる１対の出力トランジス
タを直列接続し、両出力トランジスタを交互にオ
ンオフさせながらそれらの相互接続点からオンオ
フ出力を取り出す出力回路において、交互にオン
オフ動作して出力トランジスタのゲートがもつキ
ヤパシタンスに対してそれぞれ充電路および放電
路を形成する一対の駆動トランジスタを出力トラ
ンジスタごとに設け、この充電路および放電路中
の出力トランジスタをオン動作させる一方の側の
時定数を他方の時定数よりも大きく選定したこと
を特徴とするＣＭＯＳオンオフ出力回路。 In an output circuit, a pair of output transistors each serving as a field effect transistor of a reverse channel type are connected in series between a pair of power supply points, and an on/off output is taken out from their interconnection point while alternately turning on and off both output transistors. A pair of drive transistors are provided for each output transistor, which alternately turn on and off to form a charging path and a discharging path for the capacitance of the gate of the output transistor, respectively, and turn on the output transistor in the charging path and the discharging path. A CMOS on/off output circuit characterized in that a time constant on one side is selected to be larger than a time constant on the other side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP912488U JPH01115334U (en) | 1988-01-27 | 1988-01-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP912488U JPH01115334U (en) | 1988-01-27 | 1988-01-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01115334U true JPH01115334U (en) | 1989-08-03 |
Family
ID=31215599
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP912488U Pending JPH01115334U (en) | 1988-01-27 | 1988-01-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01115334U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04284019A (en) * | 1991-03-13 | 1992-10-08 | Nkk Corp | Output buffer circuit |
| JPH07142986A (en) * | 1993-11-19 | 1995-06-02 | Nec Corp | Semiconductor integrated circuit |
-
1988
- 1988-01-27 JP JP912488U patent/JPH01115334U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04284019A (en) * | 1991-03-13 | 1992-10-08 | Nkk Corp | Output buffer circuit |
| JPH07142986A (en) * | 1993-11-19 | 1995-06-02 | Nec Corp | Semiconductor integrated circuit |
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