JPH03240093A - Method and device for driving plasma display panel - Google Patents

Abstract

PURPOSE: To increase the speed of the address function by including plural address cycles in one fundamental cycle. CONSTITUTION: Address lines YAm and Yan are made negative to discharge corresponding coupling cells C2 and C3, and pixel cells P1 to P4 in cell groups 202 and 204 are turned on. Next, an erase pulse is applied to address lines XA and YAm to discharge an address A of the cell group 204. By this discharge, plasma is diffused to vertical coupling cells C1 and C4 to form wall electric charge. A pair of holding voltages are supplied to erase the cent P1. Next, holding lines XSa and YSa are kept high-voltage and a holding line YSb is kept constant-voltage to discharge the cell C1 of the cell group 204. The cell P2 is not erased until it is reset by a load holding half cycle. Next, the erase pulse is applied to lines XA and YAn to discharge the address A of the cell group 202, and charged electric charge is generated in cells C1 and C4 to erase the cell P1, P3 or P4.

Description

Description: TECHNICAL FIELD This invention relates to independently maintained and addressed AC plasma display panels, and more particularly to high speed driving methods and apparatus for such panels.

BACKGROUND OF THE INVENTION Plasma display panels (or gas discharge panels) are well known and include a pair of transparent substrates each supporting row and column electrodes. Each transparent substrate is arranged in parallel to form a gap in which ionized gas is enclosed. The substrate is arranged so that the electrodes intersect with each other, and the intersections form discharge cells. In this discharge cell,
Discharging is selectively performed to accomplish the desired storage or display function. It is also known to drive such panels with alternating voltages to provide a write voltage that exceeds the firing voltage at the discharge point defined by the selected row and column electrodes to cause a discharge in the selected cell. The discharge in such a selected cell is continuously "stained"2 by applying an alternating current holding voltage (which by itself is not sufficient to initiate the discharge). wall electrification
) cooperates with the holding voltage to maintain the discharge.

Such a gas discharge or plasma display panel is described in US Pat. No. 3,559,190 to Donald L. Bitzer et al.

AC plasma displays have been found to be suitable for a wide range of applications due to their excellent optical properties and flat panel geometry.

These characteristics are what have made plasma displays the leader in the flat display panel market. However, plasma display panels have captured only a small portion of that potential market due to competition from low-cost CRTs. I haven't been able to do it.

Various attempts have been made to reduce the costs inherent in AC plasma panel construction. One successful example is r Independent 5ustain a
nd＾ddress Pasma Dfspley P
No. 4,772,884 entitled anel J. This US patent discloses changing the electrode arrangement in standard AC plasma technology so that addressing and holding functions are performed by separate panel electrode structures. By separating the two functions in this way,
Achieving both a different addressing mode and a reduction in the number of address drivers relative to standard AC plasma technology is achieved. Furthermore, the address driver does not provide a holding current and therefore can be very small and low cost.

In Figure 1, 8x8 pixel independent (Indepe
ndent) Sustain and address (A
ddress (hereinafter abbreviated as ISA) plasma panel is shown. FIG. 2 is an enlarged view of the area surrounded by circle 10 in FIG. This enlarged view shows the nine elementary cells that are the repeating units of the ISA geometry. Each elementary cell is classified according to the type of cross-electrode that forms it. In conventional plasma panels prior to ISA technology, all cells on the panel were electrically identical and were technically all display pixels. However, in the ISA panel, only 4 cells out of 9 cells in the basic cell group are display pixels, i.e. P
l, P2. They are P3 and P4. These pixel cells are located at the intersection of four storage electrodes XSa, XSb, YSa and YSb. In addition to the four pixel cells, there are five other cells in the basic cell group. The center cell of the basic cell group is the address cell A, and this cell A has 2
It exists at the intersection of two address electrodes XA and YA. The remaining four cells are coupling cells C1, C2, C3 and C4, located at the intersection of the hold and address electrodes. Coupling cells are classified into two groups depending on their location relative to address cells. C1 and C4 cells are called vertical coupling cells, and C2 and C3 cells are called horizontal coupling cells. It should be understood that the terms vertical and horizontal are used merely to indicate orthogonal directions for conductors and cells and for ease of reference.

The horizontal electrodes of an ISA panel are all on one substrate of the panel and are called Y electrodes. All of the vertical electrodes are on the opposite substrate and are called X electrodes. As is well known, an ionizable gas exists between these substrates to enable selected cells to emit light.

The X address electrodes are electrodes 12, 14, 16 and 18, while the Y electrodes are electrodes 20. 22. 24 and 26. Each X electrode is selectively driven by a column address drive circuit 28 and each Y address line is driven by a row address drive circuit 30.

The X hold signal is generated by two hold signal generators 32 and 34. Each of the hold signal generators 32 and 34 has a pair of parallel hold lines connected to each other (i.e. 36.3
8). Each holding line pair, i.e. 36.3
8 are short-circuited to each other by short-circuit bars at their ends to form a pair of holding electrodes. Every other pair of holding electrodes on a given substrate are connected to each other by a holding bus and to one of the two holding drivers. Separate hold drivers 40 and 42 are similarly connected to the column hold electrode pairs.

In Figure 3, the above-mentioned U.S. patent cylinder 4.772,88
A waveform representing the basic cycle of the ISA plasma panel described in No. 4 is shown. In the preferred mode of operation, two rows of pixel cells are turned on first. An erase cycle is then performed to selectively turn off the pixels whose image data display is to be turned off. The waveforms in FIG. 3 assume that a "write two rows" cycle has already occurred. Selective erasure of desired "on" pixels consists of two steps. The first
In this step, the selected YA address electrode (second
A discharge is generated in the selected address cell along the line (see figure). This results in the movement of wall charges into the vertical coupling cells C1 and C4.

This will be explained in more detail with reference to the waveforms in FIG. Before selective erasure occurs, a reset pulse is applied to the X and Y address lines to reset the wall voltages in vertical coupling cells C1 and C4. Holding line XSa
, XSb and YSa.

By synchronously supplying the YSb reset pulse and holding voltage, a slight discharge is generated within the coupling cell, and the wall voltage is adjusted.

Erase address pulses 50 and 52 are then applied to XA and Y
A address lines are respectively supplied. This initiates step 1 of the selective erasure procedure, the effect of which is illustrated in FIG. The erase address waveform has polarity, so the XA and YA electrodes act as anodes and cathodes. Since the XA electrode is an anode, address cell A
The plasma discharge charge 54 generated in the cell spreads primarily towards the vertical coupling cells and cells C1 and C4.

The voltage across the gap of each coupling cell C1 and C4 is such that the dispersed plasma imparts a significant negative charge to these cells. FIG. 5 is a cross-sectional view taken along line 5-5 in FIG. 4 (step 1), showing the state of plasma diffusion in step 1, and shows the coupling cell C.
1 and C4 and the charges on the inner walls of address cell A.

Two degrees of selection are performed in the selective erasure step. This step 2 is initiated by the falling edge of erase address pulses 50 and 52 and the rise of the selective potential at the hold electrodes. As shown in FIG. 5, in step 1, when address cell A is discharged, equal wall charges are applied to coupling cells C1 and C4. By applying a voltage only to the Y holding line corresponding to the selected vertical coupling cell, unselected vertical coupling cells defined by the non-applied Y holding line do not discharge.

In step 2, the selected YS and XS electrodes are anode and cathode, respectively. Such polarity causes the plasma formed by the coupling cell discharge to diffuse horizontally from the cell to adjacent pixel cells. The cross section along line 6-6 in Figure 4 (Step 2) is the 6th section.
6a to 6d for ease of understanding of the selective erase operation. In FIG. 3, the voltage waveforms applied to the X and Y hold lines in step 2 enable the selection of pixel cells to be erased.

In Figure 6a, it is assumed that step 1 has already been done, coupling cell C1 has a wall charge and forms a positive voltage under the YSa electrode, and pixel cells P1 and P2 are both in the on state. At this point, we want to erase Pl while keeping P2 on.

Therefore, an i00 volt voltage is applied to each of the XSa and YSa electrodes, and an O voltage is applied to the XA and XSb electrodes.

The wall charge held in coupling cell C1 adds to the applied potential on the YSa electrode and
The charge of 1 is discharged. At the same time, a discharge occurs in pixel cell P2, but not in Pl. This is because the same voltage is present at the coupling electrode.

The plasma generated by the discharge of cell C1 diffuses along the YSa electrode and neutralizes and erases the wall charge already present in cell P1. Cell P2 is already discharged and further charge transfer has no effect.

Different initial conditions are assumed in FIG. 6c. That is, cell P2 should be in the off state and Pl should be erased without affecting the state of cell P2. in this case,
Since the dielectric directly under the YSa electrode of cell P1 has a positive wall charge, electrons due to the discharge of coupling cell C1 move thereto and neutralize the already existing wall charge. The negative wall charge in pixel cell P2 repels the electrons caused by the discharge in coupling cell C1, leaving cell P2 unaffected. Thus, in step 2 of selective erasing, the raised hold line determines the type of pixel cell to be erased. Thus, to erase a pixel cell of the selected type, a voltage is simultaneously applied to the two retention electrodes defining the selected pixel cell, causing the XA address pulse to fall.

I have reduced the number of address drivers by half.
In the SA plasma display panel, in the simplest case, updating the panel size is twice as slow as in a normal AC plasma panel. Since there is one address driver for every two columns or rows of pixels, two selective erase cycles delay operation of the entire panel. This becomes a problem when the number of columns of data or the frame update rate is high. If the frame update rate is to be increased for any reason, the maximum number of rows of data that can be generated is accordingly reduced. Similarly, if the number of columns of display data is to increase beyond the maximum allowed for the original frame update rate, the frame update rate must be decreased.

Further, in conventional ISA AC plasma panels, one or more cell wall charge stabilization cycles are required following the selective erase cycle.

Therefore, in addition to the time required for erase pixels in each group of cells, hold pulses are spread between erase pulses, increasing the overall address time.

Additionally, the pulse width of the hold pulse needed to be long enough to ensure proper discharge of the cells to be kept "on". These factors combine to create an ISA
The address time of AC plasma panels was extremely long.

The speed limit mentioned above becomes a problem. Relatively fast frame update rates are often required for displaying continuous information when a mouse, pointer, or graphics are required.

Furthermore, the ability to efficiently display gray images is highly dependent on the update rate of the display screen.

OBJECTS OF THE INVENTION It is therefore an object of the present invention to provide an ISA AC plasma panel with improved addressing requirements.

Another object of the present invention is to provide an ISA with high-speed address capability.
Our goal is to provide AC plasma panels. Yet another object of the present invention is to provide an ISA AC plasma panel that uses conventional panel construction but has improved addressing capabilities.

Yet another object of the present invention is to provide a power consuming ISA AC plasma panel.

Still another object of the present invention is to provide an ISA AC plasma panel with variable display brightness.

Summary of the Invention A method for driving an ISA AC plasma panel according to the present invention will be described.

The panel has at least two cell groups and in each cell group there are an address cell, two vertical coupling cells, two horizontal coupling cells and four pixel cells. Horizontal and vertical address lines intersect at each address cell, and parallel hold lines are placed on either side of each address line to intersect parallel and adjacent pixel cells and coupling cells in each group of cells. This improved driving method consists of the following steps. That is, A,
B. applying an erase pulse to the address cells so that the first coupling cell has a wall charge; C. Applying a preset voltage between the cross-hold lines, one of which intersects the first coupling cell and the second adjacent pixel cell, causes electrons from the discharge of the first coupling cell to move to the first adjacent pixel cell and erase them. , causing an "on" pixel cell adjacent to the first coupling cell to discharge; D. applying another erase pulse to the address cell to cause another coupling cell to generate a wall charge; E. Applying a voltage of a width shorter than the preset voltage to the intersecting hold line to cause wall charge to be transferred to a pixel cell adjacent to the different coupling cell to erase this pixel cell, the voltage of the short width being equal to the voltage of the different coupling cell; A step that is insufficiently long for other pigcell cells adjacent to the coupling cell to discharge.

Other methods of selective erasing eliminate the need for the shorter pulse width voltages described above. The disclosed erasing techniques also prevent panel energy dissipation.

Embodiment The method of addressing an ISA plasma panel according to the present invention includes multiple addressing cycles in one basic cycle. In FIG. 7, waveforms of multiple address basic cycles used in an rsA AC plasma panel are shown. In summary, the procedure starts by writing all pixels of four (or more) lines. One type of pixel is then erased in the first line and half a hold cycle causes the other type of pixel to be erased in the other line. The second erase is done with a shorter hold signal.

This shorter hold signal may continue to be used in the next erase operation.

FIG. 7 shows an address line XA in the X direction, address lines YAm and YAn in the Y direction, and a pair of holding lines Xa and XA.
b, shows voltage changes supplied to YSa and YSb. It should be noted that in the waveform diagram of FIG. 7, two address cycles are shown, or there may be more under normal conditions. Each address cycle includes independent discharge steps 1 and 2 similar to that illustrated by FIG. 5 and 6a-6d. FIGS. 8 through 11 sequentially illustrate phenomena that occur in a basic cycle including a plurality of address cycles, and illustrate address operations at different points in the basic cycle. 8th
In each of the figures to FIG. 11, a line 2 indicating a certain point in time
00 is shown, extending between each waveform to demonstrate the action occurring in each group of cells at a given point in time.

In FIG. 8, four columns of consecutive pixel cells in cell groups 202 and 204 are first written to the "on" state.

This is done by making both address lines YAm and YAn negative, causing the corresponding coupling cells C2 and C3 to discharge. As a result, the wall charge is distributed to adjacent big cell cells, preparing these pixel cells for discharge in the subsequent hold cycle. In this way, pixel cells PI, P in cell groups 202 and 204
2°P3 and P4 are turned on.

First, a plurality of reset pulses are applied to the address lines to adjust the wall charge of the coupling cell, as described above by conventional addressing methods.

Erase pulses 208 and 210 are then applied to address lines XA and YAm to cause address cell A of cell group 204 to discharge. This discharge causes plasma 2
07 diffuses into the vertical coupling cells C1 and C4 to form wall charges. In summary, this is the discharge in step 1 above.

For purposes of illustration, the first cell to be erased was pixel cell P1, but other pixel cells may be selected as the first cell to be erased. In FIG. 9, the dashed line 200 representing a point in time is advanced a little at which address pulses 208 and 210 fall to a low state. A pair of holding voltages are applied to appropriately influence the plasma generated by the discharge of vertical coupling cell C1 to erase cell P1.

As shown by waveforms 212 and 214
The Sa holding line is maintained at a high voltage while the Xsb and Y
The Sb holding line is maintained at a constant voltage.

When the XSa and YSa holding lines become high voltages, the wall charges in the coupling cell C1 of the cell group 204 combine with the supplied holding voltage to cause the coupling cell C1 to discharge. (In the same way as step 2 discharge described above)
Electrons from the discharge of coupling cell C1 move to pixel cell P1 and neutralize its wall charge. Pixel cell P
1 does not discharge despite its previous "on" state. This is because 0 volt is applied to the pixel cell P1. It is then erased by the moving electrons.

On the other hand, pixel cell P2 is discharged by the high voltage on YSa that is added to the wall charge within big cell cell P2.

Hold voltage waveforms 212 and 214 must be long enough to properly discharge pixel cell P2. On the other hand, pixel cell P2 may turn off during erasing of pixel cell P1. In conventional ISA addressing schemes, hold pulses 212 and 214 are followed by two load hold pulses of opposite polarity to reset and stabilize the "on" state of the pixel cell. However, in this embodiment, when pixel cell P2 discharges, its wall charge reverses state and is not reset by the subsequent hold cycle. Thus, pixel cell P2 cannot be erased until it is reset by a load hold half cycle. This point will be discussed in detail below.

In FIG. 10, consider the second address portion of the basic cycle. Under these conditions the erase pulse 216
is applied to the XA address line and the erase pulse 218 is applied to the Y
Assume that An is applied to the An address line. These erase pulses combine to discharge address cell A of cell group 202, creating the Step I type discharge effect described above and creating wall charges in coupling cells C1 and C4. In this regard, it is clear from FIG. 9 that the application of the XSa and YSa hold pulses 212 and 214 caused the discharge of pixel cell P2. These same hold pulses cause all P2 cells (which were in the on state) to discharge and reverse their wall charge state. Thus, no pixel cell P2 on the panel can be erased until a further subsequent elementary cycle is reached when the wall charge of the P2 cell is reset by the next hold half cycle. Therefore, pixel cell P
i, P3 or P4 may be deleted.

Assuming that pixel cell P1 in cell group 202 is selected for erasure, point in time line 200 moves to the point shown in FIG. is given by As a result, pixel cell P1 in cell group 202 is erased by dispersion of electrons into its cell structure. At this time, the plasma does not diffuse into the pixel cell P2. This is because the cell in question has already been discharged and its wall charge is less positive than that of pixel cell P1. Therefore,
Plasma diffusion occurs only in pixel cell P1.

Here, the hold pulses 220 and 222 are the hold pulses 212
It should be noted that it is shorter in width than and 214. This is because hold pulses 220 and 222 are not required to ensure proper discharge of pixel cell P2. This reduces address time and allows for faster panel updates.

As is clear from the above, two successive erasing pulses enable the erasure of the first type of pixel cell of a group of cells, and then the erasure of the second type of pixel cell of this same group of cells or of another group of cells. This erases the pixel cells. One constraint is that pixel cells that are on the same Y hold line as the erased pixel cell cannot be erased until reset by the next hold half cycle. As a result, two different types of pixel cells are erased within each elementary cycle and a second elementary cycle is required for erasure of the other two types of pixel cells. However, in one elementary cycle two pixel cells of the same type can be erased in as many different cell groups as possible.

In each erase operation, the erase pulse is followed by a short hold level pulse.

In FIG. 2 a second solution is shown which reduces the time required to update the state of a pixel. This solution does not use multiple independent address cycles within each basic cycle. Instead, multiple independent Step 1 erase cycles are used in this method and only one Step 2 cycle occurs. In this method all pixel cells erased in one basic cycle must be of the same type. Furthermore, each step 1 erase pulse must be applied to a different YA address line.

At each erase pulse (step 1 discharge) in FIG. 12, a discharge occurs in a selected column of address cells. The plasma caused by this discharge is diffused in the vertical direction and
Enter the vertical coupling cell in a similar manner as shown in the figure. The wall charges within these coupling cells remain until the step 2 discharge occurs. When the step 2 discharge begins, a plurality of vertical coupling cells discharge at different points on the panel. These discharges cause plasma dispersion as shown in Figures 6a, 6b, 6c and 6d. The important point is that the selected vertical coupling cell retains the wall charge therein during step 1. These coupling cells use the preset and held wall charge for the next step 2 discharge to discharge the selected erased pixel cell.

FIGS. 13-15 illustrate successive phenomena that occur in the multiple address basic cycle described above with reference to FIG. 12. Next to each diagram showing plasma diffusion, a waveform representing an address phenomenon is shown. In each figure, time point line 300 indicates the point in time in each waveform at which the address phenomenon occurs. address cell 1
It is selectively generated in columns. As a result, cell group 304
A discharge occurs in address cell A and plasma diffuses into vertical coupling cells C1 and C4.

In FIG. 14, a step 1 discharge is generated at the intersection of address line XA and address line YAn. The subsequent address erase pulse is generated immediately after the first erase pulse described in FIG.

FIG. 15 shows how holding voltages are applied to cell groups 302, 304 and 306 via holding lines XSa and YSa. These voltages are applied to cell groups 302 and 304.
The discharge of step 2 is generated in the coupling C1 within. This step 2 discharge causes the movement of charge into the pixel cell to be erased and also discharges the adjacent pixel cells that are in the "on" state.

These step 2 discharges occur within the same type of vertical coupling cell, C1. This is because all vertical coupling cells receive the same Step 2 waveforms, and these Step 2 waveforms define the vertical coupling cell and pixel cell type to be selected.

After step 2 discharge, all of the selected pixel cells in the selected column, in this case P1, are updated to a new state, either "on" or "off", according to the image data.

In an ISA plasma panel, display brightness and power consumption are roughly proportional. Therefore, decreasing or increasing one or the other of these parameters directly affects the other. For example, for a given image in an ISA plasma panel display, doubling the brightness also doubles the power consumption. The instantaneous value of power consumption for a given brightness is roughly proportional to the number of pixel cells in the on state.

In conventional AC plasma panels, panel power consumption has been controlled by adjusting the holding frequency or by time modulating the on-state pixels. In the first method, the holding frequency was adjusted so that fewer holding discharges were produced in discrete time periods. In the second method, i.e., the method of time modulation of the "on" pixel, the desired erasure power and brightness level could be used, but the time modulation of the "on" pixel resulted in flickering on the display screen. In this method, the "on" pixels were kept on for a portion of the frame time and then all pixels were erased. The time during which a pixel is on within a frame time determines the brightness and also determines the power consumption. In the ISA AC plasma panel according to the present invention, a time modulation technique is used, and a "double layer erasure" of pixels is done simultaneously,
It is similar to "two-layer writing", which is used to turn on two layers of pixels simultaneously. This "double-layer erasing" operation is performed at any time within the frame time, and the brightness of the display surface becomes lower as it approaches the erasing operation of raster lines written on the display surface of the AC plasma panel.

The waveforms in FIG. 16 are indicative of a "two-layer erase" operation.

Note that the XA address line is not included in this operation.

As shown in FIG. 16, an erase pulse is applied to address line YAk via pulse generator YAp.

Figure 17 shows the reduction caused by the application of these Y address waveforms, showing that horizontal coupling cells C2 and C3 are being discharged simultaneously. As can be seen from FIG. 16, the waveforms that produce these discharges are such that the XS electrode serves as an anode and the YA electrode serves as a cathode. The polarity of this discharge causes the plasma to spread vertically towards the display pixels on either side of the horizontal coupling cell. The subsequently applied holding voltage waveform is adjusted to minimize the voltage across the gas of the pixel cell that is in the off state.

However, in an "on" pixel cell, a voltage very close to the holding voltage is applied to the gas. This difference between "on" and "off" pixel cells and its effects is illustrated in Figures 18a-18d.

Each of Figures 18a to 18d corresponds to line 18 in Figure 17.
-18 shows a cross-section of the panel. M18
a is that the pixels above and below the coupling cell are initially “on J”.
It also shows the influence during the discharge of coupling cell C2.

No. 18b shows the state of erased pixel cells P1 and P3 after the discharge has ended.

Figures 18c and 18d further show the situation when one pixel cell is initially "off" and the other pixel cell is initially "on". The plasma spreading along the anode of the coupling cell is Gives a negative charge to the dielectric covering the anode.

The amount of this charge depends on the voltage across the gas of the pixel cell.

In the cases shown in 18c and 18d, the plasma diffusing from the horizontal coupling cell C2 towards the pixel cells P1 and P3 causes the voltage applied to the gas in the pixel cell Pi (on pixel) to be O. As is clear from FIG. 18c, the positive wall charge within the pixel cell Pl greatly influences the direction in which the electrons generated by the discharge within the coupling cell C2 move. There is no similar wall charge in pixel cell P3, which is in the off state, so the plasma has no effect on this pixel cell.

After dissipation of this plasma, the pixels that were in the on state have no voltage across the gas, as do the pixels that are in the off state. Therefore, even if a holding voltage is applied to the pixel cell that was in the on state, the pixel cell no longer discharges, and therefore, the pixel cell is in the off state. Using this technique, both brightness levels and power consumption can be varied significantly in ISA AC plasma panels.

The embodiments described above are for the purpose of illustrating the invention, and it is obvious that a person skilled in the art can easily make various modifications without departing from the invention.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing the circuit configuration of a conventional ISA AC plasma panel, Figure 2 is an enlarged view of the cell group in Figure 1,
FIG. 3 is a waveform diagram showing the voltages used to erase selected pixels in the AC plasma panel of FIG. 1; FIG. Diagrams showing the plasma diffusion effect, FIG. 5 is a cross-sectional view taken along line 55 in FIG. 4 (step 1), and FIGS. 68 and 6b are cross-sectional views taken along line 6 in FIG. 4 (step 2).
Figures 6C and 6d are cross-sectional views along P2 pixel cells in the OFF state, showing the state of the step 2 discharge erasing the P1 pixel cell while the P2 pixel cell is in the ON state; A cross-sectional view taken along line 6-6 of FIG. 4 (Step 2) to illustrate the operation of the step 2 discharge to erase the P1 pixel cell while FIG. FIG. 8 is a diagram showing the voltage waveform that causes the step 1 discharge that occurs in the address cell in the selective erasing method of the present invention and the three related cell groups. FIG. 10 is a diagram similar to FIGS. 8 and 9 but showing a step 1 discharge caused by a different address cell; FIG. 11 is a diagram similar to FIG. FIG. 12 is a waveform diagram illustrating another alternate selective erase address operation according to the present invention; FIG. 13 illustrates a step 1 discharge in an address cell implementing the alternate addressing method. A diagram showing the waveform necessary for and the three cell groups related to this,
Fig. 14 is similar to Fig. 13, but shows the step 1 discharge that occurs following the step 1 discharge shown in Fig. 13, and Fig. 15 shows the address cycle when two step 2 discharges occur simultaneously. FIG. 16 is a waveform diagram showing the operation of the two-column erasing method adopted in the I5AAC plasma panel to reduce power consumption. FIG. 17 is a waveform diagram showing the operation of the two-column erasing technique. Figures 18a and 18b are cross-sectional views taken along line 18--18 of Figure 17 and illustrate the operation of the two-layer erase method when pixel cells P1 and P3 are both on. 18c and 18d are cross-sectional views taken along line 18-18 of FIG. 17, showing the operation of the two-layer erasure method when one pixel cell is on and the other pixel cell is off. It is a diagram. Explanation of symbols of main parts A...Address cell

Claims (10)

[Claims] (1) at least two groups of cells each including an address cell, two vertical coupling cells, two horizontal coupling cells and four pixel cells; horizontal and vertical address lines intersecting at the address cell; A method for driving an ISA AC plasma display panel having parallel holding lines located on both sides of an address line and intersecting at adjacent pixel cells and coupling cells, the method comprising: (a) exciting the address line and the holding line; (b) applying an erase voltage to the address cell to generate a wall charge in the first coupling cell; (c) the first coupling cell and applying a voltage for a preset period between cross-hold lines including one of the intersecting hold lines in the first and second adjacent pixel cells to transfer electrons from the discharge of the coupling cell to the first adjacent pixel cell; erasing the first neighboring pixel cell;
further discharging the second adjacent pixel cell when it is in an "on"state; (d) applying an erase voltage to the address cell to generate wall charges in a different coupling cell; (e) applying a voltage for a shorter period than the preset period voltage to a pair of intersecting holding lines to move the wall charge to a pixel cell adjacent to the different coupling cell and erase the pixel cell. , wherein the voltage for the shorter period is of insufficient magnitude to discharge other pixel cells adjacent to the different coupling cell. 2. The method of claim 1, wherein the erase voltage is applied to address cells of one group of cells, and the other erase voltage is applied to address cells of another group of cells. (3) Adjacent holding lines are connected to each other as pairs, and each pair exists between parallel address lines and intersects at an adjacent pixel cell and a coupling cell in an adjacent cell group, and the preset 3. A method as claimed in claim 2, characterized in that the period voltage and the shorter period voltage are applied to adjacent and parallel pairs of holding lines. (4) One type of pixel cell in one cell group is formed by the intersection of one of the first horizontal holding line pairs and one of the first vertical holding line pairs, and the same type of pixel cell in one other cell group cells are formed by said one intersection of another position of a first pair of horizontal retention lines and a first pair of vertical retention lines, further comprising: (f) sequentially erasing pixel cells of the same type in different groups of cells; 4. The method according to claim 3, further comprising: (5) One type of pixel cell in one cell group is formed by crossing one of the first horizontal retention line pairs and one of the first vertical retention line pair, and the same type of pixel cell in the other cell group (f) pixels of the same type in different groups of cells; 2. The method of claim 1, further comprising the step of erasing cells in sequence. One type of pixel cell in the cell group in (6) is formed by the intersection of one of the first horizontal holding line pair and one of the first vertical holding line pair, and the same type of pixel cell in the other cell group cells are formed by the intersection of the first pair of horizontal retention lines with the first pair of horizontal retention lines and the first pair of vertical retention lines to cause different types of cells to be erased; (c1) Applying an erase voltage to the first address cell to
(d1) A holding line intersecting to form a different type of pixel cell adjacent to the other vertical coupling cell; applying a voltage for a preset period between the two coupling cells to cause electrons caused by the discharge of the other coupling cell to move to the different type of pixel cell to erase the different type of pixel cell; do"
2. The method of claim 1, further comprising the step of: discharging the "on" pixel cell. (7) two cell groups each consisting of an address cell, two vertical coupling cells arranged on both sides of the address cell, two horizontal coupling cells arranged on both sides of the address cell, and four pixel cells; , horizontal and vertical address lines that intersect at the address cell, and holding lines disposed on both sides of each of the address lines, each holding line passing through a series of pixel cells and coupling cells, Each pixel cell is P
1 to P4, and identical pixel cells of adjacent cell groups are formed at the intersection of a pair of adjacent holding lines and a holding line orthogonal thereto, the method comprising: (a) the address; (b) Applying an erase voltage pulse train to address cells in the cell group to discharge the address cells so as to turn on the pixel cells in the group of cells; generating a wall charge in a coupling cell adjacent to the cell; (c) applying a voltage for a preset period to a pair of holding lines that intersect the pixel cell of the same type and the coupling cell to close the coupling cell; a discharge, and transfer electrons into the pixel cell of the same type to erase the pixel cell. 8. The method of claim 7, wherein the preset period voltage causes unerased "on" pixel cells adjacent to each of the coupling cells to discharge. (9) a plurality of cell groups each consisting of an address cell, two vertical coupling cells, two horizontal coupling cells and four pixel cells; horizontal and vertical address electrodes intersecting the address cells; and each of the address lines; a pair of parallel holding electrodes arranged on both sides of the ISAAC plasma display panel, each of said holding electrode pairs intersecting a series of parallel and adjacent pixels and coupling cells in an adjacent cell group, the method comprising: (a) energizing address electrodes that intersect address cells of all cell groups on the same line to discharge the address cells to generate wall charges in each horizontal coupling cell of the cell group on the same line; (b) applying a holding voltage to horizontal holding electrodes that intersect all pixel cells in each of said group of cells along said same line and applying a holding voltage to all vertical holding electrodes to line said line; erasing all pixel cells in each of said groups of cells along two lines, thereby erasing pixel cells on two lines. 10. The method of claim 9, wherein said step is performed before all lines of said plasma display panel are operated for image display.