FR2654244A1 - High-speed addressing method and device, for independent holding and addressing of plasma display panels - Google Patents

Abstract

a) High-speed addressing method and device, for independent holding and addressing of plasma display panels; b) method characterised in that it consists in: a. exciting the addressing and hold lines in order to illuminate the cells of pixels in a group of cells; b. applying an erase potential to an addressing cell (A) in order thus to bring about deposition of wall charges in a first coupling cell; c. then applying a potential of predetermined duration between the hold lines which intersect; d. then applying another erase potential to an addressing cell; e. then applying a potential of shorter duration than that of the potential of predetermined duration, between a pair of hold lines which intersect, in order to cause migration of the wall charges from one adjacent pixel cell to the different coupling cell; c) the invention relates to a high-speed addressing method and device, for independent holding and addressing of plasma display panels.

Description

 The present invention relates to independent servicing and addressing of AC plasma display panels. More particularly, the invention relates to a method and a device for high-speed addressing of these panels.

 Plasma display panels or gas discharge panels are well known in the art and generally include a pair of transparent substrates respectively supporting column and row electrodes each covered with a dielectric layer and arranged parallel to a certain distance from each other to form a gap between them in which an ionizable gas is sealed tightly. The substrates are placed so that the electrodes are arranged orthogonally to each other to thereby form points of intersection which in turn define discharge cells where selective discharges can be established to achieve a desired storage or display function. It is also well known to operate these panels by alternating voltages, and in particular to use a write voltage greater than the ignition voltage at a given discharge point defined by a column electrode and a row electrode. selected, to thereby produce a discharge in a selected cell. The discharge produced in the selected cell can be permanently "maintained" by the application of an alternating maintenance voltage (which is in itself insufficient to trigger a discharge ). This technique is based on the wall charges produced on the dielectric layers of the substrates and which, in association with the maintenance voltage, serve to maintain the discharges.

The details of the structure and operation of these gas discharge panels or plasma display panels are described in the
US Patent No. 3,559,190 filed January 26, 1971 by Donald L. Bitzer, et Cie.

 Plasma displays with alternating current have found a very wide field of use because of their excellent optical qualities and their characteristics of flat panels. These qualities have made plasma displays a leader in the flat panel display market. However, plasma panels have conquered a small part of their potential market due to competition from cheaper products using cathode ray tubes.

Various attempts have been made to reduce the costs associated with AC plasma display panel structures. One of the most successful attempts is described in the
US patent 4,772,884 and is entitled "Independent maintenance and addressing plasma display panel" by Weber et Cie (one of the authors of the present invention). This patent describes a modification of the geometry of the electrodes compared to standard alternating plasma technology, modification in which the addressing and maintenance functions are carried out on electrode structures of separate panels. These functions allowed both to implement a different addressing combination and to reduce, by a factor of two, the number of address commands required (compared to the number required for standard AC plasma technology). In addition, the address commands did not have to provide maintenance currents and could therefore be carried out in a much smaller and therefore less expensive form.

 To this end, the present invention relates to a method for controlling an AC plasma display panel ISA, in which the panel comprises at least two groups of end cells, each group of cells comprising a cell of addressing, two vertical coupling cells, two horizontal coupling cells and four pixel cells, horizontal and vertical addressing lines cutting each of the addressing cells, and parallel service lines placed on both sides of each line d addressing and cutting adjacent series of pixels and coupling cells in each group of cells, process characterized in that it consists of a. energize the address and maintenance lines to turn on the pixel cells in a group of cells b. applying an erasure potential to an addressing cell to thereby produce the deposition of wall charges in a first coupling cell c. then apply a potential of predetermined duration between intersecting maintenance lines, one of these maintenance lines intersecting the first coupling cell and the first and second adjacent pixel cells, so as to produce the migration of electrons coming from a discharge from the first coupling cell, to a first adjacent pixel cell to thereby erase this first adjacent pixel cell, the potential of predetermined duration further producing the discharge from the second adjacent pixel cell if the latter is "on" d. then apply another erasure potential to an addressing cell to produce deposition of wall charges in a different coupling cell; summer. then apply a potential of shorter duration than that of the potential of predetermined duration, between a pair of intersecting maintenance lines, to produce the migration of the wall charges in a pixel cell adjacent to the different coupling cell, of so as to erase the pixel cell, this shorter duration potential being insufficient to produce the discharge of another pixel cell adjacent to the different coupling cell.

 As a result, the present invention aims to create an ISA alternative plasma panel having an improved addressing system.

 Another object of the present invention is to create an ISA reciprocating plasma panel having a significantly increased speed addressing system.

 Yet another object of the present invention is to create an ISA alternative plasma panel having an improved addressing system which allows the use of existing panel structures.

 Yet another object of the present invention is to create an ISA alternative plasma display panel which has a driver system for saving energy.

 Yet another object of the present invention is to create an ISA alternating plasma panel which has a variable brightness characteristic.

 Another method of selective erasure is also described in which the application of the shorter-term potential is avoided. We also describe an erasing technique to conserve energy consumption of the panel.

The invention will be described in detail with reference to the accompanying drawings in which
- Figure 1 is an example circuit diagram of an ISA alternating current plasma panel according to the prior art;
- Figure 2 is an enlarged view of a group of cells in Figure 1
- Figure 3 shows a set of waveforms used to erase selected pixels in the AC plasma panel of Figure 1
- Figure 4 shows the plasma spreading effects that occur during Step 1 and Step 2 of a selective erase cycle
- Figure 5 is a sectional view along line 5-5 of Figure 4 (Step 1)
- Figures 6a and 6b are sectional views along line 6-6 in Figure 4 (Step 2), showing the operation of a discharge from Step 2 to erase a pixel cell P1 while a cell pixel P2 is in "on" state
- Figures 6c and 6d are sectional views along line 6-6 of Figure 4 (Step 2), showing the operation of a discharge from Step 2 to erase a pixel cell P1 while a cell pixel P2 is in "off" state
- Figure 7 is a waveform diagram illustrating the general operation of the improved selective erasure method used by the present invention
FIG. 8 illustrates three groups of cells and a set of waveforms causing the establishment of a Step 1 discharge in an addressing cell during the improved selective erasure process
- Figure 9 is similar to Figure 8 except that it illustrates the establishment of a Step 2 discharge later in the waveform diagram
- Figure 10 is similar to Figures 8 and 9 but illustrates the establishment of a Step 1 discharge in a different addressing cell
- Figure 11 illustrates a Step 2 discharge after the Step 1 discharge in Figure 10
- Figure 12 is a general waveform diagram illustrating an alternative embodiment of the selective erase addressing system according to the present invention
- Figure 13 illustrates three groups of cells and the waveforms necessary to implement the alternative addressing system, the waveforms indicating a discharge of Step 1 in an addressing cell
- Figure 14 is similar to Figure 13 but shows the establishment of a Stage 1 discharge after a previous Stage 1 discharge shown in Figure 13
FIG. 15 represents the variant of the addressing system at a later point in the addressing cycle when two discharges of Step 2 are carried out simultaneously
- Figure 16 is a general waveform diagram showing the operation of a two-row erasure process used in an ISA plasma panel for energy saving purposes
- Figure 17 is a representation of a group of cells indicating the operation of the two-row erasure technique
- Figures 18a and 18b are sectional views along line 18-18 of Figure 17, showing the operation of the process of erasing two rows when the pixel cells P1 and
P3 are both on; and
- Figures 18c and 18d are sectional views along line 18-18 of Figure 17, showing the process of erasing two rows when one pixel cell is on while the other is off.

 In Figure 1 is shown schematically a plasma panel with independent maintenance and addressing (hereinafter called "ISA") at 8 x 8, hereinafter called pixels (picture elements). FIG. 2 represents an enlarged view of the area surrounded by the circle 10 in FIG. 1. The enlarged view shown in FIG. 2 represents a basic group with 9 cells which constitutes the repeating block of the ISA geometry.

Each of the nine cells is defined according to the types of electrodes that intersect to define a cell. In plasma panels that existed before ISA technology, all of the cells in the panel were electrically identical and, in fact, all constituted display pixels. On the contrary, in an ISA panel, only four of the nine cells of a group of cells constitute display pixels, namely cells P1, P2, P3 and
P4. These pixel cells are placed at the intersections of four XSa maintenance electrodes,
XSb, YSa and YSb.

In addition to the four pixel cells, there are also five other cells in a cell group. In the center of the group of cells is an addressing cell A which occurs at the intersection of two addressing electrodes XA and YA. There are also four coupling cells: C1, C2
C3 and C4 which occur at the intersections of a service electrode and a addressing electrode.

The coupling cells are divided into two groups according to their relative position with respect to the addressing cell. Cells C1 and C4 are called vertical coupling cells and cells C2 and C3 are called horizontal coupling cells. It is obvious that the terms vertical and horizontal are used simply to designate the orthogonal orientations of the conductors and of the cells, and to facilitate references.

 All the horizontal electrodes of the ISA panel are on a substrate of a panel and are called Y electrodes. All of the vertical electrodes are on an opposite substrate and are called X electrodes. In a well known manner, an ionizable gas is placed between the substrates and ensures the illumination of the selected cell. The X address electrodes include the electrodes 12, 14, 16 and 18 while the Y electrodes include the electrodes 20, 22, 24 and 26. Each X electrode can be selectively addressed by an address and column control circuit 28, and each address line Y can be addressed by a row address control circuit 30.

 The maintenance signals X are supplied by two maintenance generators in phase 32 and 34 each coupled to a pair of parallel maintenance lines (for example 36, 38) connected to these generators. The maintenance lines such as 36, 38 of each pair are short-circuited by short-circuit bars at their two ends, thereby forming a pair of maintenance electrodes. Pairs of alternating maintenance electrodes on a given substrate are grouped by a maintenance bus and connected to one of the two maintenance control pilots. Row maintenance pilots 40 and 42 are connected in the same way to interleaved row maintenance pairs.

Figure 3 shows waveforms that describe a basic cycle of a plasma panel
ISA such as that described in US Patent 4,772,884 indicated above. In a preferred mode of operation, two rows of pixel cells are initially lit. An erasure cycle is then carried out to selectively extinguish the pixels whose image data indicate that they must be extinguished. The waveforms in Figure 3 assume that a "two-row write" cycle has already been performed. Selective erasure of certain desired "lit" pixels involves two steps. The first step triggers the production of a discharge in selected addressing cells along a selected YA addressing electrode (see Figure 2).

This results from the migration of wall charges in vertical coupling cells C1 and C4.

 This is described in more detail by the waveform diagram in Figure 3. Before selective erasure occurs, reset pulses are applied to the address lines X and Y to reset the initial state the wall voltages of the vertical coupling cells C1 and C4. The simultaneous application of maintenance voltages to XSa, XSb and YSA, YSB maintains the lines while the reset pulses cause, in the coupling cells, small discharges which are used to regulate their wall voltages .

Then, address erase pulses 50 and 52 are applied to the address lines XA and YA respectively. This begins Step 1 of the selective erasure procedure and the effect produced is shown in FIG. 4. The erasing and addressing waveforms are polarized so that the electrodes XA and YA are the anode and the cathode. As the electrode XA is the anode, the plasma discharge 54 which occurs in the addressing cell A, spreads mainly towards the vertical coupling cells C1 and C4. The voltage across the intervals of each of the coupling cells C1 and
C4 is such that the spreading of the plasma deposits significant negative charges in these cells. FIG. 5 is a sectional view along line 5-5 in FIG. 4 (Step 1) illustrating the plasma spreading activity during Step 1 and the charges of the interior walls which are present in the coupling cells C1, C4 and the addressing cell
AT.

 Step 2 of the selective erase addressing performs two degrees of selection. This step begins with the drop of erase addressing pulses 50, 52, and the rise of certain selection potentials on the maintenance electrodes. As shown in Figure 5, Step 1 had deposited equal amounts of wall charges in the coupling cells C1 and C4 when the addressing cell A was discharged. When only one maintenance line Y is associated with a selected vertical coupling cell, the unselected vertical coupling cell defined by the maintenance line Y that has not been raised is not not discharge.

 During Step 2, the YS and XS electrodes selected are the anode and the cathode respectively. This polarization allows the plasma produced by the discharge of a coupling cell to spread horizontally away from the cell to penetrate the neighboring pixel cells. The sectional views along line 6-6 in Figure 4 (Step 2) are shown in Figures 6a to 6d and allow a better understanding of the operation of selective erasure. In FIG. 3, the waveforms applied to the maintenance lines X and Y during Step 2 make it possible to select the one of the pixel cells which must be erased.

 In FIG. 6a, it is assumed that Step 1 has already been carried out, that the coupling cell C1 has significant wall charges polarized so as to provide a more positive voltage under the electrode YSa, and that the two cells pixels P1 and P2 are in the lit state. At this stage, we want to delete cell P1 while leaving cell P2 in its on state. Thus, potentials of 100 volts are applied respectively to the XA and XSb electrodes. The wall charges stored in the coupling cell C1 are added to the potential applied to the electrode YSa so as to produce a discharge in the cell C1. At the same time, there is a discharge in the cell P2 but no discharge in cell P1 due to the fact that identical voltages exist on its limit electrodes. The plasma which results from the discharge of cell C1 spreads along the electrode YSa and neutralizes all charges of preexisting walls in cell P1, which causes its erasure. As cell P2 is already discharged, the migration of additional charge states therein has no effect.

In Figure 6c, we assume that there is a different set of initial conditions. In this case, cell P2 is in the off state and cell P1 must be deleted without changing the state of cell P2. As the dielectric located just below the electrode YSa of cell P1 has a positive wall charge, the electrons resulting from a subsequent discharge from the coupling cell CI preferably migrate therein and neutralize the pre-existing wall charge . The charges of preexisting negative walls of the pixel cell P2 tend to repel the electrons resulting from the discharge in the coupling cell C1, and the cell
P2 remains unchanged, so we can see that the maintenance line whose potential was raised during Step 2 of the selective erasure, determines the type of pixel cell which must be erased. Consequently, to erase a selected type of pixel cell, the two maintenance electrodes which define the type of pixel cell selected must be raised simultaneously, immediately after the descent of the addressing pulse XA.

 Due to the reduction in the number of addressing drivers by a factor of 2, the ISA plasma display panel, in its simplest form, is slower by a factor of two for updating a size panel size compared to a standard AC plasma panel. As there is only one addressing driver for each pair of rows or columns of pixels, the two cycles of selective erasure delay the overall operation of the panel. This factor becomes a problem when the number of rows of data or the frame update speed becomes high. If the frame update speed needs to be increased for any reason, the maximum number of rows of data that can be displayed is correspondingly decreased. Similarly, if the number of rows of display data is to be increased beyond a maximum allowed for a given frame update speed, then the frame update speed must be reduced. .

 In addition, it will be noted that after each selective erasing cycle, the preceding ISA AC plasma panels have introduced one or more maintenance cycles to stabilize the cell wall charges. Thus, in addition to the time taken to erase the pixels of each group of cells individually, maintenance pulses are inserted between the erasure pulses and increase the total addressing time. In addition, the duration of the maintenance pulses must be sufficient to ensure the proper discharge of the cells which must remain in the "on" state. The combination of all these phenomena significantly increases the addressing time of the ISA AC plasma panel.

 The speed limit indicated above poses problems. Applications that require the use of a mouse, pointing device, or graphics often require relatively high frame update speeds for continuous information display.

 In addition, the ability to effectively present greyscale images depends, to a large extent, on the speed at which the display image can be updated.

 The present invention modifies the addressing method of an ISA plasma panel according to the prior art by performing multiple addressing cycles in a single "basic" cycle. Figure 7 shows a set of waveforms illustrating an approach of a basic multiple addressing cycle for the ISA AC plasma panel. In summary, the procedure begins by writing all the pixels in four (or more) lines. Then, a type of pixel is erased in a first line, this operation being followed by a half-life cycle then by the erasure of another type of pixel in another line. The second erase is followed by a shorter service signal which can then be maintained for use during subsequent erase events.

 FIG. 7 illustrates the potentials applied to address lines XA of dimension X, to address lines YAm and TAn of dimension Y, and to maintenance pairs XSa, XSb, YSa and YSb. Note that although there are two complete addressing cycles in the waveform diagram in Figure 7, there must be many more under normal conditions. Each addressing cycle includes its own independent Stage 1 and Stage 2 discharges, similar to those described in Figures 5 and 6a to 6d. Figures 8 to 11 illustrate the sequence of events that occur in a basic multiple addressing cycle and are used to illustrate the addressing operation at different times in a basic cycle. In each of Figures 8 to 11, represented a timeline 200 which must be stepped in the waveform diagram to highlight the functioning occurring in the group of cells at the indicated time.

 In FIG. 8, it is initially supposed that four rows of cells of contiguous pixels of the groups of cells 202 and 204 have been described in "on" state. This is achieved by causing the two negative addressing lines YAm and YAn to discharge the associated coupling cells C2 and C3. As a result, the wall charges spread across the adjacent pixel cells preparing them for discharge during a subsequent maintenance cycle.

Thus, the pixel cells P1, P2, P3 and P4 of the group of cells 202 and 204 are "lit".

Initially, as indicated above in the case of the addressing system according to the prior art, a number of reset pulses are applied to the address lines to adjust the wall voltages of the cells of coupling. Then, erase pulses 208 and 210 are applied to the address lines XA and YAm to cause the discharge of the address cell A of the group of cells 204. This discharge causes the plasma 207 to spread in the coupling cells. vertical C1 and C4, and causes the wall charges to settle in them. This essentially represents Step 1 of discharge described above.

 As an example, the initial cell to be erased must be the pixel cell P1; however, any of the other pixel cells can be selected as the first cell to be erased.

Now considering Fig. 9, the timeline 200 has advanced and the addressing pulses 208 and 210 fall in their low state. We now apply a pair of maintenance voltages which must properly influence a plasma created by the discharge of the vertical coupling cell C1 to erase the cell P1.

 As indicated by waveforms 212 and 214, the maintenance lines XSa and YSa are brought to the high state while the maintenance lines XSb and YSb remain in the low state. When the maintenance lines XSa and YSa pass in the high state, the wall charges previously deposited in the coupling cell C1 of the group of cells 204, combine with the maintenance potentials applied and cause the discharge of C1 ( in the manner of Step 2 of discharge described above). The electrons coming from the discharge of the cell C1 migrate towards the pixel cell P1 thus causing the neutralization of its wall charges. The pixel cell P1 does not discharge, despite its previous "on" state, because there is a zero global voltage across its terminals, so that this cell is thus deleted by the migrating electrodes. On the contrary, the pixel cell P2 of the group of cells 204 discharges due to the high level applied to YSa, which is added to the previous wall charges stored in the pixel cell P2.

 The maintenance waveforms 212 and 214 should be long enough to allow the pixel cell P2 to discharge properly during this part of the addressing cycle. If this were not the case, the pixel cell P2 could be inadvertently switched off during the erasure of the pixel cell P1. In the ISA addressing system according to the prior art, the maintenance pulses 212 and 214 are generally followed by two additional maintenance pulses of opposite polarity to completely return to the initial state and stabilize the "lit" pixel cells. "remaining. In this case, however, when the pixel cell P2 discharges, its wall charges change state and are not reset by a subsequent maintenance cycle. Thus, the pixel cell P2 cannot be erased until it is subsequently reset to the initial state by an additional maintenance half-cycle. This will be considered in more detail below.

Referring now to FIG. 10, the second part of addressing of a basic cycle will be considered. Under these circumstances, it is assumed that the erase pulse 216 is applied to the address line XA, and that the erase pulse 218 is applied to the address line XAn. These pulses combine to discharge the addressing cell A of the group of cells 202 by producing the discharge effects of the type of Step 1 described above, to deposit wall voltages in the coupling cells C1 and C4. It will be recalled in FIG. 9 that the application of the maintenance pulses XSa and YSa 212 and 214 cause the discharge of the pixel cell P2 of the group of cells 204. These same maintenance pulses also caused the discharge and the inversion of the state of charge of the walls of all the cells P2 (which were in the on state). So, until a later basic cycle (when the cell wall charges
P2 have been reset by a half-cycle of subsequent maintenance the P2 pixel cells located anywhere on the panel cannot be erased. Thus, we can now erase any of the pixel cells P1, P3 or P4.

 Assuming that one chooses to erase the pixel cell P1 from the group of cells 202, the timeline 200 moves to the point indicated in FIG. 11 and rising levels are applied to the maintenance lines XSa and YSa as indicated by pulses 220 and 222. Consequently, the pixel cell P1 of the group of cells 202 is erased by the spreading of the electrons in its cell structure. The plasma does not spread in the pixel cell P2 because this cell had been discharged at a previous time, and its wall tension is less positive than that of the pixel cell P1. As a result, the plasma preferably spreads towards P1. It will be noted that the maintenance pulses 220 and 220 are of significantly shorter duration than that of the maintenance pulses 212 and 214 because they do not have to ensure the discharge suitable for pixel cell P2. This significantly shortens the addressing time and allows faster panel updating.

 From the above, it can be seen that the two successive erasure pulses make it possible to erase a first type of pixel cell in a group of cells, then to erase subsequently a second type of pixel cell either in the same group of cells is in another group. The only constraint is that a type of pixel cell present on the same maintenance line Y as an erased pixel cell cannot be erased before being reset to the initial state by the maintenance half-cycle. following. As a result, you can erase two different types of pixel cells during each basic cycle, and a second basic cycle is required to erase the other two different types of pixel cells. In any basic cycle, however, can erase as many pixel cells of the same two types as desired, in different cell groups. For each subsequent erase, the erase pulse is followed by a shortened maintenance level pulse.

 A second solution to the problem of reducing the time required to update the state of a pixel is shown in the waveforms in Figure 12. This approach does not have multiple independent addressing cycles per cycle basic. On the contrary, this approach uses multiple independent Stage 1 erasure cycles, and a single occurrence of a Stage 2 cycle. In this approach, all pixel cells erased in a single basic cycle, must be of the same type.

In addition, each erase pulse from Step 1 must be applied to a different address line YA.

 Each erase pulse (Step 1 discharge) shown in Figure 12, a discharge occurs in a selected row of address cells. The plasma from these discharges spreads vertically in vertical coupling cells in the same manner as that illustrated in FIG. 5. The charges of walls deposited in these cells persist until a discharge from Step 2 occurs. happen. When the Step 2 discharge occurs, multiple vertical coupling cell discharges are obtained at different points on the panel. These discharges must produce the spread of plasmas in exactly the same way as that illustrated in FIGS. 6a, 6b, 6c and 6d. The important point is that the selected vertical coupling cells maintain the wall charges deposited in them during Step 1. These cells are thus preset for a future Step 2 discharge which must use wall charges stored in the vertical coupling cells to produce discharges erasing selected pixels.

 Figures 13 to 15 illustrate the sequence of events that occur in a basic multiple addressing cycle such as that described above with reference to Figure 12. In the vicinity of each of the illustrations of the spread plasma are the forms of 'waves that perform addressing event.

In each figure, a time line 300 indicates at what point event waveforms occur.

 In FIG. 13, a row of addressing cells is selectively subjected to a discharge of the type of Step 1 by the application of erasure pulses on the lines XA and YAm. As a result, a discharge occurs in the addressing cell A of the group of cells 304 while the plasma spreads out in the vertical coupling cells C1 and C4.

 In FIG. 14, an identical Step 1 discharge occurs at the intersection of the address line XA and the address line YAn. This next addressing erase pulse occurs shortly after the first erase pulse described with reference to Figure 13.

FIG. 15 represents the application of maintenance potentials to groups of cells 302, 304 and 306 via the maintenance lines
XSa and YSa. These potentials result from discharges
Stage 2 appearing in the coupling cells C1 of the groups of cells 302 and 304. The resulting discharges of Stage 2 cause a migration of the charge in the pixel cell during erasure and also allow the discharge of the cell adjacent pixel if it is in the "on" state. It will be noted that these Stage 2 discharges occur in the same type of vertical coupling cell, namely cell C1. This is due to the fact that all the vertical coupling cells receive the same waveforms of Stage 2, these waveforms determining that of the vertical coupling cells and that of the types of pixel cells that are selected.

 After the discharges from Steps 2, all the selected pixel cells, P1 in this case, selected rows have been updated to their new state either "on" or "off", depending on the image data.

 In the ISA plasma panel, the brightness of the display and the power consumed by it are almost directly proportional. The decrease or increase in one or the other of these parameters must directly affect the other. For example, for an image given on an ISA plasma display panel, if the brightness is increased by a factor of 2. the power consumption must then increase by a factor of 2. The instantaneous power consumption, for a given brightness depends practically linearly on the number of "lit" pixels.

 The AC plasma panels according to the prior art have used several approaches to control the power consumption of the panel, these approaches consisting in adjusting the maintenance frequency or in modulating the "ignition" time of the pixels. The first approach is to adjust the maintenance frequency to achieve fewer maintenance discharges in a defined period of time. The second approach, that is to say the modulation of the "on" duration of the pixels, can be used to obtain practically any desired level of maximum power and maximum brightness. However, the latter approach may add a blink to the display.

 The modulation of the "on" duration of the pixels consists in leaving the pixels "on" in their on state for a certain part of the duration of the frame, then in erasing the entire row of pixels. The fraction of the frame time during which pixels are left "on" determines the brightness and therefore the power consumption of the panel. In an ISA AC plasma panel, the duration modulation technique is implemented by "erasing two rows" of pixels simultaneously, and this technique is somewhat analogous to that of "writing two rows" that 'we use to "light" two rows of pixels at the same time.

The "erase two rows" operation can be performed at any time during the frame duration, and the closer the erase operation occurs to the frame line being written on the side from the AC plasma display panel, the dimmer the display.

The waveforms in Figure 16 represent the "erase two rows" operation. Note that the XA address lines are not affected by this operation. As shown in FIG. 16, the erasure pulses are applied to the address line YAk by the pulse generator YAp. FIG. 17 represents the events which occur from the application of these Y addressing waveforms, and shows that the horizontal coupling cells C2 and
C3 are caused to discharge simultaneously. As can be seen in Figure 16, the waveforms which cause these discharges are arranged so that the electrodes XS are the anodes for the discharge, and that the electrodes YA are the anodes for the discharge, and that the electrodes YA are the cathodes. With this discharge polarity, the plasma spreads vertically towards the display pixels on two sides of the horizontal coupling cells. The maintenance waveforms applied thereafter are set so that there is only a minimum voltage across the gas in any of the "off" pixel cells. On the contrary, in any one of the "lit" pixel cells a voltage very close to the maintenance voltage is applied to the terminals of the gas. We can see in Figures 18a to 18d the difference between the "on" and "off" pixel cells, as well as the effect of this difference.

Each of Figures 18a to 18d shows a sectional view of the panel shown in Figure 17 along line 18-18. FIG. 18a represents the case where the pixels situated above and below a coupling cell are both initially "lit", and further represents the effect produced during the discharge of the coupling cell C2. FIG. 18b indicates the state of the erased pixel cells P1 and
P3 after the discharge has extinguished by itself.

 Figures 18c and 18d further illustrate the case where one of the pixel cells is initially "on" while the other pixel cell is initially "off". The plasma which spreads along the anode of the coupling cell deposits negative charges on the dielectric covering the anode electrode. The quantity of charges deposited depends on the potential at the terminals of the gas in the pixel cell considered.

In the case shown in FIGS. 18c and 18d, the plasma which spreads away from the horizontal coupling cell C2 towards the pixels P1 and P3 must cancel the voltage across the gas in the pixel cell P1 (pixel alight). It can be seen in the diagram of FIG. 18c that there are, in the pixel cell P1, positive wall charges which largely influence the direction of movement of the electrons created by the discharge in the coupling cell C2. As there is no similar state of charge of walls in the pixel cell
P3 "off" ,. plasma does not affect this cell.

 After the plasma dissipates, the pixels that were on "should now have zero voltage across the gas, just like the pixel cells" turned off. "So the pixel cells that were" on "should no longer discharge when maintenance voltages are applied and these pixel cells are now "turned off." Using this technique, the brightness level and power consumption of an ISA AC plasma panel can be varied significantly.

 It will be understood that the above description is given only by way of illustration of the invention.

Many variants and modifications can be imagined by specialists in the subject without departing from the scope of the invention.

Claims (10)

 1. A method of controlling an ISA AC plasma display panel, wherein the panel comprises at least two groups of end cells, each group of cells comprising an address cell (A), two cells vertical coupling cells (C1 C4), two horizontal coupling cells (C2, C3) and four pixel cells, horizontal and vertical address lines cutting each of the address cells, and parallel service lines placed on both sides of each address line and cutting adjacent series of pixels and coupling cells in each group of cells, process characterized in that it consists of a. energize the addressing and maintenance lines for  turn on the pixel cells in a group of  cells b. apply an erasure potential to a cell  addressing (A) to thereby produce the deposit of  wall charges in a first cell of  coupling; vs. then apply a duration potential  predetermined between maintenance lines which are  cut, one of these maintenance lines cutting the  first coupling cell and the first and  second cell of adjacent pixels, so that  produce the migration of electrons from a  discharge of the first coupling cell, towards  a first adjacent pixel cell for  thus erase this first pixel cell  adjacent, the predetermined duration potential  further producing the discharge of the second  adjacent pixel cell if this is  "on" d. then apply another erasure potential to  an addressing cell to produce filing  wall charges in a coupling cell  different ; summer. then apply a shorter duration potential  than that of the predetermined duration potential,  between a pair of maintenance lines which  cut, to produce the migration of the charges of  walls in a pixel cell adjacent to the  different coupling cell, so that  erase the pixel cell, that more potential  short duration being insufficient to produce the  discharge from another pixel cell adjacent to  the different coupling cell.  2. Method according to claim 1. characterized in that the erasure potential is applied to an addressing cell in one group of cells, and in that another erasure potential is applied to an addressing cell in another group of cells.  3. Method according to claim 2, characterized in that parallel and adjacent maintenance lines are connected in pairs, each pair lying between parallel address lines and intersecting adjacent series of pixels and coupling cells in adjacent cell groups, and in that the predetermined and shorter duration potentials are applied to adjacent and parallel pairs of maintenance lines.  4. Method according to claim 3, characterized in that a type of pixel cell of a group of cells is defined by the intersection of one of a first pair of horizontally connected maintenance lines, and of one of a first pair of maintenance lines connected vertically; in that a pixel cell of the same type from another group of cells is defined by the intersection of the other of the first pair of horizontally connected maintenance lines, and the first line of the first pair of maintenance lines connected vertically; and in that the method further comprises f. sequentially erase pixel cells from  same type in different cell groups.  5. Method according to claim 1, characterized in that a type of pixel cell of a group of cells is defined by the intersection of one of a first pair of horizontally connected maintenance lines, and of one of a first pair of maintenance lines connected vertically; in that an identical type of pixel cell of another group of cells is defined by the intersection of the other of the first pair of horizontally connected maintenance lines, and the first line of the first pair of maintenance lines connected vertically; and in that the method further comprises f. sequentially erase pixel cells from  same type in different cell groups.  6. Method according to claim 1, characterized in that a type of pixel cell of a group of cells is defined by the intersection of one of a first pair of horizontally connected maintenance lines, and of one of a first pair of maintenance lines connected vertically in that an identical type of pixel cell of another group of cells is defined by the intersection of the other of the first pair of lines d 'maintenance connected horizontally, and the first line of the first pair of maintenance lines connected vertically; and in that this method produces the erasure of different types of pixel cells, this method comprising the additional steps cl and dl in place of steps c and d, these steps consisting in: cl. then apply an erasure potential to a  addressing cell to produce the deposit of  wall charges in another cell of  vertical coupling as the first cell of  vertical coupling; and dl. then apply a duration potential  predetermined between the maintenance lines which are  cut defining a type pixel cell  different in the vicinity of the other cell of  vertical coupling, to produce the migration of  electrons resulting from the discharge of the other  coupling cell to the pixel cell of  different type, so as to erase this cell  different type of pixel, this potential  further producing the discharge of a  pixel "lit" adjacent to the other cell of  coupling.  The method of controlling an ISA AC plasma display panel according to claim 1, wherein the panel comprises at least two groups of cells, each of these groups of cells comprising an address cell, two cells. coupling cells arranged in a network on both sides of the address cell, two horizontal coupling cells arranged in a network on both sides of the address cell and four pixel cells, horizontal and vertical address lines intersecting each cell addressing lines and maintenance lines placed on both sides of each addressing line, each maintenance line intersecting a series of pixel cells and coupling cells, each pixel cell having a type designation P1 to P4 and the cells of pixels of the same type in adjacent groups of cells being defined as the cells located at the intersections of a pair of parallel service lines els and adjacent and an orthogonal maintenance line, characterized in that it consists of: a. energize the addressing and maintenance lines for  light up pixel cells in groups of  cells; b. apply a series of erasure potentials to  addressing cells in cell groups  to produce the discharge of these cells  addressing and depositing wall loads in  coupling cells adjacent to cells  pixels of the same type; and c. apply a potential of predetermined duration to a  pair of maintenance lines that cut  same-type pixel cells and the cells of  coupling, to discharge these coupling cells,  which allows electrons to migrate to  same type pixel cells to clear  these pixel cells.  8. Method according to claim 7, characterized in that the method of predetermined duration produces the discharge of an "erased" pixel cell not erased adjacent to each coupling cell.  9. A method of controlling an ISA alternating current plasma display panel according to claim 1, in which the panel comprises a certain number of groups of cells, these groups being arranged in networks of lines across the panel of display, each group of cells comprising an addressing cell, two vertical coupling cells, two horizontal coupling cells and four pixel cells, horizontal and vertical addressing electrodes intersecting each address cell, and connected pairs of 'parallel maintenance electrodes on both sides of each address line, each of the pairs of maintenance electrodes intersecting parallel and adjacent series of pixel cells and coupling cells in adjacent cell groups, method characterized by what it consists of: a. excite the address electrodes which cut the  addressing cells of all groups of  cells of a line, to discharge the  addressing cells and drop loads of  walls in the horizontal coupling cells  from each group of cells in the row; and B. apply maintenance potentials to the electrodes  maintenance lines that cut cells  of pixels in each group of cells along  the line and further apply potentials  service at all service electrodes  vertical, thereby erasing all cells  of pixels of each group of cells along  the line, which allows to erase two worthy  pixels.  10. The method of claim 9, characterized in that the erasing step b is performed before all the lines of the plasma display panel are scanned to display an image.